Module Name: src
Committed By: msaitoh
Date: Wed Apr 24 10:21:23 UTC 2019
Modified Files:
src/sys/dev/pci: if_wm.c
Log Message:
KNF. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.632 -r1.633 src/sys/dev/pci/if_wm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_wm.c
diff -u src/sys/dev/pci/if_wm.c:1.632 src/sys/dev/pci/if_wm.c:1.633
--- src/sys/dev/pci/if_wm.c:1.632 Mon Mar 25 05:32:01 2019
+++ src/sys/dev/pci/if_wm.c Wed Apr 24 10:21:22 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.632 2019/03/25 05:32:01 msaitoh Exp $ */
+/* $NetBSD: if_wm.c,v 1.633 2019/04/24 10:21:22 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -82,7 +82,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.632 2019/03/25 05:32:01 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.633 2019/04/24 10:21:22 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -546,10 +546,10 @@ struct wm_softc {
int sc_nqueues;
struct wm_queue *sc_queue;
- u_int sc_tx_process_limit; /* Tx processing repeat limit in softint */
- u_int sc_tx_intr_process_limit; /* Tx processing repeat limit in H/W intr */
- u_int sc_rx_process_limit; /* Rx processing repeat limit in softint */
- u_int sc_rx_intr_process_limit; /* Rx processing repeat limit in H/W intr */
+ u_int sc_tx_process_limit; /* Tx proc. repeat limit in softint */
+ u_int sc_tx_intr_process_limit; /* Tx proc. repeat limit in H/W intr */
+ u_int sc_rx_process_limit; /* Rx proc. repeat limit in softint */
+ u_int sc_rx_intr_process_limit; /* Rx proc. repeat limit in H/W intr */
int sc_affinity_offset;
@@ -603,9 +603,12 @@ struct wm_softc {
struct wm_nvmop nvm;
};
-#define WM_CORE_LOCK(_sc) if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
-#define WM_CORE_UNLOCK(_sc) if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
-#define WM_CORE_LOCKED(_sc) (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
+#define WM_CORE_LOCK(_sc) \
+ if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
+#define WM_CORE_UNLOCK(_sc) \
+ if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
+#define WM_CORE_LOCKED(_sc) \
+ (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
#define WM_RXCHAIN_RESET(rxq) \
do { \
@@ -641,7 +644,7 @@ do { \
#define CSR_WRITE(sc, reg, val) \
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
#define CSR_WRITE_FLUSH(sc) \
- (void) CSR_READ((sc), WMREG_STATUS)
+ (void)CSR_READ((sc), WMREG_STATUS)
#define ICH8_FLASH_READ32(sc, reg) \
bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, \
@@ -1924,7 +1927,7 @@ wm_attach(device_t parent, device_t self
preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
- /* power up chip */
+ /* Power up chip */
if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL))
&& error != EOPNOTSUPP) {
aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
@@ -1984,7 +1987,7 @@ alloc_retry:
goto alloc_retry;
}
} else if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
- wm_adjust_qnum(sc, 0); /* must not use multiqueue */
+ wm_adjust_qnum(sc, 0); /* Must not use multiqueue */
error = wm_setup_legacy(sc);
if (error) {
pci_intr_release(sc->sc_pc, sc->sc_intrs,
@@ -1996,7 +1999,7 @@ alloc_retry:
goto alloc_retry;
}
} else {
- wm_adjust_qnum(sc, 0); /* must not use multiqueue */
+ wm_adjust_qnum(sc, 0); /* Must not use multiqueue */
error = wm_setup_legacy(sc);
if (error) {
pci_intr_release(sc->sc_pc, sc->sc_intrs,
@@ -2304,7 +2307,7 @@ alloc_retry:
* NVM_SIZE_MULTIPLIER;
/* It is size in bytes, we want words */
sc->sc_nvm_wordsize /= 2;
- /* assume 2 banks */
+ /* Assume 2 banks */
sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2;
sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET;
sc->phy.acquire = wm_get_swflag_ich8lan;
@@ -2583,7 +2586,7 @@ alloc_retry:
sc->sc_flags &= ~WM_F_WOL;
break;
case PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3:
- /* if quad port adapter, disable WoL on all but port A */
+ /* If quad port adapter, disable WoL on all but port A */
if (sc->sc_funcid != 0)
sc->sc_flags &= ~WM_F_WOL;
break;
@@ -2596,7 +2599,7 @@ alloc_retry:
case PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER:
case PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER:
case PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER:
- /* if quad port adapter, disable WoL on all but port A */
+ /* If quad port adapter, disable WoL on all but port A */
if (sc->sc_funcid != 0)
sc->sc_flags &= ~WM_F_WOL;
break;
@@ -3134,11 +3137,9 @@ wm_watchdog(struct ifnet *ifp)
wm_watchdog_txq(ifp, txq, &hang_queue);
}
- /*
- * IF any of queues hanged up, reset the interface.
- */
+ /* IF any of queues hanged up, reset the interface. */
if (hang_queue != 0) {
- (void) wm_init(ifp);
+ (void)wm_init(ifp);
/*
* There are still some upper layer processing which call
@@ -3156,9 +3157,9 @@ wm_watchdog_txq(struct ifnet *ifp, struc
mutex_enter(txq->txq_lock);
if (txq->txq_sending &&
- time_uptime - txq->txq_lastsent > wm_watchdog_timeout) {
+ time_uptime - txq->txq_lastsent > wm_watchdog_timeout)
wm_watchdog_txq_locked(ifp, txq, hang);
- }
+
mutex_exit(txq->txq_lock);
}
@@ -3196,28 +3197,28 @@ wm_watchdog_txq_locked(struct ifnet *ifp
#ifdef WM_DEBUG
for (i = txq->txq_sdirty; i != txq->txq_snext;
i = WM_NEXTTXS(txq, i)) {
- txs = &txq->txq_soft[i];
- printf("txs %d tx %d -> %d\n",
- i, txs->txs_firstdesc, txs->txs_lastdesc);
- for (j = txs->txs_firstdesc; ; j = WM_NEXTTX(txq, j)) {
- if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
- printf("\tdesc %d: 0x%" PRIx64 "\n", j,
- txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
- printf("\t %#08x%08x\n",
- txq->txq_nq_descs[j].nqtx_data.nqtxd_fields,
- txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen);
- } else {
- printf("\tdesc %d: 0x%" PRIx64 "\n", j,
- (uint64_t)txq->txq_descs[j].wtx_addr.wa_high << 32 |
- txq->txq_descs[j].wtx_addr.wa_low);
- printf("\t %#04x%02x%02x%08x\n",
- txq->txq_descs[j].wtx_fields.wtxu_vlan,
- txq->txq_descs[j].wtx_fields.wtxu_options,
- txq->txq_descs[j].wtx_fields.wtxu_status,
- txq->txq_descs[j].wtx_cmdlen);
- }
- if (j == txs->txs_lastdesc)
- break;
+ txs = &txq->txq_soft[i];
+ printf("txs %d tx %d -> %d\n",
+ i, txs->txs_firstdesc, txs->txs_lastdesc);
+ for (j = txs->txs_firstdesc; ; j = WM_NEXTTX(txq, j)) {
+ if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
+ printf("\tdesc %d: 0x%" PRIx64 "\n", j,
+ txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
+ printf("\t %#08x%08x\n",
+ txq->txq_nq_descs[j].nqtx_data.nqtxd_fields,
+ txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen);
+ } else {
+ printf("\tdesc %d: 0x%" PRIx64 "\n", j,
+ (uint64_t)txq->txq_descs[j].wtx_addr.wa_high << 32 |
+ txq->txq_descs[j].wtx_addr.wa_low);
+ printf("\t %#04x%02x%02x%08x\n",
+ txq->txq_descs[j].wtx_fields.wtxu_vlan,
+ txq->txq_descs[j].wtx_fields.wtxu_options,
+ txq->txq_descs[j].wtx_fields.wtxu_status,
+ txq->txq_descs[j].wtx_cmdlen);
+ }
+ if (j == txs->txs_lastdesc)
+ break;
}
}
#endif
@@ -3352,7 +3353,7 @@ static int
wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
{
struct wm_softc *sc = ifp->if_softc;
- struct ifreq *ifr = (struct ifreq *) data;
+ struct ifreq *ifr = (struct ifreq *)data;
struct ifaddr *ifa = (struct ifaddr *)data;
struct sockaddr_dl *sdl;
int s, error;
@@ -3394,7 +3395,7 @@ wm_ioctl(struct ifnet *ifp, u_long cmd,
sdl = satosdl(ifp->if_dl->ifa_addr);
(void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen);
- /* unicast address is first multicast entry */
+ /* Unicast address is the first multicast entry */
wm_set_filter(sc);
error = 0;
WM_CORE_UNLOCK(sc);
@@ -3622,11 +3623,11 @@ wm_mchash(struct wm_softc *sc, const uin
|| (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
|| (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
- (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
+ (((uint16_t)enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
return (hash & 0x3ff);
}
hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
- (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
+ (((uint16_t)enaddr[5]) << hi_shift[sc->sc_mchash_type]);
return (hash & 0xfff);
}
@@ -3730,7 +3731,7 @@ wm_set_filter(struct wm_softc *sc)
ralmax = 1;
break;
default:
- /* available SHRA + RAR[0] */
+ /* Available SHRA + RAR[0] */
ralmax = i + 1;
}
} else
@@ -4518,7 +4519,7 @@ wm_initialize_hardware_bits(struct wm_so
CSR_WRITE(sc, WMREG_RFCTL, reg);
break;
case WM_T_82574:
- /* use extened Rx descriptor. */
+ /* Use extened Rx descriptor. */
reg = CSR_READ(sc, WMREG_RFCTL);
reg |= WMREG_RFCTL_EXSTEN;
CSR_WRITE(sc, WMREG_RFCTL, reg);
@@ -4652,20 +4653,17 @@ wm_flush_desc_rings(struct wm_softc *sc)
delay(150);
reg = CSR_READ(sc, WMREG_RXDCTL(0));
- /* zero the lower 14 bits (prefetch and host thresholds) */
+ /* Zero the lower 14 bits (prefetch and host thresholds) */
reg &= 0xffffc000;
/*
- * update thresholds: prefetch threshold to 31, host threshold
+ * Update thresholds: prefetch threshold to 31, host threshold
* to 1 and make sure the granularity is "descriptors" and not
* "cache lines"
*/
reg |= (0x1f | (1 << 8) | RXDCTL_GRAN);
CSR_WRITE(sc, WMREG_RXDCTL(0), reg);
- /*
- * momentarily enable the RX ring for the changes to take
- * effect
- */
+ /* Momentarily enable the RX ring for the changes to take effect */
CSR_WRITE(sc, WMREG_RCTL, rctl | RCTL_EN);
CSR_WRITE_FLUSH(sc);
delay(150);
@@ -4947,7 +4945,7 @@ wm_reset(struct wm_softc *sc)
if (phy_reset != 0)
wm_get_cfg_done(sc);
- /* reload EEPROM */
+ /* Reload EEPROM */
switch (sc->sc_type) {
case WM_T_82542_2_0:
case WM_T_82542_2_1:
@@ -5044,7 +5042,7 @@ wm_reset(struct wm_softc *sc)
if ((sc->sc_type == WM_T_82580)
|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
- /* clear global device reset status bit */
+ /* Clear global device reset status bit */
CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
}
@@ -5068,7 +5066,7 @@ wm_reset(struct wm_softc *sc)
CSR_WRITE(sc, WMREG_KABGTXD, reg);
}
- /* reload sc_ctrl */
+ /* Reload sc_ctrl */
sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
wm_set_eee(sc);
@@ -5093,7 +5091,7 @@ wm_reset(struct wm_softc *sc)
wm_pll_workaround_i210(sc);
if (sc->sc_type == WM_T_80003) {
- /* default to TRUE to enable the MDIC W/A */
+ /* Default to TRUE to enable the MDIC W/A */
sc->sc_flags |= WM_F_80003_MDIC_WA;
rv = wm_kmrn_readreg(sc,
@@ -5481,9 +5479,7 @@ wm_setup_msix(struct wm_softc *sc)
intr_idx++;
}
- /*
- * LINK
- */
+ /* LINK */
intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
sizeof(intrbuf));
#ifdef WM_MPSAFE
@@ -5502,7 +5498,7 @@ wm_setup_msix(struct wm_softc *sc)
goto fail;
}
- /* keep default affinity to LINK interrupt */
+ /* Keep default affinity to LINK interrupt */
aprint_normal_dev(sc->sc_dev,
"for LINK interrupting at %s\n", intrstr);
sc->sc_ihs[intr_idx] = vih;
@@ -5530,9 +5526,7 @@ wm_unset_stopping_flags(struct wm_softc
KASSERT(WM_CORE_LOCKED(sc));
- /*
- * must unset stopping flags in ascending order.
- */
+ /* Must unset stopping flags in ascending order. */
for (i = 0; i < sc->sc_nqueues; i++) {
struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
@@ -5558,9 +5552,7 @@ wm_set_stopping_flags(struct wm_softc *s
sc->sc_core_stopping = true;
- /*
- * must set stopping flags in ascending order.
- */
+ /* Must set stopping flags in ascending order. */
for (i = 0; i < sc->sc_nqueues; i++) {
struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
@@ -5576,7 +5568,7 @@ wm_set_stopping_flags(struct wm_softc *s
}
/*
- * write interrupt interval value to ITR or EITR
+ * Write interrupt interval value to ITR or EITR
*/
static void
wm_itrs_writereg(struct wm_softc *sc, struct wm_queue *wmq)
@@ -5728,7 +5720,7 @@ wm_init_locked(struct ifnet *ifp)
/* Cancel any pending I/O. */
wm_stop_locked(ifp, 0);
- /* update statistics before reset */
+ /* Update statistics before reset */
ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
@@ -5818,9 +5810,7 @@ wm_init_locked(struct ifnet *ifp)
if (error)
goto out;
- /*
- * Clear out the VLAN table -- we don't use it (yet).
- */
+ /* Clear out the VLAN table -- we don't use it (yet). */
CSR_WRITE(sc, WMREG_VET, 0);
if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
trynum = 10; /* Due to hw errata */
@@ -5950,7 +5940,7 @@ wm_init_locked(struct ifnet *ifp)
CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
/*
- * workaround issue with spurious interrupts
+ * Workaround issue with spurious interrupts
* in MSI-X mode.
* At wm_initialize_hardware_bits(), sc_nintrs has not
* initialized yet. So re-initialize WMREG_RFCTL here.
@@ -6158,9 +6148,7 @@ wm_init_locked(struct ifnet *ifp)
sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
| __SHIFTIN(sc->sc_mchash_type, RCTL_MO);
- /*
- * 82574 use one buffer extended Rx descriptor.
- */
+ /* 82574 use one buffer extended Rx descriptor. */
if (sc->sc_type == WM_T_82574)
sc->sc_rctl |= RCTL_DTYP_ONEBUF;
@@ -6335,7 +6323,7 @@ wm_stop_locked(struct ifnet *ifp, int di
struct wm_queue *wmq = &sc->sc_queue[qidx];
struct wm_txqueue *txq = &wmq->wmq_txq;
mutex_enter(txq->txq_lock);
- txq->txq_sending = false; /* ensure watchdog disabled */
+ txq->txq_sending = false; /* Ensure watchdog disabled */
for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
txs = &txq->txq_soft[i];
if (txs->txs_mbuf != NULL) {
@@ -6737,9 +6725,7 @@ wm_alloc_txrx_queues(struct wm_softc *sc
goto fail_0;
}
- /*
- * For transmission
- */
+ /* For transmission */
error = 0;
tx_done = 0;
for (i = 0; i < sc->sc_nqueues; i++) {
@@ -6801,9 +6787,7 @@ wm_alloc_txrx_queues(struct wm_softc *sc
if (error)
goto fail_1;
- /*
- * For recieve
- */
+ /* For recieve */
error = 0;
rx_done = 0;
for (i = 0; i < sc->sc_nqueues; i++) {
@@ -6918,7 +6902,7 @@ wm_free_txrx_queues(struct wm_softc *sc)
WM_Q_EVCNT_DETACH(txq, underrun, txq, i);
#endif /* WM_EVENT_COUNTERS */
- /* drain txq_interq */
+ /* Drain txq_interq */
while ((m = pcq_get(txq->txq_interq)) != NULL)
m_freem(m);
pcq_destroy(txq->txq_interq);
@@ -6982,7 +6966,7 @@ wm_init_tx_regs(struct wm_softc *sc, str
/* XXX should update with AIM? */
CSR_WRITE(sc, WMREG_TIDV, wmq->wmq_itr / 4);
if (sc->sc_type >= WM_T_82540) {
- /* should be same */
+ /* Should be the same */
CSR_WRITE(sc, WMREG_TADV, wmq->wmq_itr / 4);
}
@@ -7230,9 +7214,7 @@ wm_tx_offload(struct wm_softc *sc, struc
break;
default:
- /*
- * Don't support this protocol or encapsulation.
- */
+ /* Don't support this protocol or encapsulation. */
*fieldsp = 0;
*cmdp = 0;
return 0;
@@ -7356,7 +7338,7 @@ wm_tx_offload(struct wm_softc *sc, struc
tucs = WTX_TCPIP_TUCSS(offset) |
WTX_TCPIP_TUCSO(offset +
M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
- WTX_TCPIP_TUCSE(0) /* rest of packet */;
+ WTX_TCPIP_TUCSE(0) /* Rest of packet */;
} else if ((m0->m_pkthdr.csum_flags &
(M_CSUM_TCPv6 | M_CSUM_UDPv6 | M_CSUM_TSOv6)) != 0) {
WM_Q_EVCNT_INCR(txq, tusum6);
@@ -7364,12 +7346,12 @@ wm_tx_offload(struct wm_softc *sc, struc
tucs = WTX_TCPIP_TUCSS(offset) |
WTX_TCPIP_TUCSO(offset +
M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
- WTX_TCPIP_TUCSE(0) /* rest of packet */;
+ WTX_TCPIP_TUCSE(0) /* Rest of packet */;
} else {
/* Just initialize it to a valid TCP context. */
tucs = WTX_TCPIP_TUCSS(offset) |
WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
- WTX_TCPIP_TUCSE(0) /* rest of packet */;
+ WTX_TCPIP_TUCSE(0) /* Rest of packet */;
}
/*
@@ -7460,9 +7442,7 @@ wm_transmit(struct ifnet *ifp, struct mb
return ENOBUFS;
}
- /*
- * XXXX NOMPSAFE: ifp->if_data should be percpu.
- */
+ /* XXX NOMPSAFE: ifp->if_data should be percpu. */
ifp->if_obytes += m->m_pkthdr.len;
if (m->m_flags & M_MCAST)
ifp->if_omcasts++;
@@ -7594,7 +7574,7 @@ retry:
m_freem(m0);
continue;
}
- /* Short on resources, just stop for now. */
+ /* Short on resources, just stop for now. */
DPRINTF(WM_DEBUG_TX,
("%s: TX: dmamap load failed: %d\n",
device_xname(sc->sc_dev), error));
@@ -8067,9 +8047,7 @@ wm_nq_transmit(struct ifnet *ifp, struct
return ENOBUFS;
}
- /*
- * XXXX NOMPSAFE: ifp->if_data should be percpu.
- */
+ /* XXX NOMPSAFE: ifp->if_data should be percpu. */
ifp->if_obytes += m->m_pkthdr.len;
if (m->m_flags & M_MCAST)
ifp->if_omcasts++;
@@ -8273,7 +8251,7 @@ retry:
/* Initialize the first transmit descriptor. */
nexttx = txq->txq_next;
if (!do_csum) {
- /* setup a legacy descriptor */
+ /* Setup a legacy descriptor */
wm_set_dma_addr(&txq->txq_descs[nexttx].wtx_addr,
dmamap->dm_segs[0].ds_addr);
txq->txq_descs[nexttx].wtx_cmdlen =
@@ -8290,7 +8268,7 @@ retry:
dcmdlen = 0;
} else {
- /* setup an advanced data descriptor */
+ /* Setup an advanced data descriptor */
txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr =
htole64(dmamap->dm_segs[0].ds_addr);
KASSERT((dmamap->dm_segs[0].ds_len & cmdlen) == 0);
@@ -8311,7 +8289,7 @@ retry:
lasttx = nexttx;
nexttx = WM_NEXTTX(txq, nexttx);
/*
- * fill in the next descriptors. legacy or advanced format
+ * Fill in the next descriptors. legacy or advanced format
* is the same here
*/
for (seg = 1; seg < dmamap->dm_nsegs;
@@ -8452,7 +8430,7 @@ wm_txeof(struct wm_txqueue *txq, u_int l
return false;
txq->txq_flags &= ~WM_TXQ_NO_SPACE;
- /* for ALTQ and legacy(not use multiqueue) ethernet controller */
+ /* For ALTQ and legacy(not use multiqueue) ethernet controller */
if (wmq->wmq_id == 0)
ifp->if_flags &= ~IFF_OACTIVE;
@@ -8681,7 +8659,7 @@ wm_rxdesc_has_errors(struct wm_rxqueue *
{
struct wm_softc *sc = rxq->rxq_sc;
- /* XXXX missing error bit for newqueue? */
+ /* XXX missing error bit for newqueue? */
if (wm_rxdesc_is_set_error(sc, errors,
WRX_ER_CE | WRX_ER_SE | WRX_ER_SEQ | WRX_ER_CXE | WRX_ER_RXE,
EXTRXC_ERROR_CE | EXTRXC_ERROR_SE | EXTRXC_ERROR_SEQ
@@ -9043,7 +9021,7 @@ wm_linkintr_gmii(struct wm_softc *sc, ui
break;
default:
/*
- * fiber?
+ * Fiber?
* Shoud not enter here.
*/
printf("unknown media (%x)\n", active);
@@ -9763,7 +9741,7 @@ wm_gmii_reset(struct wm_softc *sc)
#endif
delay(20*1000); /* XXX extra delay to get PHY ID? */
break;
- case WM_T_82544: /* reset 10000us */
+ case WM_T_82544: /* Reset 10000us */
case WM_T_82540:
case WM_T_82545:
case WM_T_82545_3:
@@ -9773,7 +9751,7 @@ wm_gmii_reset(struct wm_softc *sc)
case WM_T_82541_2:
case WM_T_82547:
case WM_T_82547_2:
- case WM_T_82571: /* reset 100us */
+ case WM_T_82571: /* Reset 100us */
case WM_T_82572:
case WM_T_82573:
case WM_T_82574:
@@ -9786,7 +9764,7 @@ wm_gmii_reset(struct wm_softc *sc)
case WM_T_I211:
case WM_T_82583:
case WM_T_80003:
- /* generic reset */
+ /* Generic reset */
CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
CSR_WRITE_FLUSH(sc);
delay(20000);
@@ -9798,7 +9776,7 @@ wm_gmii_reset(struct wm_softc *sc)
|| (sc->sc_type == WM_T_82541_2)
|| (sc->sc_type == WM_T_82547)
|| (sc->sc_type == WM_T_82547_2)) {
- /* workaround for igp are done in igp_reset() */
+ /* Workaround for igp are done in igp_reset() */
/* XXX add code to set LED after phy reset */
}
break;
@@ -9810,7 +9788,7 @@ wm_gmii_reset(struct wm_softc *sc)
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
case WM_T_PCH_CNP:
- /* generic reset */
+ /* Generic reset */
CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
CSR_WRITE_FLUSH(sc);
delay(100);
@@ -9829,7 +9807,7 @@ wm_gmii_reset(struct wm_softc *sc)
/* get_cfg_done */
wm_get_cfg_done(sc);
- /* extra setup */
+ /* Extra setup */
switch (sc->sc_type) {
case WM_T_82542_2_0:
case WM_T_82542_2_1:
@@ -9855,7 +9833,7 @@ wm_gmii_reset(struct wm_softc *sc)
case WM_T_I210:
case WM_T_I211:
case WM_T_80003:
- /* null */
+ /* Null */
break;
case WM_T_82541:
case WM_T_82547:
@@ -10260,13 +10238,13 @@ wm_gmii_mediainit(struct wm_softc *sc, p
CSR_WRITE_FLUSH(sc);
delay(300*1000); /* XXX too long */
- /* from 1 to 8 */
+ /* From 1 to 8 */
for (i = 1; i < 8; i++)
mii_attach(sc->sc_dev, &sc->sc_mii,
0xffffffff, i, MII_OFFSET_ANY,
MIIF_DOPAUSE);
- /* restore previous sfp cage power state */
+ /* Restore previous sfp cage power state */
CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
}
}
@@ -10730,7 +10708,7 @@ wm_gmii_i80003_readreg(device_t dev, int
uint16_t temp, temp2;
int rv = 0;
- if (phy != 1) /* only one PHY on kumeran bus */
+ if (phy != 1) /* Only one PHY on kumeran bus */
return -1;
if (sc->phy.acquire(sc)) {
@@ -10788,7 +10766,7 @@ wm_gmii_i80003_writereg(device_t dev, in
int page_select, rv;
uint16_t temp, temp2;
- if (phy != 1) /* only one PHY on kumeran bus */
+ if (phy != 1) /* Only one PHY on kumeran bus */
return -1;
if (sc->phy.acquire(sc)) {
@@ -11388,9 +11366,7 @@ wm_gmii_statchg(struct ifnet *ifp)
sc->sc_tctl &= ~TCTL_COLD(0x3ff);
sc->sc_fcrtl &= ~FCRTL_XONE;
- /*
- * Get flow control negotiation result.
- */
+ /* Get flow control negotiation result. */
if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
(mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
@@ -12758,7 +12734,7 @@ wm_nvm_valid_bank_detect_ich8lan(struct
bank1_offset = sc->sc_ich8_flash_bank_size * 2;
act_offset = ICH_NVM_SIG_WORD * 2;
- /* set bank to 0 in case flash read fails. */
+ /* Set bank to 0 in case flash read fails. */
*bank = 0;
/* Check bank 0 */
@@ -12873,7 +12849,7 @@ wm_ich8_cycle_init(struct wm_softc *sc)
error = 0;
} else {
/*
- * otherwise poll for sometime so the current cycle has a
+ * Otherwise poll for sometime so the current cycle has a
* chance to end before giving up.
*/
for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
@@ -13880,16 +13856,14 @@ wm_get_nvm_80003(struct wm_softc *sc)
if ((rv = wm_get_swfw_semaphore(sc, SWFW_EEP_SM)) != 0) {
aprint_error_dev(sc->sc_dev,
- "%s: failed to get semaphore(SWFW)\n",
- __func__);
+ "%s: failed to get semaphore(SWFW)\n", __func__);
return rv;
}
if (((sc->sc_flags & WM_F_LOCK_EECD) != 0)
&& (rv = wm_get_eecd(sc)) != 0) {
aprint_error_dev(sc->sc_dev,
- "%s: failed to get semaphore(EECD)\n",
- __func__);
+ "%s: failed to get semaphore(EECD)\n", __func__);
wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
return rv;
}
@@ -14175,7 +14149,7 @@ wm_check_mng_mode(struct wm_softc *sc)
rv = wm_check_mng_mode_generic(sc);
break;
default:
- /* noting to do */
+ /* Noting to do */
rv = 0;
break;
}
@@ -14306,7 +14280,7 @@ wm_phy_resetisblocked(struct wm_softc *s
return false;
break;
default:
- /* no problem */
+ /* No problem */
break;
}
@@ -15037,7 +15011,7 @@ wm_enable_wakeup(struct wm_softc *sc)
(sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP))
wm_suspend_workarounds_ich8lan(sc);
-#if 0 /* for the multicast packet */
+#if 0 /* For the multicast packet */
reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG;
reg |= WUFC_MC;
CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE);
@@ -15206,7 +15180,7 @@ wm_set_eee_i350(struct wm_softc *sc)
ipcnfg = CSR_READ(sc, WMREG_IPCNFG);
eeer = CSR_READ(sc, WMREG_EEER);
- /* enable or disable per user setting */
+ /* Enable or disable per user setting */
if ((ec->ec_capenable & ETHERCAP_EEE) != 0) {
ipcnfg |= ipcnfg_mask;
eeer |= eeer_mask;
@@ -15505,7 +15479,7 @@ wm_hv_phy_workarounds_ich8lan(struct wm_
if (rv)
goto release;
- /* set MSE higher to enable link to stay up when noise is high */
+ /* Set MSE higher to enable link to stay up when noise is high */
rv = wm_write_emi_reg_locked(dev, I82577_MSE_THRESHOLD, 0x0034);
release:
sc->phy.release(sc);
@@ -15580,11 +15554,11 @@ wm_lv_phy_workarounds_ich8lan(struct wm_
rv = sc->phy.acquire(sc);
if (rv != 0)
return rv;
- /* set MSE higher to enable link to stay up when noise is high */
+ /* Set MSE higher to enable link to stay up when noise is high */
rv = wm_write_emi_reg_locked(dev, I82579_MSE_THRESHOLD, 0x0034);
if (rv != 0)
goto release;
- /* drop link after 5 times MSE threshold was reached */
+ /* Drop link after 5 times MSE threshold was reached */
rv = wm_write_emi_reg_locked(dev, I82579_MSE_LINK_DOWN, 0x0005);
release:
sc->phy.release(sc);
@@ -15774,7 +15748,7 @@ wm_link_stall_workaround_hv(struct wm_so
if ((phyreg & BMCR_LOOP) != 0)
return 0;
- /* check if link is up and at 1Gbps */
+ /* Check if link is up and at 1Gbps */
wm_gmii_hv_readreg(sc->sc_dev, 2, BM_CS_STATUS, &phyreg);
phyreg &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED
| BM_CS_STATUS_SPEED_MASK;
@@ -15784,7 +15758,7 @@ wm_link_stall_workaround_hv(struct wm_so
delay(200 * 1000); /* XXX too big */
- /* flush the packets in the fifo buffer */
+ /* Flush the packets in the fifo buffer */
wm_gmii_hv_writereg(sc->sc_dev, 1, HV_MUX_DATA_CTRL,
HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED);
wm_gmii_hv_writereg(sc->sc_dev, 1, HV_MUX_DATA_CTRL,
@@ -15863,7 +15837,7 @@ static void
wm_reset_init_script_82575(struct wm_softc *sc)
{
/*
- * remark: this is untested code - we have no board without EEPROM
+ * Remark: this is untested code - we have no board without EEPROM
* same setup as mentioned int the FreeBSD driver for the i82575
*/
