Module Name: src
Committed By: jmcneill
Date: Sat Dec 7 16:00:36 UTC 2019
Modified Files:
src/sys/arch/arm/rockchip: rk3399_pcie.c
Log Message:
Use bus_space_{peek,poke}_4 for pci conf reg access.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/rockchip/rk3399_pcie.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rk3399_pcie.c
diff -u src/sys/arch/arm/rockchip/rk3399_pcie.c:1.7 src/sys/arch/arm/rockchip/rk3399_pcie.c:1.8
--- src/sys/arch/arm/rockchip/rk3399_pcie.c:1.7 Fri Nov 29 00:36:22 2019
+++ src/sys/arch/arm/rockchip/rk3399_pcie.c Sat Dec 7 16:00:36 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399_pcie.c,v 1.7 2019/11/29 00:36:22 jmcneill Exp $ */
+/* $NetBSD: rk3399_pcie.c,v 1.8 2019/12/07 16:00:36 jmcneill Exp $ */
/*
* Copyright (c) 2018 Mark Kettenis <[email protected]>
*
@@ -17,7 +17,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.7 2019/11/29 00:36:22 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.8 2019/12/07 16:00:36 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -121,10 +121,10 @@ __KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
#define HWRITE4(sc, reg, val) \
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
-#define AXIREAD4(sc, reg) \
- bus_space_read_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg))
-#define AXIWRITE4(sc, reg, val) \
- bus_space_write_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (val))
+#define AXIPEEK4(sc, reg, valp) \
+ bus_space_peek_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (valp))
+#define AXIPOKE4(sc, reg, val) \
+ bus_space_poke_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (val))
struct rkpcie_softc {
struct pcihost_softc sc_phsc;
@@ -540,8 +540,12 @@ rkpcie_conf_read(void *v, pcitag_t tag,
if (bus == phsc->sc_bus_min)
return HREAD4(sc, PCIE_RC_NORMAL_BASE + reg);
- else
- return AXIREAD4(sc, reg);
+ else {
+ uint32_t val;
+ if (AXIPEEK4(sc, reg, &val) != 0)
+ return 0xffffffff;
+ return val;
+ }
}
void
@@ -563,7 +567,7 @@ rkpcie_conf_write(void *v, pcitag_t tag,
if (bus == phsc->sc_bus_min)
HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data);
else
- AXIWRITE4(sc, reg, data);
+ AXIPOKE4(sc, reg, data);
}
static int
