Module Name: src
Committed By: jakllsch
Date: Wed Dec 18 18:40:19 UTC 2019
Modified Files:
src/sys/arch/arm/rockchip: rk3399_cru.c
Log Message:
rk3399_cru: Reparent dclk_vop[01] to gpll via dclk_vop[01]_frac.
The previous source of dclk_vop[01] was vpll via dclk_vop[01]_div.
vpll is apparently used directly as a pixel clock source for the
HDMI PHY, and we don't want the other VOP's dclk changing out from
under it because we can't handle finding a replacement clock source
with the right rate yet.
gpll happens to run at 594MHz, which works well as a basis for pixel
clocks.
Linux suggests that the source clock of the fractional divider needs
to be more than twenty times greater than the resulting clock (or some
intermediate clock?) for output stability. This may not be the case
with 594MHz and the common pixel clocks I see used by displays in my
area of the wild, but it works for now.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/rockchip/rk3399_cru.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rk3399_cru.c
diff -u src/sys/arch/arm/rockchip/rk3399_cru.c:1.17 src/sys/arch/arm/rockchip/rk3399_cru.c:1.18
--- src/sys/arch/arm/rockchip/rk3399_cru.c:1.17 Tue Dec 17 17:51:12 2019
+++ src/sys/arch/arm/rockchip/rk3399_cru.c Wed Dec 18 18:40:19 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399_cru.c,v 1.17 2019/12/17 17:51:12 jakllsch Exp $ */
+/* $NetBSD: rk3399_cru.c,v 1.18 2019/12/18 18:40:19 jakllsch Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.17 2019/12/17 17:51:12 jakllsch Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.18 2019/12/18 18:40:19 jakllsch Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -1030,6 +1030,10 @@ static const struct rk3399_init_param {
{ .clk = "clk_i2s0_mux", .parent = "clk_i2s0_frac" },
{ .clk = "clk_i2s1_mux", .parent = "clk_i2s1_frac" },
{ .clk = "clk_i2s2_mux", .parent = "clk_i2s2_frac" },
+ { .clk = "dclk_vop0_div", .parent = "gpll" },
+ { .clk = "dclk_vop1_div", .parent = "gpll" },
+ { .clk = "dclk_vop0", .parent = "dclk_vop0_frac" },
+ { .clk = "dclk_vop1", .parent = "dclk_vop1_frac" },
};
static void
