Module Name: src Committed By: simonb Date: Sun May 24 07:15:24 UTC 2020
Modified Files: src/sys/arch/mips/include: cpuregs.h locore.h src/sys/arch/mips/mips: locore_mips3.S Log Message: Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number read from the CPUNum hardware register on MIPS{32,64}R2. To generate a diff of this commit: cvs rdiff -u -r1.98 -r1.99 src/sys/arch/mips/include/cpuregs.h cvs rdiff -u -r1.104 -r1.105 src/sys/arch/mips/include/locore.h cvs rdiff -u -r1.114 -r1.115 src/sys/arch/mips/mips/locore_mips3.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/mips/include/cpuregs.h diff -u src/sys/arch/mips/include/cpuregs.h:1.98 src/sys/arch/mips/include/cpuregs.h:1.99 --- src/sys/arch/mips/include/cpuregs.h:1.98 Sat May 23 10:39:25 2020 +++ src/sys/arch/mips/include/cpuregs.h Sun May 24 07:15:24 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: cpuregs.h,v 1.98 2020/05/23 10:39:25 simonb Exp $ */ +/* $NetBSD: cpuregs.h,v 1.99 2020/05/24 07:15:24 simonb Exp $ */ /* * Copyright (c) 2009 Miodrag Vallat. @@ -805,15 +805,27 @@ #endif /* + * RDHWR register numbers + */ +#define MIPS_HWR_CPUNUM _(0) +#define MIPS_HWR_SYNCI_STEP _(1) +#define MIPS_HWR_CC _(2) +#define MIPS_HWR_CCRES _(3) +#define MIPS_HWR_UL _(29) /* Userlocal */ +#define MIPS_HWR_IMPL30 _(30) +#define MIPS_HWR_IMPL31 _(31) +#define MIPS_HWR_CPUNUM _(0) + +/* * Bits defined for HWREna (CP0 register 7, select 0). */ -#define MIPS_HWRENA_IMPL31 __BIT(31) -#define MIPS_HWRENA_IMPL30 __BIT(30) -#define MIPS_HWRENA_UL __BIT(29) /* Userlocal */ -#define MIPS_HWRENA_CCRES __BIT(3) -#define MIPS_HWRENA_CC __BIT(2) -#define MIPS_HWRENA_SYNCI_STEP __BIT(1) -#define MIPS_HWRENA_CPUNUM __BIT(0) +#define MIPS_HWRENA_IMPL31 __BIT(MIPS_HWR_IMPL31) +#define MIPS_HWRENA_IMPL30 __BIT(MIPS_HWR_IMPL30) +#define MIPS_HWRENA_UL __BIT(MIPS_HWR_UL) +#define MIPS_HWRENA_CCRES __BIT(MIPS_HWR_CCRES) +#define MIPS_HWRENA_CC __BIT(MIPS_HWR_CC) +#define MIPS_HWRENA_SYNCI_STEP __BIT(MIPS_HWR_SYNCI_STEP) +#define MIPS_HWRENA_CPUNUM __BIT(MIPS_HWR_CPUNUM) /* * Bits defined for EBASE (CP0 register 15, select 1). Index: src/sys/arch/mips/include/locore.h diff -u src/sys/arch/mips/include/locore.h:1.104 src/sys/arch/mips/include/locore.h:1.105 --- src/sys/arch/mips/include/locore.h:1.104 Sat Apr 6 03:06:26 2019 +++ src/sys/arch/mips/include/locore.h Sun May 24 07:15:24 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.h,v 1.104 2019/04/06 03:06:26 thorpej Exp $ */ +/* $NetBSD: locore.h,v 1.105 2020/05/24 07:15:24 simonb Exp $ */ /* * This file should not be included by MI code!!! @@ -435,6 +435,8 @@ void mipsNN_cp0_watchhi_write(u_int, uin int32_t mipsNN_cp0_ebase_read(void); void mipsNN_cp0_ebase_write(int32_t); +uint32_t mipsNN_cp0_rdhwr_cpunum(void); + #ifdef MIPSNNR2 void mipsNN_cp0_hwrena_write(uint32_t); void mipsNN_cp0_userlocal_write(void *); Index: src/sys/arch/mips/mips/locore_mips3.S diff -u src/sys/arch/mips/mips/locore_mips3.S:1.114 src/sys/arch/mips/mips/locore_mips3.S:1.115 --- src/sys/arch/mips/mips/locore_mips3.S:1.114 Fri Jan 26 05:29:43 2018 +++ src/sys/arch/mips/mips/locore_mips3.S Sun May 24 07:15:24 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: locore_mips3.S,v 1.114 2018/01/26 05:29:43 maya Exp $ */ +/* $NetBSD: locore_mips3.S,v 1.115 2020/05/24 07:15:24 simonb Exp $ */ /* * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author) @@ -92,7 +92,7 @@ #include <mips/asm.h> #include <mips/cpuregs.h> -RCSID("$NetBSD: locore_mips3.S,v 1.114 2018/01/26 05:29:43 maya Exp $") +RCSID("$NetBSD: locore_mips3.S,v 1.115 2020/05/24 07:15:24 simonb Exp $") #include "assym.h" @@ -493,6 +493,22 @@ END(mipsNN_cp0_ebase_write) #if (MIPS32R2 + MIPS64R2) > 0 /* + * uint32_t mipsNN_cp0_rdhwr_cpunum(void); + * Set the value of the CP0 HWRENA register. + */ +LEAF(mipsNN_cp0_rdhwr_cpunum) + .set push +#ifdef __mips_o32 + .set mips32r2 +#else + .set mips64r2 +#endif + jr ra + rdhwr v0, MIPS_HWR_CPUNUM + .set pop +END(mipsNN_cp0_rdhwr_cpunum) + +/* * void mipsNN_cp0_hwrena_write(void *); * Set the value of the CP0 HWRENA register. */