Module Name: src
Committed By: riastradh
Date: Sun Jun 14 16:10:18 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
src/sys/arch/aarch64/include: armreg.h
Log Message:
Add some more id_aa64pfr0_el1 bits.
To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.46 src/sys/arch/aarch64/aarch64/cpu.c:1.47
--- src/sys/arch/aarch64/aarch64/cpu.c:1.46 Sat May 30 17:50:39 2020
+++ src/sys/arch/aarch64/aarch64/cpu.c Sun Jun 14 16:10:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.46 2020/05/30 17:50:39 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.47 2020/06/14 16:10:18 riastradh Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.46 2020/05/30 17:50:39 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.47 2020/06/14 16:10:18 riastradh Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -343,6 +343,16 @@ cpu_identify2(device_t self, struct cpu_
aprint_verbose_dev(self, "auxID=0x%" PRIx64, ci->ci_id.ac_aa64isar0);
/* PFR0 */
+ switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_CSV3)) {
+ case ID_AA64PFR0_EL1_CSV3_IMPL:
+ aprint_verbose(", CSV3");
+ break;
+ }
+ switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_CSV2)) {
+ case ID_AA64PFR0_EL1_CSV2_IMPL:
+ aprint_verbose(", CSV2");
+ break;
+ }
switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_GIC)) {
case ID_AA64PFR0_EL1_GIC_CPUIF_EN:
aprint_verbose(", GICv3");
@@ -384,6 +394,12 @@ cpu_identify2(device_t self, struct cpu_
break;
}
+ /* PFR0:DIT -- data-independent timing support */
+ switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_DIT)) {
+ case ID_AA64PFR0_EL1_DIT_IMPL:
+ aprint_verbose(", DIT");
+ break;
+ }
/* PFR0:AdvSIMD */
switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.48 src/sys/arch/aarch64/include/armreg.h:1.49
--- src/sys/arch/aarch64/include/armreg.h:1.48 Thu May 28 12:41:15 2020
+++ src/sys/arch/aarch64/include/armreg.h Sun Jun 14 16:10:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.48 2020/05/28 12:41:15 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.49 2020/06/14 16:10:18 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -1305,6 +1305,26 @@ AARCH64REG_WRITE_INLINE(cntvct_el0)
#define CNTCTL_ENABLE __BIT(0) // Timer Enabled
// ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
+#define ID_AA64PFR0_EL1_CSV3 __BITS(63,60) // Speculative fault data
+#define ID_AA64PFR0_EL1_CSV3_NONE 0
+#define ID_AA64PFR0_EL1_CSV3_IMPL 1
+#define ID_AA64PFR0_EL1_CSV2 __BITS(59,56) // Speculative branches
+#define ID_AA64PFR0_EL1_CSV2_NONE 0
+#define ID_AA64PFR0_EL1_CSV2_IMPL 1
+// reserved [55:52]
+#define ID_AA64PFR0_EL1_DIT __BITS(51,48) // Data-indep. timing
+#define ID_AA64PFR0_EL1_DIT_NONE 0
+#define ID_AA64PFR0_EL1_DIT_IMPL 1
+#define ID_AA64PFR0_EL1_AMU __BITS(47,44) // Activity monitors ext.
+#define ID_AA64PFR0_EL1_AMU_NONE 0
+#define ID_AA64PFR0_EL1_AMU_IMPLv8_4 1
+#define ID_AA64PFR0_EL1_AMU_IMPLv8_6 2
+#define ID_AA64PFR0_EL1_MPAM __BITS(43,40) // MPAM Extension
+#define ID_AA64PFR0_EL1_MPAM_NONE 0
+#define ID_AA64PFR0_EL1_MPAM_IMPL 1
+#define ID_AA64PFR0_EL1_SEL2 __BITS(43,40) // Secure EL2
+#define ID_AA64PFR0_EL1_SEL2_NONE 0
+#define ID_AA64PFR0_EL1_SEL2_IMPL 1
#define ID_AA64PFR0_EL1_SVE __BITS(35,32) // Scalable Vector
#define ID_AA64PFR0_EL1_SVE_NONE 0
#define ID_AA64PFR0_EL1_SVE_IMPL 1
