Module Name: src
Committed By: msaitoh
Date: Mon Aug 3 07:16:51 UTC 2020
Modified Files:
src/sys/dev/mii: igphy.c igphyreg.h
src/sys/dev/pci: if_wm.c
Log Message:
s/MII_IGPHY_/IGPHY_/. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/dev/mii/igphy.c
cvs rdiff -u -r1.11 -r1.12 src/sys/dev/mii/igphyreg.h
cvs rdiff -u -r1.681 -r1.682 src/sys/dev/pci/if_wm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/igphy.c
diff -u src/sys/dev/mii/igphy.c:1.34 src/sys/dev/mii/igphy.c:1.35
--- src/sys/dev/mii/igphy.c:1.34 Tue Jul 7 08:44:12 2020
+++ src/sys/dev/mii/igphy.c Mon Aug 3 07:16:51 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: igphy.c,v 1.34 2020/07/07 08:44:12 msaitoh Exp $ */
+/* $NetBSD: igphy.c,v 1.35 2020/08/03 07:16:51 msaitoh Exp $ */
/*
* The Intel copyright applies to the analog register setup, and the
@@ -70,7 +70,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.34 2020/07/07 08:44:12 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.35 2020/08/03 07:16:51 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_mii.h"
@@ -268,7 +268,7 @@ igphy_load_dspcode(struct mii_softc *sc)
delay(20000);
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
PHY_WRITE(sc, 0x0000, 0x0140);
delay(5000);
@@ -276,7 +276,7 @@ igphy_load_dspcode(struct mii_softc *sc)
for (i = 0; !((code[i].reg == 0) && (code[i].val == 0)); i++)
IGPHY_WRITE(sc, code[i].reg, code[i].val);
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
PHY_WRITE(sc, 0x0000, 0x3300);
delay(20000);
@@ -323,9 +323,9 @@ igphy_reset(struct mii_softc *sc)
}
if (igsc->sc_mactype == WM_T_82547) {
- IGPHY_READ(sc, MII_IGPHY_ANALOG_SPARE_FUSE_STATUS, &fused);
+ IGPHY_READ(sc, IGPHY_ANALOG_SPARE_FUSE_STATUS, &fused);
if ((fused & ANALOG_SPARE_FUSE_ENABLED) == 0) {
- IGPHY_READ(sc, MII_IGPHY_ANALOG_FUSE_STATUS, &fused);
+ IGPHY_READ(sc, IGPHY_ANALOG_FUSE_STATUS, &fused);
fine = fused & ANALOG_FUSE_FINE_MASK;
coarse = fused & ANALOG_FUSE_COARSE_MASK;
@@ -340,12 +340,12 @@ igphy_reset(struct mii_softc *sc)
(fine & ANALOG_FUSE_FINE_MASK) |
(coarse & ANALOG_FUSE_COARSE_MASK);
- IGPHY_WRITE(sc, MII_IGPHY_ANALOG_FUSE_CONTROL, fused);
- IGPHY_WRITE(sc, MII_IGPHY_ANALOG_FUSE_BYPASS,
+ IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_CONTROL, fused);
+ IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_BYPASS,
ANALOG_FUSE_ENABLE_SW_CONTROL);
}
}
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
}
@@ -379,14 +379,14 @@ igphy_service(struct mii_softc *sc, stru
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
- PHY_READ(sc, MII_IGPHY_PORT_CTRL, ®);
+ PHY_READ(sc, IGPHY_PORT_CTRL, ®);
if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
reg |= PSCR_AUTO_MDIX;
reg &= ~PSCR_FORCE_MDI_MDIX;
- PHY_WRITE(sc, MII_IGPHY_PORT_CTRL, reg);
+ PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
} else {
reg &= ~(PSCR_AUTO_MDIX | PSCR_FORCE_MDI_MDIX);
- PHY_WRITE(sc, MII_IGPHY_PORT_CTRL, reg);
+ PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
}
mii_phy_setmedia(sc);
@@ -429,7 +429,7 @@ igphy_status(struct mii_softc *sc)
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
- PHY_READ(sc, MII_IGPHY_PORT_STATUS, &pssr);
+ PHY_READ(sc, IGPHY_PORT_STATUS, &pssr);
if (pssr & PSSR_LINK_UP)
mii->mii_media_status |= IFM_ACTIVE;
Index: src/sys/dev/mii/igphyreg.h
diff -u src/sys/dev/mii/igphyreg.h:1.11 src/sys/dev/mii/igphyreg.h:1.12
--- src/sys/dev/mii/igphyreg.h:1.11 Tue Jan 22 03:42:27 2019
+++ src/sys/dev/mii/igphyreg.h Mon Aug 3 07:16:51 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: igphyreg.h,v 1.11 2019/01/22 03:42:27 msaitoh Exp $ */
+/* $NetBSD: igphyreg.h,v 1.12 2020/08/03 07:16:51 msaitoh Exp $ */
/*******************************************************************************
@@ -43,7 +43,7 @@
*/
/* IGP01E1000 Specific Port Config Register - R/W */
-#define MII_IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */
+#define IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */
#define PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
#define PSCFR_PRE_EN 0x0020
#define PSCFR_SMART_SPEED 0x0080
@@ -52,7 +52,7 @@
#define PSCFR_DISABLE_TRANSMIT 0x2000
/* IGP01E1000 Specific Port Status Register - R/O */
-#define MII_IGPHY_PORT_STATUS 0x11
+#define IGPHY_PORT_STATUS 0x11
#define PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
#define PSSR_POLARITY_REVERSED 0x0002
#define PSSR_CABLE_LENGTH 0x007C
@@ -67,7 +67,7 @@
#define PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
/* IGP01E1000 Specific Port Control Register - R/W */
-#define MII_IGPHY_PORT_CTRL 0x12
+#define IGPHY_PORT_CTRL 0x12
#define PSCR_TP_LOOPBACK 0x0010
#define PSCR_CORRECT_NC_SCMBLR 0x0200
#define PSCR_TEN_CRS_SELECT 0x0400
@@ -76,7 +76,7 @@
#define PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
/* IGP01E1000 Specific Port Link Health Register */
-#define MII_IGPHY_LINK_HEALTH 0x13
+#define IGPHY_LINK_HEALTH 0x13
#define PLHR_VALID_CHANNEL_A 0x0001
#define PLHR_VALID_CHANNEL_B 0x0002
#define PLHR_VALID_CHANNEL_C 0x0004
@@ -96,61 +96,61 @@
#define GMII_SPD 0x20 /* Enable SPD */
/* IGP01E1000 Channel Quality Register */
-#define MII_IGPHY_CHANNEL_QUALITY 0x15
+#define IGPHY_CHANNEL_QUALITY 0x15
#define MSE_CHANNEL_A 0x000F
#define MSE_CHANNEL_B 0x00F0
#define MSE_CHANNEL_C 0x0F00
#define MSE_CHANNEL_D 0xF000
/* IGP01E1000 Power Management */
-#define MII_IGPHY_POWER_MGMT 0x19
+#define IGPHY_POWER_MGMT 0x19
#define PMR_SPD_EN 0x0001
#define PMR_D0_LPLU 0x0002
#define PMR_D3_LPLU 0x0004
#define PMR_DIS_1000 0x0040
-#define MII_IGPHY_PAGE_SELECT 0x1F
+#define IGPHY_PAGE_SELECT 0x1F
#define IGPHY_MAXREGADDR 0x1F
#define IGPHY_PAGEMASK (~IGPHY_MAXREGADDR)
/* IGP01E1000 AGC Registers - stores the cable length values*/
-#define MII_IGPHY_AGC_A 0x1172
-#define MII_IGPHY_AGC_PARAM_A 0x1171
-#define MII_IGPHY_AGC_B 0x1272
-#define MII_IGPHY_AGC_PARAM_B 0x1271
-#define MII_IGPHY_AGC_C 0x1472
-#define MII_IGPHY_AGC_PARAM_C 0x1471
-#define MII_IGPHY_AGC_D 0x1872
-#define MII_IGPHY_AGC_PARAM_D 0x1871
+#define IGPHY_AGC_A 0x1172
+#define IGPHY_AGC_PARAM_A 0x1171
+#define IGPHY_AGC_B 0x1272
+#define IGPHY_AGC_PARAM_B 0x1271
+#define IGPHY_AGC_C 0x1472
+#define IGPHY_AGC_PARAM_C 0x1471
+#define IGPHY_AGC_D 0x1872
+#define IGPHY_AGC_PARAM_D 0x1871
#define AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
#define AGC_LENGTH_TABLE_SIZE 128
#define AGC_RANGE 10
/* IGP01E1000 DSP Reset Register */
-#define MII_IGPHY_DSP_RESET 0x1F33
-#define MII_IGPHY_DSP_SET 0x1F71
-#define MII_IGPHY_DSP_FFE 0x1F35
-#define MII_IGPHY_CHANNEL_NUM 4
-#define MII_IGPHY_EDAC_MU_INDEX 0xC000
-#define MII_IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000
-#define MII_IGPHY_ANALOG_TX_STATE 0x2890
-#define MII_IGPHY_ANALOG_CLASS_A 0x2000
-#define MII_IGPHY_FORCE_ANALOG_ENABLE 0x0004
-#define MII_IGPHY_DSP_FFE_CM_CP 0x0069
-#define MII_IGPHY_DSP_FFE_DEFAULT 0x002A
+#define IGPHY_DSP_RESET 0x1F33
+#define IGPHY_DSP_SET 0x1F71
+#define IGPHY_DSP_FFE 0x1F35
+#define IGPHY_CHANNEL_NUM 4
+#define IGPHY_EDAC_MU_INDEX 0xC000
+#define IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000
+#define IGPHY_ANALOG_TX_STATE 0x2890
+#define IGPHY_ANALOG_CLASS_A 0x2000
+#define IGPHY_FORCE_ANALOG_ENABLE 0x0004
+#define IGPHY_DSP_FFE_CM_CP 0x0069
+#define IGPHY_DSP_FFE_DEFAULT 0x002A
/* IGP01E1000 PCS Initialization register - stores the polarity status */
-#define MII_IGPHY_PCS_INIT_REG 0x00B4
-#define MII_IGPHY_PCS_CTRL_REG 0x00B5
+#define IGPHY_PCS_INIT_REG 0x00B4
+#define IGPHY_PCS_CTRL_REG 0x00B5
-#define MII_IGPHY_ANALOG_REGS_PAGE 0x20C0
+#define IGPHY_ANALOG_REGS_PAGE 0x20C0
#define PHY_POLARITY_MASK 0x0078
/* IGP01E1000 Analog Register */
-#define MII_IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1
-#define MII_IGPHY_ANALOG_FUSE_STATUS 0x20D0
-#define MII_IGPHY_ANALOG_FUSE_CONTROL 0x20DC
-#define MII_IGPHY_ANALOG_FUSE_BYPASS 0x20DE
+#define IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1
+#define IGPHY_ANALOG_FUSE_STATUS 0x20D0
+#define IGPHY_ANALOG_FUSE_CONTROL 0x20DC
+#define IGPHY_ANALOG_FUSE_BYPASS 0x20DE
#define ANALOG_FUSE_POLY_MASK 0xF000
#define ANALOG_FUSE_FINE_MASK 0x0F80
#define ANALOG_FUSE_COARSE_MASK 0x0070
@@ -180,7 +180,7 @@ IGPHY_READ(struct mii_softc *sc, int reg
{
int rv;
- if ((rv = PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
+ if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
return rv;
return PHY_READ(sc, reg & 0x1f, val);
}
@@ -189,7 +189,7 @@ IGPHY_WRITE(struct mii_softc *sc, int re
{
int rv;
- if ((rv = PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
+ if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
return rv;
return PHY_WRITE(sc, reg & 0x1f, val);
Index: src/sys/dev/pci/if_wm.c
diff -u src/sys/dev/pci/if_wm.c:1.681 src/sys/dev/pci/if_wm.c:1.682
--- src/sys/dev/pci/if_wm.c:1.681 Thu Jul 9 06:42:44 2020
+++ src/sys/dev/pci/if_wm.c Mon Aug 3 07:16:51 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.681 2020/07/09 06:42:44 msaitoh Exp $ */
+/* $NetBSD: if_wm.c,v 1.682 2020/08/03 07:16:51 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -82,7 +82,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.681 2020/07/09 06:42:44 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.682 2020/08/03 07:16:51 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -4319,7 +4319,7 @@ wm_init_lcd_from_nvm(struct wm_softc *sc
if (wm_nvm_read(sc, (word_addr + i * 2 + 1), 1, ®_addr) !=0)
goto release;
- if (reg_addr == MII_IGPHY_PAGE_SELECT)
+ if (reg_addr == IGPHY_PAGE_SELECT)
phy_page = reg_data;
reg_addr &= IGPHY_MAXREGADDR;
@@ -10883,7 +10883,7 @@ wm_gmii_i82544_readreg_locked(device_t d
case WMPHY_IGP_2:
case WMPHY_IGP_3:
rv = wm_gmii_mdic_writereg(dev, phy,
- MII_IGPHY_PAGE_SELECT, reg);
+ IGPHY_PAGE_SELECT, reg);
if (rv != 0)
return rv;
break;
@@ -10933,7 +10933,7 @@ wm_gmii_i82544_writereg_locked(device_t
case WMPHY_IGP_2:
case WMPHY_IGP_3:
rv = wm_gmii_mdic_writereg(dev, phy,
- MII_IGPHY_PAGE_SELECT, reg);
+ IGPHY_PAGE_SELECT, reg);
if (rv != 0)
return rv;
break;
@@ -11098,7 +11098,7 @@ wm_gmii_bm_readreg(device_t dev, int phy
if ((phy == 1) && (sc->sc_type != WM_T_82574)
&& (sc->sc_type != WM_T_82583))
rv = wm_gmii_mdic_writereg(dev, phy,
- MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
+ IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
else
rv = wm_gmii_mdic_writereg(dev, phy,
BME1000_PHY_PAGE_SELECT, page);
@@ -11145,7 +11145,7 @@ wm_gmii_bm_writereg(device_t dev, int ph
if ((phy == 1) && (sc->sc_type != WM_T_82574)
&& (sc->sc_type != WM_T_82583))
rv = wm_gmii_mdic_writereg(dev, phy,
- MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
+ IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
else
rv = wm_gmii_mdic_writereg(dev, phy,
BME1000_PHY_PAGE_SELECT, page);
@@ -11183,7 +11183,7 @@ wm_enable_phy_wakeup_reg_access_bm(devic
/* All page select, port ctrl and wakeup registers use phy address 1 */
/* Select Port Control Registers page */
- rv = wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
+ rv = wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
BM_PORT_CTRL_PAGE << IGP3_PAGE_SHIFT);
if (rv != 0)
return rv;
@@ -11206,7 +11206,7 @@ wm_enable_phy_wakeup_reg_access_bm(devic
/* Select Host Wakeup Registers page - caller now able to write
* registers on the Wakeup registers page
*/
- return wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
+ return wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
BM_WUC_PAGE << IGP3_PAGE_SHIFT);
}
@@ -11232,7 +11232,7 @@ wm_disable_phy_wakeup_reg_access_bm(devi
return -1;
/* Select Port Control Registers page */
- wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
+ wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
BM_PORT_CTRL_PAGE << IGP3_PAGE_SHIFT);
/* Restore 769.17 to its original value */
@@ -11379,7 +11379,7 @@ wm_gmii_hv_readreg_locked(device_t dev,
page = 0;
if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
- rv = wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
+ rv = wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
page << BME1000_PAGE_SHIFT);
if (rv != 0)
return rv;
@@ -11465,7 +11465,7 @@ wm_gmii_hv_writereg_locked(device_t dev,
if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
rv = wm_gmii_mdic_writereg(dev, 1,
- MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
+ IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
if (rv != 0)
return rv;
}
@@ -15469,9 +15469,9 @@ wm_lplu_d0_disable(struct wm_softc *sc)
case WM_T_82573:
case WM_T_82575:
case WM_T_82576:
- mii->mii_readreg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT, &phyval);
+ mii->mii_readreg(sc->sc_dev, 1, IGPHY_POWER_MGMT, &phyval);
phyval &= ~PMR_D0_LPLU;
- mii->mii_writereg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT, phyval);
+ mii->mii_writereg(sc->sc_dev, 1, IGPHY_POWER_MGMT, phyval);
break;
case WM_T_82580:
case WM_T_I350:
@@ -15797,7 +15797,7 @@ wm_hv_phy_workarounds_ich8lan(struct wm_
/* Select page 0 */
if ((rv = sc->phy.acquire(sc)) != 0)
return rv;
- rv = wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT, 0);
+ rv = wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT, 0);
sc->phy.release(sc);
if (rv != 0)
return rv;
