Module Name: src
Committed By: msaitoh
Date: Thu Dec 24 18:32:53 UTC 2020
Modified Files:
src/sys/dev/pci/ixgbe: ixgbe.c
Log Message:
Fix a bug that INTx is disabled if the INTx line is shared with other device.
ixgbe.c rev. 1.264 was not correct.
Restore EIMS before return. To read ECIR, clearing EIMC is required for
an errata, so
0) save the original EIMS value
1) clear EIMS
2) read EICR
3) restore with the saved value.
To generate a diff of this commit:
cvs rdiff -u -r1.268 -r1.269 src/sys/dev/pci/ixgbe/ixgbe.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/ixgbe/ixgbe.c
diff -u src/sys/dev/pci/ixgbe/ixgbe.c:1.268 src/sys/dev/pci/ixgbe/ixgbe.c:1.269
--- src/sys/dev/pci/ixgbe/ixgbe.c:1.268 Thu Dec 24 15:51:33 2020
+++ src/sys/dev/pci/ixgbe/ixgbe.c Thu Dec 24 18:32:53 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe.c,v 1.268 2020/12/24 15:51:33 msaitoh Exp $ */
+/* $NetBSD: ixgbe.c,v 1.269 2020/12/24 18:32:53 msaitoh Exp $ */
/******************************************************************************
@@ -5161,9 +5161,14 @@ ixgbe_legacy_irq(void *arg)
bool more = false;
bool reenable_intr = true;
u32 eicr, eicr_mask;
+ u32 eims_orig;
u32 task_requests = 0;
- /* Silicon errata #26 on 82598. Disable all interrupts */
+ eims_orig = IXGBE_READ_REG(hw, IXGBE_EIMS);
+ /*
+ * Silicon errata #26 on 82598. Disable all interrupts before reading
+ * EICR.
+ */
IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
/* Read and clear EICR */
@@ -5173,6 +5178,7 @@ ixgbe_legacy_irq(void *arg)
++que->irqs.ev_count;
if (eicr == 0) {
adapter->stats.pf.intzero.ev_count++;
+ IXGBE_WRITE_REG(hw, IXGBE_EIMS, eims_orig);
return 0;
}
