Module Name: src
Committed By: jmcneill
Date: Sat Dec 26 00:55:26 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S locore.S locore_el2.S
Log Message:
Always issue isb after cpacr_el1 writes since it is a context-changing
operation.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.74 -r1.75 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/locore_el2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.31 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.32
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.31 Thu Oct 22 07:36:02 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Sat Dec 26 00:55:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.31 2020/10/22 07:36:02 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.32 2020/12/26 00:55:26 jmcneill Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.31 2020/10/22 07:36:02 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.32 2020/12/26 00:55:26 jmcneill Exp $")
ARMV8_DEFINE_OPTIONS
@@ -86,6 +86,7 @@ ENTRY_NP(cpu_switchto)
DISABLE_INTERRUPT
mov sp, x4 /* restore stack pointer */
msr cpacr_el1, x5 /* restore cpacr_el1 */
+ isb
#ifdef ARMV83_PAC
/* Switch the PAC key. */
@@ -191,6 +192,7 @@ ENTRY_NP(cpu_switchto_softint)
mov x5, #CPACR_FPEN_NONE
msr cpacr_el1, x5 /* cpacr_el1 = CPACR_FPEN_NONE */
+ isb
#ifdef ARMV83_PAC
/* Switch the PAC key. */
@@ -223,6 +225,7 @@ ENTRY_NP(cpu_switchto_softint)
mov sp, x4 /* restore pinned_lwp sp */
msr cpacr_el1, x5 /* restore pinned_lwp cpacr */
+ isb
#ifdef ARMV83_PAC
/* Restore the PAC key. */
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.74 src/sys/arch/aarch64/aarch64/locore.S:1.75
--- src/sys/arch/aarch64/aarch64/locore.S:1.74 Thu Oct 22 07:16:06 2020
+++ src/sys/arch/aarch64/aarch64/locore.S Sat Dec 26 00:55:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $ */
+/* $NetBSD: locore.S,v 1.75 2020/12/26 00:55:26 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -38,7 +38,7 @@
#include <aarch64/hypervisor.h>
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $")
+RCSID("$NetBSD: locore.S,v 1.75 2020/12/26 00:55:26 jmcneill Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -250,6 +250,7 @@ init_sysregs:
/* No trap system register access, and Trap FP/SIMD access */
msr cpacr_el1, xzr
+ isb
/* allow to read CNTVCT_EL0 and CNTFRQ_EL0 from EL0 */
mrs x0, cntkctl_el1
Index: src/sys/arch/aarch64/aarch64/locore_el2.S
diff -u src/sys/arch/aarch64/aarch64/locore_el2.S:1.7 src/sys/arch/aarch64/aarch64/locore_el2.S:1.8
--- src/sys/arch/aarch64/aarch64/locore_el2.S:1.7 Tue Sep 15 09:28:20 2020
+++ src/sys/arch/aarch64/aarch64/locore_el2.S Sat Dec 26 00:55:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_el2.S,v 1.7 2020/09/15 09:28:20 ryo Exp $ */
+/* $NetBSD: locore_el2.S,v 1.8 2020/12/26 00:55:26 jmcneill Exp $ */
/*-
* Copyright (c) 2012-2014 Andrew Turner
@@ -32,7 +32,7 @@
#include <aarch64/hypervisor.h>
#include "assym.h"
-RCSID("$NetBSD: locore_el2.S,v 1.7 2020/09/15 09:28:20 ryo Exp $")
+RCSID("$NetBSD: locore_el2.S,v 1.8 2020/12/26 00:55:26 jmcneill Exp $")
/*
* For use in #include "locore_el2.S".
@@ -85,6 +85,7 @@ in_el2:
bic x2, x2, #CPACR_FPEN
orr x2, x2, #CPACR_FPEN_ALL
msr cpacr_el1, x2
+ isb
/* Don't trap to EL2 on access to various registers. */
mov x2, #CPTR_RES1
