Module Name: src
Committed By: matt
Date: Thu Feb 25 05:45:12 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: locore.h
src/sys/arch/mips/mips [matt-nb5-mips64]: locore.S locore_mips3.S
mipsX_subr.S mips_machdep.c
Log Message:
Add mipsXX_tlb_record_asids - records what ASIDs have valid TLB entries in
the TLB.
Move some mips3 specific routines from locore.S to locore_mips3.S
To generate a diff of this commit:
cvs rdiff -u -r1.78.36.1.2.14 -r1.78.36.1.2.15 \
src/sys/arch/mips/include/locore.h
cvs rdiff -u -r1.167.38.15 -r1.167.38.16 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.93.38.6 -r1.93.38.7 src/sys/arch/mips/mips/locore_mips3.S
cvs rdiff -u -r1.26.36.1.2.25 -r1.26.36.1.2.26 \
src/sys/arch/mips/mips/mipsX_subr.S
cvs rdiff -u -r1.205.4.1.2.1.2.35 -r1.205.4.1.2.1.2.36 \
src/sys/arch/mips/mips/mips_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.78.36.1.2.14 src/sys/arch/mips/include/locore.h:1.78.36.1.2.15
--- src/sys/arch/mips/include/locore.h:1.78.36.1.2.14 Tue Feb 23 20:33:47 2010
+++ src/sys/arch/mips/include/locore.h Thu Feb 25 05:45:12 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.78.36.1.2.14 2010/02/23 20:33:47 matt Exp $ */
+/* $NetBSD: locore.h,v 1.78.36.1.2.15 2010/02/25 05:45:12 matt Exp $ */
/*
* This file should not be included by MI code!!!
@@ -51,6 +51,7 @@
void mips1_tlb_invalidate_globals(void);
void mips1_tlb_invalidate_asids(uint32_t, uint32_t);
void mips1_tlb_invalidate_addr(vaddr_t);
+u_int mips1_tlb_record_asids(u_long *, uint32_t);
int mips1_tlb_update(vaddr_t, uint32_t);
void mips1_tlb_read_indexed(size_t, struct tlbmask *);
void mips1_wbflush(void);
@@ -67,6 +68,7 @@
void mips3_tlb_invalidate_globals(void);
void mips3_tlb_invalidate_asids(uint32_t, uint32_t);
void mips3_tlb_invalidate_addr(vaddr_t);
+u_int mips3_tlb_record_asids(u_long *, uint32_t);
int mips3_tlb_update(vaddr_t, uint32_t);
void mips3_tlb_read_indexed(size_t, struct tlbmask *);
void mips3_tlb_write_indexed_VPS(size_t, struct tlbmask *);
@@ -82,6 +84,7 @@
void mips5900_tlb_invalidate_globals(void);
void mips5900_tlb_invalidate_asids(uint32_t, uint32_t);
void mips5900_tlb_invalidate_addr(vaddr_t);
+u_int mips5900_tlb_record_asids(u_long *, uint32_t);
int mips5900_tlb_update(vaddr_t, uint32_t);
void mips5900_tlb_read_indexed(size_t, struct tlbmask *);
void mips5900_tlb_write_indexed_VPS(size_t, struct tlbmask *);
@@ -99,6 +102,7 @@
void mips32_tlb_invalidate_globals(void);
void mips32_tlb_invalidate_asids(uint32_t, uint32_t);
void mips32_tlb_invalidate_addr(vaddr_t);
+u_int mips32_tlb_record_asids(u_long *, uint32_t);
int mips32_tlb_update(vaddr_t, uint32_t);
void mips32_tlb_read_indexed(size_t, struct tlbmask *);
void mips32_tlb_write_indexed_VPS(size_t, struct tlbmask *);
@@ -114,6 +118,7 @@
void mips64_tlb_invalidate_globals(void);
void mips64_tlb_invalidate_asids(uint32_t, uint32_t);
void mips64_tlb_invalidate_addr(vaddr_t);
+u_int mips64_tlb_record_asids(u_long *, uint32_t);
int mips64_tlb_update(vaddr_t, uint32_t);
void mips64_tlb_read_indexed(size_t, struct tlbmask *);
void mips64_tlb_write_indexed_VPS(size_t, struct tlbmask *);
@@ -295,6 +300,7 @@
void (*ljv_tlb_invalidate_addr)(vaddr_t);
void (*ljv_tlb_invalidate_globals)(void);
void (*ljv_tlb_invalidate_all)(void);
+ u_int (*ljv_tlb_record_asids)(u_long *, uint32_t);
int (*ljv_tlb_update)(vaddr_t, uint32_t);
void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *);
void (*ljv_wbflush)(void);
@@ -334,6 +340,7 @@
#define tlb_invalidate_addr mips1_tlb_invalidate_addr
#define tlb_invalidate_globals mips1_tlb_invalidate_globals
#define tlb_invalidate_all mips1_tlb_invalidate_all
+#define tlb_record_asids mips1_tlb_record_asids
#define tlb_update mips1_tlb_update
#define tlb_read_indexed mips1_tlb_read_indexed
#define wbflush mips1_wbflush
@@ -345,6 +352,7 @@
#define tlb_invalidate_addr mips3_tlb_invalidate_addr
#define tlb_invalidate_globals mips3_tlb_invalidate_globals
#define tlb_invalidate_all mips3_tlb_invalidate_all
+#define tlb_record_asids mips3_tlb_record_asids
#define tlb_update mips3_tlb_update
#define tlb_read_indexed mips3_tlb_read_indexed
#define tlb_write_indexed_VPS mips3_tlb_write_indexed_VPS
@@ -357,6 +365,7 @@
#define tlb_invalidate_addr mips32_tlb_invalidate_addr
#define tlb_invalidate_globals mips32_tlb_invalidate_globals
#define tlb_invalidate_all mips32_tlb_invalidate_all
+#define tlb_record_asids mips32_tlb_record_asids
#define tlb_update mips32_tlb_update
#define tlb_read_indexed mips32_tlb_read_indexed
#define tlb_write_indexed_VPS mips32_tlb_write_indexed_VPS
@@ -370,6 +379,7 @@
#define tlb_invalidate_addr mips64_tlb_invalidate_addr
#define tlb_invalidate_globals mips64_tlb_invalidate_globals
#define tlb_invalidate_all mips64_tlb_invalidate_all
+#define tlb_record_asids mips64_tlb_record_asids
#define tlb_update mips64_tlb_update
#define tlb_read_indexed mips64_tlb_read_indexed
#define tlb_write_indexed_VPS mips64_tlb_write_indexed_VPS
@@ -382,6 +392,7 @@
#define tlb_invalidate_addr mips5900_tlb_invalidate_addr
#define tlb_invalidate_globals mips5900_tlb_invalidate_globals
#define tlb_invalidate_all mips5900_tlb_invalidate_all
+#define tlb_record_asids mips5900_tlb_record_asids
#define tlb_update mips5900_tlb_update
#define tlb_read_indexed mips5900_tlb_read_indexed
#define tlb_write_indexed_VPS mips5900_tlb_write_indexed_VPS
@@ -394,6 +405,7 @@
#define tlb_invalidate_addr (*mips_locore_jumpvec.ljv_tlb_invalidate_addr)
#define tlb_invalidate_globals (*mips_locore_jumpvec.ljv_tlb_invalidate_globals)
#define tlb_invalidate_all (*mips_locore_jumpvec.ljv_tlb_invalidate_all)
+#define tlb_record_asids (*mips_locore_jumpvec.ljv_tlb_record_asids)
#define tlb_update (*mips_locore_jumpvec.ljv_tlb_update)
#define tlb_read_indexed (*mips_locore_jumpvec.ljv_tlb_read_indexed)
#define wbflush (*mips_locore_jumpvec.ljv_wbflush)
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.167.38.15 src/sys/arch/mips/mips/locore.S:1.167.38.16
--- src/sys/arch/mips/mips/locore.S:1.167.38.15 Tue Feb 23 20:33:48 2010
+++ src/sys/arch/mips/mips/locore.S Thu Feb 25 05:45:12 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.167.38.15 2010/02/23 20:33:48 matt Exp $ */
+/* $NetBSD: locore.S,v 1.167.38.16 2010/02/25 05:45:12 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -551,99 +551,6 @@
nop
END(mips_cp0_status_write)
-#ifdef MIPS3_PLUS
- .set push
- .set mips3
-/*
- * uint64_t mips_cp0_tlb_entry_hi_probe(void);
- *
- * Write 1s to the VPN field of Entry_Hi0 to see how many VA bits
- * are implemented. Assumes that interrupts are disabled.
- */
-LEAF(mips_cp0_tlb_entry_hi_probe)
- dmfc0 t0, MIPS_COP_0_TLB_HI
- li v0, -4096 /* all 1s except low 12 bits */
- dsll v0, v0, 2 /* except the top 2 */
- dsrl v0, v0, 2
- dmtc0 v0, MIPS_COP_0_TLB_HI
- COP0_SYNC
- nop
- nop
- dmfc0 v0, MIPS_COP_0_TLB_HI
- dmtc0 t0, MIPS_COP_0_TLB_HI
- COP0_SYNC
- nop
-#ifdef __mips_o32
- nop
-#if BYTE_ORDER == BIG_ENDIAN
- srl v1, v0, 0
- dsra v0, v0, 32
-#endif
-#if BYTE_ORDER == LITTLE_ENDIAN
- dsra v1, v0, 32
- srl v0, v0, 0
-#endif
-#endif /* __mips_o32 */
- j ra
- nop
-END(mips_cp0_tlb_entry_hi_probe)
-
-/*
- * uint64_t mips_cp0_tlb_entry_lo_probe(void);
- *
- * Write 1s to the PFN field of Entry_Lo0 to see how many
- * PA bits are implemented. Assumes that interrupts are disabled.
- */
-LEAF(mips_cp0_tlb_entry_lo_probe)
- dmfc0 t0, MIPS_COP_0_TLB_LO0
- li v0, -64 /* all 1s except low 6 bits */
- dmtc0 v0, MIPS_COP_0_TLB_LO0
- COP0_SYNC
- nop
- nop
- dmfc0 v0, MIPS_COP_0_TLB_LO0
- dmtc0 t0, MIPS_COP_0_TLB_LO0
- COP0_SYNC
- nop
-#ifdef __mips_o32
- nop
-#if BYTE_ORDER == BIG_ENDIAN
- srl v1, v0, 0
- dsra v0, v0, 32
-#endif
-#if BYTE_ORDER == LITTLE_ENDIAN
- dsra v1, v0, 32
- srl v0, v0, 0
-#endif
-#endif /* __mips_o32 */
- j ra
- nop
-END(mips_cp0_tlb_entry_lo_probe)
- .set pop
-
-/*
- * uint32_t mips_cp0_tlb_page_mask_probe(void);
- *
- * Write 1s to the RPN field of Entry_Lo0 to see how many PA bits are implemented.
- * Assumes that interrupts are disabled.
- */
-LEAF(mips_cp0_tlb_page_mask_probe)
- mfc0 t0, MIPS_COP_0_TLB_PG_MASK
- lui v0, 0xffff
- srl v0, v0, 3
- mtc0 v0, MIPS_COP_0_TLB_PG_MASK
- COP0_SYNC
- nop
- nop
- mfc0 v0, MIPS_COP_0_TLB_PG_MASK
- mtc0 t0, MIPS_COP_0_TLB_PG_MASK
- COP0_SYNC
- nop
- j ra
- nop
-END(mips_cp0_tlb_page_mask_probe)
-#endif /* MIPS3_PLUS */
-
#if !defined(NOFPU) || defined(FPEMUL)
/*----------------------------------------------------------------------------
*
Index: src/sys/arch/mips/mips/locore_mips3.S
diff -u src/sys/arch/mips/mips/locore_mips3.S:1.93.38.6 src/sys/arch/mips/mips/locore_mips3.S:1.93.38.7
--- src/sys/arch/mips/mips/locore_mips3.S:1.93.38.6 Mon Feb 22 20:13:22 2010
+++ src/sys/arch/mips/mips/locore_mips3.S Thu Feb 25 05:45:12 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips3.S,v 1.93.38.6 2010/02/22 20:13:22 matt Exp $ */
+/* $NetBSD: locore_mips3.S,v 1.93.38.7 2010/02/25 05:45:12 matt Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -484,3 +484,91 @@
li v0, -1
END(baderr64)
#endif
+
+/*
+ * uint64_t mips3_cp0_tlb_entry_hi_probe(void);
+ *
+ * Write 1s to the VPN and ASID fields of Entry_Hi0 to see how many VA bits
+ * and ASID bits are implemented. Assumes that interrupts are disabled.
+ */
+LEAF(mips3_cp0_tlb_entry_hi_probe)
+ dmfc0 t0, MIPS_COP_0_TLB_HI
+ li v0, -1 /* all 1s */
+ dsll v0, v0, 2 /* except the top 2 */
+ dsrl v0, v0, 2
+ dmtc0 v0, MIPS_COP_0_TLB_HI
+ COP0_SYNC
+ nop
+ nop
+ dmfc0 v0, MIPS_COP_0_TLB_HI
+ dmtc0 t0, MIPS_COP_0_TLB_HI
+ COP0_SYNC
+ nop
+#ifdef __mips_o32
+ nop
+#if BYTE_ORDER == BIG_ENDIAN
+ srl v1, v0, 0
+ dsra v0, v0, 32
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+ dsra v1, v0, 32
+ srl v0, v0, 0
+#endif
+#endif /* __mips_o32 */
+ j ra
+ nop
+END(mips3_cp0_tlb_entry_hi_probe)
+
+/*
+ * uint64_t mips3_cp0_tlb_entry_lo_probe(void);
+ *
+ * Write 1s to the PFN field of Entry_Lo0 to see how many
+ * PA bits are implemented. Assumes that interrupts are disabled.
+ */
+LEAF(mips3_cp0_tlb_entry_lo_probe)
+ dmfc0 t0, MIPS_COP_0_TLB_LO0
+ li v0, -64 /* all 1s except low 6 bits */
+ dmtc0 v0, MIPS_COP_0_TLB_LO0
+ COP0_SYNC
+ nop
+ nop
+ dmfc0 v0, MIPS_COP_0_TLB_LO0
+ dmtc0 t0, MIPS_COP_0_TLB_LO0
+ COP0_SYNC
+ nop
+#ifdef __mips_o32
+ nop
+#if BYTE_ORDER == BIG_ENDIAN
+ srl v1, v0, 0
+ dsra v0, v0, 32
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+ dsra v1, v0, 32
+ srl v0, v0, 0
+#endif
+#endif /* __mips_o32 */
+ j ra
+ nop
+END(mips3_cp0_tlb_entry_lo_probe)
+
+/*
+ * uint32_t mips3_cp0_tlb_page_mask_probe(void);
+ *
+ * Write 1s to the RPN field of Entry_Lo0 to see how many PA bits are implemented.
+ * Assumes that interrupts are disabled.
+ */
+LEAF(mips3_cp0_tlb_page_mask_probe)
+ mfc0 t0, MIPS_COP_0_TLB_PG_MASK
+ lui v0, 0xffff
+ srl v0, v0, 3
+ mtc0 v0, MIPS_COP_0_TLB_PG_MASK
+ COP0_SYNC
+ nop
+ nop
+ mfc0 v0, MIPS_COP_0_TLB_PG_MASK
+ mtc0 t0, MIPS_COP_0_TLB_PG_MASK
+ COP0_SYNC
+ nop
+ j ra
+ nop
+END(mips3_cp0_tlb_page_mask_probe)
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.25 src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.26
--- src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.25 Tue Feb 23 20:33:48 2010
+++ src/sys/arch/mips/mips/mipsX_subr.S Thu Feb 25 05:45:12 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.25 2010/02/23 20:33:48 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.26 2010/02/25 05:45:12 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -181,6 +181,12 @@
#define USE_64BIT_CP0_FUNCTIONS
#endif
+#ifdef _LP64
+#define _SLLV dsllv
+#else
+#define _SLLV sllv
+#endif
+
#if defined(USE_64BIT_CP0_FUNCTIONS)
#define _SLL dsll
#define _SRL dsrl
@@ -2304,6 +2310,7 @@
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
COP0_SYNC
+ _MFC0 t0, MIPS_COP_0_TLB_HI # Save the current PID.
mfc0 t1, MIPS_COP_0_TLB_WIRED
li v0, MIPS_KSEG0_START # invalid address
INT_L t2, _C_LABEL(mips_options) + MO_NUM_TLB_ENTRIES
@@ -2355,6 +2362,8 @@
bne t1, t2, 1b
nop
+ _MFC0 t0, MIPS_COP_0_TLB_HI # restore PID.
+ COP0_SYNC
mtc0 t3, MIPS_COP_0_TLB_PG_MASK # restore pgMask
COP0_SYNC
/* XXX simonb: lose these nops for mips32/64? */
@@ -2366,6 +2375,89 @@
END(MIPSX(tlb_invalidate_asids))
/*
+ * u_int mipsN_tlb_record_asids(u_long *bitmap, uint32_t asid_mask);
+ *
+ * Record all the ASIDs in use in the TLB and return the number of different
+ * ASIDs present.
+ */
+LEAF_NOPROFILE(MIPSX(tlb_record_asids))
+
+ _MFC0 a3, MIPS_COP_0_TLB_HI # Save the current PID.
+ mfc0 ta0, MIPS_COP_0_TLB_WIRED
+ INT_L ta1, _C_LABEL(mips_options) + MO_NUM_TLB_ENTRIES
+ move ta2, zero
+ li ta3, 1
+ move v0, zero
+
+ mfc0 v1, MIPS_COP_0_STATUS # save status register
+#ifdef _LP64
+ and t0, v1, MIPS_SR_INT_IE
+ xor t0, v1
+ mtc0 t0, MIPS_COP_0_STATUS # disable interrupts
+#else
+ mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
+#endif
+ COP0_SYNC
+
+ # do {} while (ta0 < ta1)
+1:
+ mtc0 ta0, MIPS_COP_0_TLB_INDEX # set index
+ COP0_SYNC
+ nop
+ nop
+ /* XXX simonb: lose this nop for mips32/64? */
+ nop
+ tlbr # obtain an entry
+ COP0_SYNC
+ /* XXX simonb: lose these nops for mips32/64? */
+ nop
+ nop
+ nop
+ _MFC0 t0, MIPS_COP_0_TLB_LO1
+ and t0, MIPS3_PG_G # check to see it has G bit
+ bnez t0, 4f # yep, skip this one.
+ nop
+ _MFC0 t0, MIPS_COP_0_TLB_HI # get VA and ASID
+ and t0, a1 # focus on ASID
+
+ srl a2, t0, 3 + LONG_SCALESHIFT # drop low 5 or 6 bits
+ sll a2, LONG_SCALESHIFT # make an index for the bitmap
+ _SLLV t0, ta3, t0 # t0 is mask (ta3 == 1)
+
+ PTR_ADDU a2, a0 # index into the bitmap
+ beq a2, ta2, 3f # is the desired cell loaded?
+ nop # yes, don't reload it
+ beqz ta2, 2f # have we ever loaded it?
+ nop # nope, so don't save it.
+
+ LONG_S t2, 0(ta2) # save the updated value.
+2:
+ move ta2, a2 # remember the new cell's addr
+ LONG_L t2, 0(ta2) # and load it
+3:
+ and t1, t2, t0 # t1 = t2 & t0
+ sltu t1, t1, ta3 # t1 = t1 < 1 (aka t1 == 0)
+ addu v0, t1 # v0 += t1
+ or t2, t0 # or in the new ASID bits
+4:
+ addu ta0, 1 # increment TLB entry #
+ bne ta0, ta1, 1b # keep lookup if not limit
+ nop
+
+ beqz ta2, 5f # do we have a cell to write?
+ nop # nope. nothing
+
+ LONG_S t2, 0(ta2) # save the updated value.
+5:
+ _MTC0 a3, MIPS_COP_0_TLB_HI # restore ASID
+ COP0_SYNC
+
+ mtc0 v1, MIPS_COP_0_STATUS # restore status register
+ j ra
+ COP0_SYNC # XXXX - not executed!!
+END(MIPSX(tlb_record_asids))
+
+/*
* void mipsN_tlb_invalidate_globals(void);
*
* Invalidate the non-wired TLB entries belonging to kernel space while
Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.35 src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.36
--- src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.35 Tue Feb 23 20:33:48 2010
+++ src/sys/arch/mips/mips/mips_machdep.c Thu Feb 25 05:45:12 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.35 2010/02/23 20:33:48 matt Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.36 2010/02/25 05:45:12 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.35 2010/02/23 20:33:48 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.36 2010/02/25 05:45:12 matt Exp $");
#include "opt_cputype.h"
#include "opt_compat_netbsd32.h"
@@ -173,9 +173,9 @@
int cpu_dump(void);
#if defined(MIPS3_PLUS)
-uint32_t mips_cp0_tlb_page_mask_probe(void);
-uint64_t mips_cp0_tlb_entry_hi_probe(void);
-uint64_t mips_cp0_tlb_entry_lo_probe(void);
+uint32_t mips3_cp0_tlb_page_mask_probe(void);
+uint64_t mips3_cp0_tlb_entry_hi_probe(void);
+uint64_t mips3_cp0_tlb_entry_lo_probe(void);
static void mips3_tlb_probe(void);
#endif
@@ -530,6 +530,7 @@
.ljv_tlb_invalidate_all = mips1_tlb_invalidate_all,
.ljv_tlb_invalidate_asids = mips1_tlb_invalidate_asids,
.ljv_tlb_invalidate_globals = mips1_tlb_invalidate_globals,
+ .ljv_tlb_record_asids = mips1_tlb_record_asids,
.ljv_tlb_update = mips1_tlb_update,
.ljv_tlb_read_indexed = mips1_tlb_read_indexed,
.ljv_wbflush = mips1_wbflush,
@@ -578,6 +579,7 @@
.ljv_tlb_invalidate_all = mips3_tlb_invalidate_all,
.ljv_tlb_invalidate_asids = mips3_tlb_invalidate_asids,
.ljv_tlb_invalidate_globals = mips3_tlb_invalidate_globals,
+ .ljv_tlb_record_asids = mips3_tlb_record_asids,
.ljv_tlb_update = mips3_tlb_update,
.ljv_tlb_read_indexed = mips3_tlb_read_indexed,
.ljv_wbflush = mips3_wbflush,
@@ -640,6 +642,7 @@
.ljv_tlb_invalidate_all = mips5900_tlb_invalidate_all,
.ljv_tlb_invalidate_asids = mips5900_tlb_invalidate_asids,
.ljv_tlb_invalidate_globals = mips5900_tlb_invalidate_globals,
+ .ljv_tlb_record_asids = mips5900_tlb_record_asids,
.ljv_tlb_update = mips5900_tlb_update,
.ljv_tlb_read_indexed = mips5900_tlb_read_indexed,
.ljv_wbflush = mips5900_wbflush,
@@ -690,6 +693,7 @@
.ljv_tlb_invalidate_all = mips32_tlb_invalidate_all,
.ljv_tlb_invalidate_asids = mips32_tlb_invalidate_asids,
.ljv_tlb_invalidate_globals = mips32_tlb_invalidate_globals,
+ .ljv_tlb_record_asids = mips32_tlb_record_asids,
.ljv_tlb_update = mips32_tlb_update,
.ljv_tlb_read_indexed = mips32_tlb_read_indexed,
.ljv_wbflush = mips32_wbflush,
@@ -753,6 +757,7 @@
.ljv_tlb_invalidate_all = mips64_tlb_invalidate_all,
.ljv_tlb_invalidate_asids = mips64_tlb_invalidate_asids,
.ljv_tlb_invalidate_globals = mips64_tlb_invalidate_globals,
+ .ljv_tlb_record_asids = mips64_tlb_record_asids,
.ljv_tlb_update = mips64_tlb_update,
.ljv_tlb_read_indexed = mips64_tlb_read_indexed,
.ljv_wbflush = mips64_wbflush,
@@ -1045,12 +1050,12 @@
mips3_tlb_probe(void)
{
struct mips_options * const opts = &mips_options;
- opts->mips3_tlb_pg_mask = mips_cp0_tlb_page_mask_probe();
+ opts->mips3_tlb_pg_mask = mips3_cp0_tlb_page_mask_probe();
if (CPUIS64BITS) {
- opts->mips3_tlb_vpn_mask = mips_cp0_tlb_entry_hi_probe();
+ opts->mips3_tlb_vpn_mask = mips3_cp0_tlb_entry_hi_probe();
opts->mips3_tlb_vpn_mask <<= 2;
opts->mips3_tlb_vpn_mask >>= 2;
- opts->mips3_tlb_pfn_mask = mips_cp0_tlb_entry_lo_probe();
+ opts->mips3_tlb_pfn_mask = mips3_cp0_tlb_entry_lo_probe();
}
}
#endif
