Module Name: src
Committed By: simonb
Date: Sat May 29 12:35:27 UTC 2021
Modified Files:
src/sys/arch/mips/include: cpuregs.h
src/sys/arch/mips/mips: fp.S locore.S mips_emul.c mips_fpu.c
mips_fputrap.c
Log Message:
Update the FPU register names and bit definitions to something somewhat
modern (MIPS32/MIPS64) and convert to __BIT/__BITS.
To generate a diff of this commit:
cvs rdiff -u -r1.110 -r1.111 src/sys/arch/mips/include/cpuregs.h
cvs rdiff -u -r1.57 -r1.58 src/sys/arch/mips/mips/fp.S
cvs rdiff -u -r1.227 -r1.228 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/mips/mips/mips_emul.c
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mips/mips/mips_fpu.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/mips/mips_fputrap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.110 src/sys/arch/mips/include/cpuregs.h:1.111
--- src/sys/arch/mips/include/cpuregs.h:1.110 Wed Mar 17 11:05:37 2021
+++ src/sys/arch/mips/include/cpuregs.h Sat May 29 12:35:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.110 2021/03/17 11:05:37 simonb Exp $ */
+/* $NetBSD: cpuregs.h,v 1.111 2021/05/29 12:35:27 simonb Exp $ */
/*
* Copyright (c) 2009 Miodrag Vallat.
@@ -704,40 +704,41 @@
/*
* The floating point version and status registers.
*/
-#define MIPS_FPU_ID $0
-#define MIPS_FPU_CSR $31
+#define MIPS_FIR $0 /* FP Implementation and Revision Register */
+#define MIPS_FCSR $31 /* FP Control/Status Register */
/*
* The floating point coprocessor status register bits.
*/
-#define MIPS_FPU_ROUNDING_BITS 0x00000003
-#define MIPS_FPU_ROUND_RN 0x00000000
-#define MIPS_FPU_ROUND_RZ 0x00000001
-#define MIPS_FPU_ROUND_RP 0x00000002
-#define MIPS_FPU_ROUND_RM 0x00000003
-#define MIPS_FPU_STICKY_BITS 0x0000007c
-#define MIPS_FPU_STICKY_INEXACT 0x00000004
-#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
-#define MIPS_FPU_STICKY_OVERFLOW 0x00000010
-#define MIPS_FPU_STICKY_DIV0 0x00000020
-#define MIPS_FPU_STICKY_INVALID 0x00000040
-#define MIPS_FPU_ENABLE_BITS 0x00000f80
-#define MIPS_FPU_ENABLE_INEXACT 0x00000080
-#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
-#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
-#define MIPS_FPU_ENABLE_DIV0 0x00000400
-#define MIPS_FPU_ENABLE_INVALID 0x00000800
-#define MIPS_FPU_EXCEPTION_BITS 0x0003f000
-#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
-#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
-#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
-#define MIPS_FPU_EXCEPTION_DIV0 0x00008000
-#define MIPS_FPU_EXCEPTION_INVALID 0x00010000
-#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
-#define MIPS_FPU_COND_BIT 0x00800000
-#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
-#define MIPS1_FPC_MBZ_BITS 0xff7c0000
-#define MIPS3_FPC_MBZ_BITS 0xfe7c0000
+#define MIPS_FCSR_RM __BITS(1,0)
+#define MIPS_FCSR_RM_RN 0 /* round to nearest */
+#define MIPS_FCSR_RM_RZ 1 /* round toward zerO */
+#define MIPS_FCSR_RM_RP 2 /* round towards +infinity */
+#define MIPS_FCSR_RM_RM 3 /* round towards -infinity */
+#define MIPS_FCSR_FLAGS __BITS(6,2)
+#define MIPS_FCSR_FLAGS_I __BIT(2) /* inexact */
+#define MIPS_FCSR_FLAGS_U __BIT(3) /* underflow */
+#define MIPS_FCSR_FLAGS_O __BIT(4) /* overflow */
+#define MIPS_FCSR_FLAGS_Z __BIT(5) /* divide by zero */
+#define MIPS_FCSR_FLAGS_V __BIT(6) /* invalid operation */
+#define MIPS_FCSR_ENABLES __BITS(11,7)
+#define MIPS_FCSR_ENABLES_I __BIT(7) /* inexact */
+#define MIPS_FCSR_ENABLES_U __BIT(8) /* underflow */
+#define MIPS_FCSR_ENABLES_O __BIT(9) /* overflow */
+#define MIPS_FCSR_ENABLES_Z __BIT(10) /* divide by zero */
+#define MIPS_FCSR_ENABLES_V __BIT(11) /* invalid operation */
+#define MIPS_FCSR_CAUSE __BITS(17,12)
+#define MIPS_FCSR_CAUSE_I __BIT(12) /* inexact */
+#define MIPS_FCSR_CAUSE_U __BIT(13) /* underflow */
+#define MIPS_FCSR_CAUSE_O __BIT(14) /* overflow */
+#define MIPS_FCSR_CAUSE_Z __BIT(15) /* divide by zero */
+#define MIPS_FCSR_CAUSE_V __BIT(16) /* invalid operation */
+#define MIPS_FCSR_CAUSE_E __BIT(17) /* unimplemented operation */
+#define MIPS_FCSR_NAN_2008 __BIT(18)
+#define MIPS_FCSR_ABS_2008 __BIT(19)
+#define MIPS_FCSR_FCC0 __BIT(23)
+#define MIPS_FCSR_FCC (MIPS_FPU_COND_BIT | __BITS(31,25))
+#define MIPS_FCSR_FS __BIT(24) /* r4k+ */
/*
Index: src/sys/arch/mips/mips/fp.S
diff -u src/sys/arch/mips/mips/fp.S:1.57 src/sys/arch/mips/mips/fp.S:1.58
--- src/sys/arch/mips/mips/fp.S:1.57 Mon May 24 07:27:39 2021
+++ src/sys/arch/mips/mips/fp.S Sat May 29 12:35:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: fp.S,v 1.57 2021/05/24 07:27:39 simonb Exp $ */
+/* $NetBSD: fp.S,v 1.58 2021/05/29 12:35:27 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -143,10 +143,10 @@ NESTED(mips_emul_fp, CALLFRAME_SIZ, ra)
PTR_L a3, fmt_tbl(v0) # switch on FUNC & FMT
INT_L a2, PCB_FPREGS+FRAME_FSR(t0)
#else
- cfc1 a2, MIPS_FPU_CSR # get exception register
+ cfc1 a2, MIPS_FCSR # get exception register
PTR_L a3, fmt_tbl(v0) # switch on FUNC & FMT
- and a2, a2, ~MIPS_FPU_EXCEPTION_BITS # clear exception
- ctc1 a2, MIPS_FPU_CSR
+ and a2, a2, ~MIPS_FCSR_CAUSE # clear exception
+ ctc1 a2, MIPS_FCSR
#endif
j a3
@@ -809,17 +809,17 @@ branchc1_tbl:
.text
bcfalse:
- li v0, MIPS_FPU_COND_BIT
+ li v0, MIPS_FCSR_FCC0
and v0, v0, a2
beq v0, zero, bcemul_branch
b done
bctrue:
- li v0, MIPS_FPU_COND_BIT
+ li v0, MIPS_FCSR_FCC0
and v0, v0, a2
bne v0, zero, bcemul_branch
b done
bcfalse_l:
- li v0, MIPS_FPU_COND_BIT
+ li v0, MIPS_FCSR_FCC0
and v0, v0, a2
beq v0, zero, bcemul_branch
REG_PROLOGUE
@@ -829,7 +829,7 @@ bcfalse_l:
REG_EPILOGUE
b done
bctrue_l:
- li v0, MIPS_FPU_COND_BIT
+ li v0, MIPS_FCSR_FCC0
and v0, v0, a2
bne v0, zero, bcemul_branch
REG_PROLOGUE
@@ -899,8 +899,8 @@ add_sub_s:
3:
bne ta1, zero, result_ft_s # if FT != 0, result=FT
bne ta2, zero, result_ft_s
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ bne v0, MIPS_FCSR_RM_RM, 1f # round to -infinity?
or t0, t0, ta0 # compute result sign
b result_fs_s
1:
@@ -958,8 +958,8 @@ add_sub_s:
bne t2, ta2, 2f # if same, result=0
move t1, zero # result=0
move t2, zero
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ bne v0, MIPS_FCSR_RM_RM, 1f # round to -infinity?
or t0, t0, ta0 # compute result sign
b result_fs_s
1:
@@ -1022,8 +1022,8 @@ add_sub_d:
bne ta1, zero, result_ft_d # if FT != 0, result=FT
bne ta2, zero, result_ft_d
bne ta3, zero, result_ft_d
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ bne v0, MIPS_FCSR_RM_RM, 1f # round to -infinity?
or t0, t0, ta0 # compute result sign
b result_fs_d
1:
@@ -1116,8 +1116,8 @@ add_sub_d:
move t1, zero # result=0
move t2, zero
move t3, zero
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ bne v0, MIPS_FCSR_RM_RM, 1f # round to -infinity?
or t0, t0, ta0 # compute result sign
b result_fs_d
1:
@@ -1312,15 +1312,15 @@ div_s:
3:
bne ta1, zero, 2f # is FT zero?
bne ta2, zero, 1f
- or a2, a2, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
- and v0, a2, MIPS_FPU_ENABLE_DIV0 # trap enabled?
+ or a2, a2, MIPS_FCSR_CAUSE_Z | MIPS_FCSR_FLAGS_Z
+ and v0, a2, MIPS_FCSR_ENABLES_Z # trap enabled?
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L t1, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(t1)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
li t1, SEXP_INF # result is infinity
move t2, zero
@@ -1392,15 +1392,15 @@ div_d:
bne ta1, zero, 2f # is FT zero?
bne ta2, zero, 1f
bne ta3, zero, 1f
- or a2, a2, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
- and v0, a2, MIPS_FPU_ENABLE_DIV0 # trap enabled?
+ or a2, a2, MIPS_FCSR_CAUSE_Z | MIPS_FCSR_FLAGS_Z
+ and v0, a2, MIPS_FCSR_ENABLES_Z # trap enabled?
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L t1, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(t1)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
li t1, DEXP_INF # result is infinity
move t2, zero
@@ -1912,7 +1912,7 @@ cvt_d_w:
* Convert single to integer.
*/
cvt_w_s:
- and v1, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ and v1, a2, MIPS_FCSR_RM # get rounding mode
_cvt_w_s:
jal _C_LABEL(get_fs_s)
bne t1, SEXP_INF, 1f # is FS an infinity?
@@ -1933,7 +1933,7 @@ _cvt_w_s:
* Convert double to integer.
*/
cvt_w_d:
- and v1, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ and v1, a2, MIPS_FCSR_RM # get rounding mode
_cvt_w_d:
jal _C_LABEL(get_fs_d)
bne t1, DEXP_INF, 1f # is FS an infinity?
@@ -1954,8 +1954,8 @@ cvt_w:
blt t1, WEXP_MIN, underflow_w # is exponent too small?
#else
bge t1, WEXP_MIN, 3f # is exponent too small?
- beq v1, MIPS_FPU_ROUND_RP, 1f # round to +infinity
- beq v1, MIPS_FPU_ROUND_RM, 2f # round to -infinity
+ beq v1, MIPS_FCSR_RM_RP, 1f # round to +infinity
+ beq v1, MIPS_FCSR_RM_RM, 2f # round to -infinity
move t2, zero
b result_fs_w
@@ -2002,10 +2002,10 @@ cvt_w:
* round result (t0 is sign, t2 is integer part, t3 is fractional part).
*/
2:
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
- beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, 3f # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FCSR_RM_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@@ -2034,15 +2034,15 @@ cvt_w:
* Handle inexact exception.
*/
inexact_w:
- or a2, a2, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
- and v0, a2, MIPS_FPU_ENABLE_INEXACT
+ or a2, a2, MIPS_FCSR_CAUSE_I | MIPS_FCSR_FLAGS_I
+ and v0, a2, MIPS_FCSR_ENABLES_I
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
b result_fs_w
@@ -2052,10 +2052,10 @@ inexact_w:
* or generate an invalid exception.
*/
overflow_w:
- or a2, a2, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
- and v0, a2, MIPS_FPU_ENABLE_OVERFLOW
+ or a2, a2, MIPS_FCSR_CAUSE_O | MIPS_FCSR_FLAGS_O
+ and v0, a2, MIPS_FCSR_ENABLES_O
bne v0, zero, fpe_trap
- and v0, a2, MIPS_FPU_ENABLE_INEXACT
+ and v0, a2, MIPS_FCSR_ENABLES_I
bne v0, zero, inexact_w # inexact traps enabled?
b invalid_w
@@ -2065,10 +2065,10 @@ overflow_w:
* or generate an invalid exception.
*/
underflow_w:
- or a2, a2, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
- and v0, a2, MIPS_FPU_ENABLE_UNDERFLOW
+ or a2, a2, MIPS_FCSR_CAUSE_U | MIPS_FCSR_FLAGS_U
+ and v0, a2, MIPS_FCSR_ENABLES_U
bne v0, zero, fpe_trap
- and v0, a2, MIPS_FPU_ENABLE_INEXACT
+ and v0, a2, MIPS_FCSR_ENABLES_I
bne v0, zero, inexact_w # inexact traps enabled?
b invalid_w
@@ -2144,32 +2144,32 @@ test_cond:
and v0, v0, a0 # condition match instruction?
set_cond:
bne v0, zero, 1f
- and a2, a2, ~MIPS_FPU_COND_BIT # clear condition bit
+ and a2, a2, ~MIPS_FCSR_FCC0 # clear condition bit
b 2f
1:
- or a2, a2, MIPS_FPU_COND_BIT # set condition bit
+ or a2, a2, MIPS_FCSR_FCC0 # set condition bit
2:
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save condition bit
+ ctc1 a2, MIPS_FCSR # save condition bit
#endif
b done
unordered:
and v0, a0, COND_UNORDERED # this cmp match unordered?
bne v0, zero, 1f
- and a2, a2, ~MIPS_FPU_COND_BIT # clear condition bit
+ and a2, a2, ~MIPS_FCSR_FCC0 # clear condition bit
b 2f
1:
- or a2, a2, MIPS_FPU_COND_BIT # set condition bit
+ or a2, a2, MIPS_FCSR_FCC0 # set condition bit
2:
and v0, a0, COND_SIGNAL
beq v0, zero, 1f # is this a signaling cmp?
- or a2, a2, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
- and v0, a2, MIPS_FPU_ENABLE_INVALID
+ or a2, a2, MIPS_FCSR_CAUSE_V | MIPS_FCSR_FLAGS_V
+ and v0, a2, MIPS_FCSR_ENABLES_V
bne v0, zero, fpe_trap
1:
#ifdef FPEMUL
@@ -2177,7 +2177,7 @@ unordered:
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save condition bit
+ ctc1 a2, MIPS_FCSR # save condition bit
#endif
b done
@@ -2267,10 +2267,10 @@ norm_s:
norm_noshift_s:
move ta1, t1 # save unrounded exponent
move ta2, t2 # save unrounded fraction
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
- beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, 3f # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FCSR_RM_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@@ -2310,15 +2310,15 @@ inexact_s:
and t2, t2, ~SIMPL_ONE # clear implied one bit
inexact_nobias_s:
jal _C_LABEL(set_fd_s) # save result
- or a2, a2, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
- and v0, a2, MIPS_FPU_ENABLE_INEXACT
+ or a2, a2, MIPS_FCSR_CAUSE_I | MIPS_FCSR_FLAGS_I
+ and v0, a2, MIPS_FCSR_ENABLES_I
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
b done
@@ -2328,18 +2328,18 @@ inexact_nobias_s:
* or generate an infinity.
*/
overflow_s:
- or a2, a2, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
- and v0, a2, MIPS_FPU_ENABLE_OVERFLOW
+ or a2, a2, MIPS_FCSR_CAUSE_O | MIPS_FCSR_FLAGS_O
+ and v0, a2, MIPS_FCSR_ENABLES_O
beq v0, zero, 1f
subu t1, t1, 192 # bias exponent
and t2, t2, ~SIMPL_ONE # clear implied one bit
jal _C_LABEL(set_fd_s) # save result
b fpe_trap
1:
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate)
- beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, 3f # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, 1f # round to zero (truncate)
+ beq v0, MIPS_FCSR_RM_RP, 2f # round to +infinity
bne t0, zero, 3f
1:
li t1, SEXP_MAX # result is max finite
@@ -2357,7 +2357,7 @@ overflow_s:
* "loss of accuracy" is detected as "an inexact result".
*/
underflow_s:
- and v0, a2, MIPS_FPU_ENABLE_UNDERFLOW
+ and v0, a2, MIPS_FCSR_ENABLES_U
beq v0, zero, 1f
/*
* Underflow is enabled so compute the result and trap.
@@ -2365,7 +2365,7 @@ underflow_s:
addu t1, t1, 192 # bias exponent
and t2, t2, ~SIMPL_ONE # clear implied one bit
jal _C_LABEL(set_fd_s) # save result
- or a2, a2, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ or a2, a2, MIPS_FCSR_CAUSE_U | MIPS_FCSR_FLAGS_U
b fpe_trap
/*
* Underflow is not enabled so compute the result,
@@ -2379,15 +2379,15 @@ underflow_s:
blt v0, SFRAC_BITS+2, 3f # shift all the bits out?
move t1, zero # result is inexact zero
move t2, zero
- or a2, a2, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ or a2, a2, MIPS_FCSR_CAUSE_U | MIPS_FCSR_FLAGS_U
/*
* Now round the zero result.
* Only need to worry about rounding to +- infinity when the sign matches.
*/
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_s # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_s # round to zero
- beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, inexact_nobias_s # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, inexact_nobias_s # round to zero
+ beq v0, MIPS_FCSR_RM_RP, 1f # round to +infinity
beq t0, zero, inexact_nobias_s # if sign is positive, truncate
b 2f
1:
@@ -2407,10 +2407,10 @@ underflow_s:
/*
* Now round the denormalized result.
*/
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
- beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, 3f # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FCSR_RM_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@@ -2432,16 +2432,16 @@ underflow_s:
move t1, zero # denorm or zero exponent
jal _C_LABEL(set_fd_s) # save result
beq t9, zero, done # check for exact result
- or a2, a2, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
- or a2, a2, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
- and v0, a2, MIPS_FPU_ENABLE_INEXACT
+ or a2, a2, MIPS_FCSR_CAUSE_U | MIPS_FCSR_FLAGS_U
+ or a2, a2, MIPS_FCSR_CAUSE_I | MIPS_FCSR_FLAGS_I
+ and v0, a2, MIPS_FCSR_ENABLES_I
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
b done
@@ -2545,10 +2545,10 @@ norm_noshift_d:
move ta1, t1 # save unrounded exponent
move ta2, t2 # save unrounded fraction (MS)
move ta3, t3 # save unrounded fraction (LS)
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
- beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, 3f # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FCSR_RM_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@@ -2592,15 +2592,15 @@ inexact_d:
and t2, t2, ~DIMPL_ONE # clear implied one bit
inexact_nobias_d:
jal _C_LABEL(set_fd_d) # save result
- or a2, a2, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
- and v0, a2, MIPS_FPU_ENABLE_INEXACT
+ or a2, a2, MIPS_FCSR_CAUSE_I | MIPS_FCSR_FLAGS_I
+ and v0, a2, MIPS_FCSR_ENABLES_I
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
b done
@@ -2610,18 +2610,18 @@ inexact_nobias_d:
* or generate an infinity.
*/
overflow_d:
- or a2, a2, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
- and v0, a2, MIPS_FPU_ENABLE_OVERFLOW
+ or a2, a2, MIPS_FCSR_CAUSE_O | MIPS_FCSR_FLAGS_O
+ and v0, a2, MIPS_FCSR_ENABLES_O
beq v0, zero, 1f
subu t1, t1, 1536 # bias exponent
and t2, t2, ~DIMPL_ONE # clear implied one bit
jal _C_LABEL(set_fd_d) # save result
b fpe_trap
1:
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate)
- beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, 3f # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, 1f # round to zero (truncate)
+ beq v0, MIPS_FCSR_RM_RP, 2f # round to +infinity
bne t0, zero, 3f
1:
li t1, DEXP_MAX # result is max finite
@@ -2641,7 +2641,7 @@ overflow_d:
* "loss of accuracy" is detected as "an inexact result".
*/
underflow_d:
- and v0, a2, MIPS_FPU_ENABLE_UNDERFLOW
+ and v0, a2, MIPS_FCSR_ENABLES_U
beq v0, zero, 1f
/*
* Underflow is enabled so compute the result and trap.
@@ -2649,7 +2649,7 @@ underflow_d:
addu t1, t1, 1536 # bias exponent
and t2, t2, ~DIMPL_ONE # clear implied one bit
jal _C_LABEL(set_fd_d) # save result
- or a2, a2, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ or a2, a2, MIPS_FCSR_CAUSE_U | MIPS_FCSR_FLAGS_U
b fpe_trap
/*
* Underflow is not enabled so compute the result,
@@ -2665,15 +2665,15 @@ underflow_d:
move t1, zero # result is inexact zero
move t2, zero
move t3, zero
- or a2, a2, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ or a2, a2, MIPS_FCSR_CAUSE_U | MIPS_FCSR_FLAGS_U
/*
* Now round the zero result.
* Only need to worry about rounding to +- infinity when the sign matches.
*/
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_d # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_d # round to zero
- beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, inexact_nobias_d # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, inexact_nobias_d # round to zero
+ beq v0, MIPS_FCSR_RM_RP, 1f # round to +infinity
beq t0, zero, inexact_nobias_d # if sign is positive, truncate
b 2f
1:
@@ -2709,10 +2709,10 @@ underflow_d:
* Now round the denormalized result.
*/
2:
- and v0, a2, MIPS_FPU_ROUNDING_BITS # get rounding mode
- beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
- beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
- beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ and v0, a2, MIPS_FCSR_RM # get rounding mode
+ beq v0, MIPS_FCSR_RM_RN, 3f # round to nearest
+ beq v0, MIPS_FCSR_RM_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FCSR_RM_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@@ -2738,16 +2738,16 @@ underflow_d:
move t1, zero # denorm or zero exponent
jal _C_LABEL(set_fd_d) # save result
beq t9, zero, done # check for exact result
- or a2, a2, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
- or a2, a2, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
- and v0, a2, MIPS_FPU_ENABLE_INEXACT
+ or a2, a2, MIPS_FCSR_CAUSE_U | MIPS_FCSR_FLAGS_U
+ or a2, a2, MIPS_FCSR_CAUSE_I | MIPS_FCSR_FLAGS_I
+ and v0, a2, MIPS_FCSR_ENABLES_I
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
b done
@@ -2756,15 +2756,15 @@ underflow_d:
* the result is a quiet NAN.
*/
invalid_s: # trap invalid operation
- or a2, a2, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
- and v0, a2, MIPS_FPU_ENABLE_INVALID
+ or a2, a2, MIPS_FCSR_CAUSE_V | MIPS_FCSR_FLAGS_V
+ and v0, a2, MIPS_FCSR_ENABLES_V
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
move t0, zero # result is a quiet NAN
li t1, SEXP_INF
@@ -2777,15 +2777,15 @@ invalid_s: # trap invalid operation
* the result is a quiet NAN.
*/
invalid_d: # trap invalid operation
- or a2, a2, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
- and v0, a2, MIPS_FPU_ENABLE_INVALID
+ or a2, a2, MIPS_FCSR_CAUSE_V | MIPS_FCSR_FLAGS_V
+ and v0, a2, MIPS_FCSR_ENABLES_V
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
move t0, zero # result is a quiet NAN
li t1, DEXP_INF
@@ -2799,15 +2799,15 @@ invalid_d: # trap invalid operation
* the result is INT_MAX or INT_MIN.
*/
invalid_w: # trap invalid operation
- or a2, a2, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
- and v0, a2, MIPS_FPU_ENABLE_INVALID
+ or a2, a2, MIPS_FCSR_CAUSE_V | MIPS_FCSR_FLAGS_V
+ and v0, a2, MIPS_FCSR_ENABLES_V
bne v0, zero, fpe_trap
#ifdef FPEMUL
PTR_L v0, L_PCB(MIPS_CURLWP) # get pcb of current lwp
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
bne t0, zero, 1f
li t2, INT_MAX # result is INT_MAX
@@ -2854,7 +2854,7 @@ ill:
#nop
INT_S a2, PCB_FPREGS+FRAME_FSR(v0)
#else
- ctc1 a2, MIPS_FPU_CSR # save exceptions
+ ctc1 a2, MIPS_FCSR # save exceptions
#endif
REG_L a1, CALLFRAME_FRAME(sp) # frame
REG_L a2, CALLFRAME_CAUSE(sp) # cause
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.227 src/sys/arch/mips/mips/locore.S:1.228
--- src/sys/arch/mips/mips/locore.S:1.227 Sun Apr 18 10:40:34 2021
+++ src/sys/arch/mips/mips/locore.S Sat May 29 12:35:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.227 2021/04/18 10:40:34 mrg Exp $ */
+/* $NetBSD: locore.S,v 1.228 2021/05/29 12:35:27 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -63,7 +63,7 @@
#include <mips/trap.h>
#include <mips/locore.h>
-RCSID("$NetBSD: locore.S,v 1.227 2021/04/18 10:40:34 mrg Exp $")
+RCSID("$NetBSD: locore.S,v 1.228 2021/05/29 12:35:27 simonb Exp $")
#include "assym.h"
@@ -162,7 +162,7 @@ EXPORT_OBJECT(kernel_text) # libkvm re
mtc0 k0, MIPS_COP_0_STATUS
COP0_HAZARD_FPUENABLE
- cfc1 t1, MIPS_FPU_ID
+ cfc1 t1, MIPS_FIR
/* Disable again, we don't want it on in the kernel */
and k0, ~MIPS_SR_COP_1_BIT
@@ -665,8 +665,8 @@ XNESTED(mips_fpu_trap)
REG_L a2, TF_REG_CAUSE(a1)
REG_EPILOGUE
- cfc1 t0, MIPS_FPU_CSR # stall til FP done
- cfc1 t0, MIPS_FPU_CSR # now get status
+ cfc1 t0, MIPS_FCSR # stall til FP done
+ cfc1 t0, MIPS_FCSR # now get status
nop
sll t2, t0, (31 - 17) # unimplemented operation?
bgez t2, 3f # no, normal trap
@@ -703,8 +703,8 @@ XNESTED(mips_fpu_trap)
REG_S a2, TF_REG_CAUSE(a1)
REG_EPILOGUE
- and t2, t0, ~MIPS_FPU_EXCEPTION_BITS
- ctc1 t2, MIPS_FPU_CSR
+ and t2, t0, ~MIPS_FCSR_CAUSE
+ ctc1 t2, MIPS_FCSR
move a1, a0 # code = instruction
jal _C_LABEL(mips_fpuillinst)
@@ -722,8 +722,8 @@ XNESTED(mips_fpu_trap)
REG_S a2, TF_REG_CAUSE(a1)
REG_EPILOGUE
- and a0, t0, ~MIPS_FPU_EXCEPTION_BITS
- ctc1 a0, MIPS_FPU_CSR
+ and a0, t0, ~MIPS_FCSR_CAUSE
+ ctc1 a0, MIPS_FCSR
move a1, t0 # FPU status
jal _C_LABEL(mips_fpuexcept)
Index: src/sys/arch/mips/mips/mips_emul.c
diff -u src/sys/arch/mips/mips/mips_emul.c:1.29 src/sys/arch/mips/mips/mips_emul.c:1.30
--- src/sys/arch/mips/mips/mips_emul.c:1.29 Thu May 27 15:00:02 2021
+++ src/sys/arch/mips/mips/mips_emul.c Sat May 29 12:35:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_emul.c,v 1.29 2021/05/27 15:00:02 simonb Exp $ */
+/* $NetBSD: mips_emul.c,v 1.30 2021/05/29 12:35:27 simonb Exp $ */
/*
* Copyright (c) 1999 Shuichiro URATA. All rights reserved.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.29 2021/05/27 15:00:02 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.30 2021/05/29 12:35:27 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -155,7 +155,7 @@ mips_emul_branch(struct trapframe *tf, v
case OP_COP1:
if (inst.RType.rs == OP_BCx || inst.RType.rs == OP_BCy) {
- int condition = (fpuCSR & MIPS_FPU_COND_BIT) != 0;
+ int condition = (fpuCSR & MIPS_FCSR_FCC0) != 0;
if ((inst.RType.rt & COPz_BC_TF_MASK) != COPz_BC_TRUE)
condition = !condition;
if (condition)
Index: src/sys/arch/mips/mips/mips_fpu.c
diff -u src/sys/arch/mips/mips/mips_fpu.c:1.16 src/sys/arch/mips/mips/mips_fpu.c:1.17
--- src/sys/arch/mips/mips/mips_fpu.c:1.16 Tue May 11 14:41:08 2021
+++ src/sys/arch/mips/mips/mips_fpu.c Sat May 29 12:35:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_fpu.c,v 1.16 2021/05/11 14:41:08 simonb Exp $ */
+/* $NetBSD: mips_fpu.c,v 1.17 2021/05/29 12:35:27 simonb Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_fpu.c,v 1.16 2021/05/11 14:41:08 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_fpu.c,v 1.17 2021/05/29 12:35:27 simonb Exp $");
#include <sys/param.h>
#include <sys/mutex.h>
@@ -336,8 +336,10 @@ mips_fpu_state_load(lwp_t *l, u_int flag
#endif
/*
- * load FPCSR and stop COP1 again
+ * Mask off the exception bits in the FPCSR, load the FPCSR
+ * and stop COP1 again
*/
+ fpcsr &= ~MIPS_FCSR_CAUSE;
__asm volatile(
".set noreorder" "\n\t"
".set noat" "\n\t"
@@ -346,7 +348,7 @@ mips_fpu_state_load(lwp_t *l, u_int flag
"mtc0 %1, $%2" "\n\t"
".set at" "\n\t"
".set reorder" "\n\t"
- :: "r"(fpcsr &~ MIPS_FPU_EXCEPTION_BITS), "r"(status),
+ :: "r"(fpcsr), "r"(status),
"n"(MIPS_COP_0_STATUS));
}
Index: src/sys/arch/mips/mips/mips_fputrap.c
diff -u src/sys/arch/mips/mips/mips_fputrap.c:1.11 src/sys/arch/mips/mips/mips_fputrap.c:1.12
--- src/sys/arch/mips/mips/mips_fputrap.c:1.11 Thu May 13 03:41:46 2021
+++ src/sys/arch/mips/mips/mips_fputrap.c Sat May 29 12:35:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_fputrap.c,v 1.11 2021/05/13 03:41:46 simonb Exp $ */
+/* $NetBSD: mips_fputrap.c,v 1.12 2021/05/29 12:35:27 simonb Exp $ */
/*
* Copyright (c) 2004
@@ -80,12 +80,12 @@ static const struct {
unsigned int bit;
int code;
} fpecodes[] = {
- { MIPS_FPU_EXCEPTION_UNDERFLOW, FPE_FLTUND },
- { MIPS_FPU_EXCEPTION_OVERFLOW, FPE_FLTOVF },
- { MIPS_FPU_EXCEPTION_INEXACT, FPE_FLTRES },
- { MIPS_FPU_EXCEPTION_DIV0, FPE_FLTDIV },
- { MIPS_FPU_EXCEPTION_INVALID, FPE_FLTINV },
- { MIPS_FPU_EXCEPTION_UNIMPL, FPE_FLTINV }
+ { MIPS_FCSR_CAUSE_I, FPE_FLTRES },
+ { MIPS_FCSR_CAUSE_U, FPE_FLTUND },
+ { MIPS_FCSR_CAUSE_O, FPE_FLTOVF },
+ { MIPS_FCSR_CAUSE_Z, FPE_FLTDIV },
+ { MIPS_FCSR_CAUSE_V, FPE_FLTINV },
+ { MIPS_FCSR_CAUSE_E, FPE_FLTINV }
};
static int
