Module Name: src
Committed By: skrll
Date: Wed Jul 28 07:32:20 UTC 2021
Modified Files:
src/common/lib/libc/arch/arm/atomic: atomic_add_16.S atomic_add_32.S
atomic_add_64.S atomic_add_8.S atomic_and_16.S atomic_and_32.S
atomic_and_64.S atomic_and_8.S atomic_cas_16.S atomic_cas_32.S
atomic_cas_64.S atomic_cas_8.S atomic_dec_32.S atomic_dec_64.S
atomic_inc_32.S atomic_inc_64.S atomic_nand_16.S atomic_nand_32.S
atomic_nand_64.S atomic_nand_8.S atomic_op_asm.h atomic_or_16.S
atomic_or_32.S atomic_or_64.S atomic_or_8.S atomic_sub_64.S
atomic_swap.S atomic_swap_16.S atomic_swap_64.S atomic_xor_16.S
atomic_xor_32.S atomic_xor_64.S atomic_xor_8.S membar_ops.S
sync_bool_compare_and_swap_1.S sync_bool_compare_and_swap_2.S
sync_bool_compare_and_swap_4.S sync_bool_compare_and_swap_8.S
sync_fetch_and_add_8.S sync_fetch_and_and_8.S
sync_fetch_and_nand_8.S sync_fetch_and_or_8.S
sync_fetch_and_sub_8.S sync_fetch_and_xor_8.S
Log Message:
Remove memory barriers from the atomic_ops(3) atomic operations. They're
not needed for correctness.
Add the correct memory barriers to the gcc legacy __sync built-in
functions for atomic memory access. From the gcc documentation:
In most cases, these built-in functions are considered a full barrier.
That is, no memory operand is moved across the operation, either forward
or backward. Further, instructions are issued as necessary to prevent the
processor from speculating loads across the operation and from queuing
stores after the operation.
type __sync_lock_test_and_set (type *ptr, type value, ...)
This built-in function is not a full barrier, but rather an acquire
barrier. This means that references after the operation cannot move to
(or be speculated to) before the operation, but previous memory stores
may not be globally visible yet, and previous memory loads may not yet
be satisfied.
void __sync_lock_release (type *ptr, ...)
This built-in function is not a full barrier, but rather a release
barrier. This means that all previous memory stores are globally
visible, and all previous memory loads have been satisfied, but
following memory reads are not prevented from being speculated to
before the barrier.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/common/lib/libc/arch/arm/atomic/atomic_add_16.S \
src/common/lib/libc/arch/arm/atomic/atomic_add_8.S \
src/common/lib/libc/arch/arm/atomic/atomic_and_16.S \
src/common/lib/libc/arch/arm/atomic/atomic_and_8.S \
src/common/lib/libc/arch/arm/atomic/atomic_nand_16.S \
src/common/lib/libc/arch/arm/atomic/atomic_nand_32.S \
src/common/lib/libc/arch/arm/atomic/atomic_nand_8.S \
src/common/lib/libc/arch/arm/atomic/atomic_or_16.S \
src/common/lib/libc/arch/arm/atomic/atomic_or_8.S \
src/common/lib/libc/arch/arm/atomic/atomic_sub_64.S \
src/common/lib/libc/arch/arm/atomic/atomic_xor_16.S \
src/common/lib/libc/arch/arm/atomic/atomic_xor_32.S \
src/common/lib/libc/arch/arm/atomic/atomic_xor_8.S \
src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S
cvs rdiff -u -r1.9 -r1.10 src/common/lib/libc/arch/arm/atomic/atomic_add_32.S \
src/common/lib/libc/arch/arm/atomic/atomic_and_32.S \
src/common/lib/libc/arch/arm/atomic/atomic_or_32.S
cvs rdiff -u -r1.13 -r1.14 \
src/common/lib/libc/arch/arm/atomic/atomic_add_64.S \
src/common/lib/libc/arch/arm/atomic/atomic_or_64.S \
src/common/lib/libc/arch/arm/atomic/atomic_swap_64.S
cvs rdiff -u -r1.12 -r1.13 \
src/common/lib/libc/arch/arm/atomic/atomic_and_64.S
cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/arch/arm/atomic/atomic_cas_16.S
cvs rdiff -u -r1.7 -r1.8 src/common/lib/libc/arch/arm/atomic/atomic_cas_32.S
cvs rdiff -u -r1.11 -r1.12 \
src/common/lib/libc/arch/arm/atomic/atomic_cas_64.S
cvs rdiff -u -r1.8 -r1.9 src/common/lib/libc/arch/arm/atomic/atomic_cas_8.S \
src/common/lib/libc/arch/arm/atomic/atomic_dec_64.S \
src/common/lib/libc/arch/arm/atomic/atomic_inc_32.S \
src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h \
src/common/lib/libc/arch/arm/atomic/membar_ops.S
cvs rdiff -u -r1.6 -r1.7 src/common/lib/libc/arch/arm/atomic/atomic_dec_32.S \
src/common/lib/libc/arch/arm/atomic/atomic_nand_64.S \
src/common/lib/libc/arch/arm/atomic/atomic_swap_16.S \
src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S
cvs rdiff -u -r1.10 -r1.11 \
src/common/lib/libc/arch/arm/atomic/atomic_inc_64.S
cvs rdiff -u -r1.18 -r1.19 src/common/lib/libc/arch/arm/atomic/atomic_swap.S
cvs rdiff -u -r1.3 -r1.4 \
src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S \
src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S \
src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S
cvs rdiff -u -r1.5 -r1.6 \
src/common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S \
src/common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S \
src/common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S \
src/common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S \
src/common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S \
src/common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/atomic/atomic_add_16.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_add_16.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_add_16.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_add_16.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_add_16.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_add_16.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_add_16.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -43,11 +43,6 @@ ENTRY_NP(_atomic_add_16)
strexh r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_add_16)
END(_atomic_sub_16)
@@ -55,7 +50,6 @@ END(_atomic_sub_16)
ATOMIC_OP_ALIAS(atomic_add_16,_atomic_add_16)
ATOMIC_OP_ALIAS(atomic_add_short,_atomic_add_16)
ATOMIC_OP_ALIAS(atomic_add_ushort,_atomic_add_16)
-CRT_ALIAS(__sync_fetch_and_add_2,_atomic_add_16)
CRT_ALIAS(__atomic_fetch_add_2,_atomic_add_16)
STRONG_ALIAS(_atomic_add_short,_atomic_add_16)
STRONG_ALIAS(_atomic_add_ushort,_atomic_add_16)
@@ -63,11 +57,27 @@ STRONG_ALIAS(_atomic_add_ushort,_atomic_
ATOMIC_OP_ALIAS(atomic_sub_16,_atomic_sub_16)
ATOMIC_OP_ALIAS(atomic_sub_short,_atomic_sub_16)
ATOMIC_OP_ALIAS(atomic_sub_ushort,_atomic_sub_16)
-CRT_ALIAS(__sync_fetch_and_sub_2,_atomic_sub_16)
CRT_ALIAS(__atomic_fetch_sub_2,_atomic_sub_16)
STRONG_ALIAS(_atomic_sub_short,_atomic_sub_16)
STRONG_ALIAS(_atomic_sub_ushort,_atomic_sub_16)
+ENTRY_NP(__sync_fetch_and_add_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_add_16
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_add_2)
+
+ENTRY_NP(__sync_fetch_and_sub_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_sub_16
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_sub_2)
+
+
ENTRY_NP(_atomic_sub_16_nv)
negs r1, r1
/* FALLTHROUGH */
@@ -78,25 +88,35 @@ ENTRY_NP(_atomic_add_16_nv)
strexh r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_add_16_nv)
END(_atomic_sub_16_nv)
+
ATOMIC_OP_ALIAS(atomic_add_16_nv,_atomic_add_16_nv)
ATOMIC_OP_ALIAS(atomic_add_short_nv,_atomic_add_16_nv)
ATOMIC_OP_ALIAS(atomic_add_ushort_nv,_atomic_add_16_nv)
-CRT_ALIAS(__sync_add_and_fetch_2,_atomic_add_16_nv)
STRONG_ALIAS(_atomic_add_short_nv,_atomic_add_16_nv)
STRONG_ALIAS(_atomic_add_ushort_nv,_atomic_add_16_nv)
-
ATOMIC_OP_ALIAS(atomic_sub_16_nv,_atomic_sub_16_nv)
ATOMIC_OP_ALIAS(atomic_sub_short_nv,_atomic_sub_16_nv)
ATOMIC_OP_ALIAS(atomic_sub_ushort_nv,_atomic_sub_16_nv)
-CRT_ALIAS(__sync_sub_and_fetch_2,_atomic_sub_16_nv)
STRONG_ALIAS(_atomic_sub_short_nv,_atomic_sub_16_nv)
STRONG_ALIAS(_atomic_sub_ushort_nv,_atomic_sub_16_nv)
+
+ENTRY_NP(__sync_add_and_fetch_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_add_16_nv
+ DMB
+ pop {r4, pc}
+END(__sync_add_and_fetch_2)
+
+ENTRY_NP(__sync_sub_and_fetch_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_sub_16_nv
+ DMB
+ pop {r4, pc}
+END(__sync_sub_and_fetch_2)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_add_8.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_add_8.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_add_8.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_add_8.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_add_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_add_8.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_add_8.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -43,11 +43,6 @@ ENTRY_NP(_atomic_add_8)
strexb r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_add_8)
END(_atomic_sub_8)
@@ -55,19 +50,34 @@ END(_atomic_sub_8)
ATOMIC_OP_ALIAS(atomic_add_8,_atomic_add_8)
ATOMIC_OP_ALIAS(atomic_add_char,_atomic_add_8)
ATOMIC_OP_ALIAS(atomic_add_uchar,_atomic_add_8)
-CRT_ALIAS(__sync_fetch_and_add_1,_atomic_add_8)
CRT_ALIAS(__atomic_fetch_add_1,_atomic_add_8)
STRONG_ALIAS(_atomic_add_char,_atomic_add_8)
STRONG_ALIAS(_atomic_add_uchar,_atomic_add_8)
+ENTRY_NP(__sync_fetch_and_add_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_add_8
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_add_1)
+
+ENTRY_NP(__sync_fetch_and_sub_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_sub_8
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_sub_1)
+
ATOMIC_OP_ALIAS(atomic_sub_8,_atomic_sub_8)
ATOMIC_OP_ALIAS(atomic_sub_char,_atomic_sub_8)
ATOMIC_OP_ALIAS(atomic_sub_uchar,_atomic_sub_8)
-CRT_ALIAS(__sync_fetch_and_sub_1,_atomic_sub_8)
CRT_ALIAS(__atomic_fetch_sub_1,_atomic_sub_8)
STRONG_ALIAS(_atomic_sub_char,_atomic_sub_8)
STRONG_ALIAS(_atomic_sub_uchar,_atomic_sub_8)
+
ENTRY_NP(_atomic_sub_8_nv)
negs r1, r1
/* FALLTHROUGH */
@@ -78,25 +88,36 @@ ENTRY_NP(_atomic_add_8_nv)
strexb r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_add_8_nv)
END(_atomic_sub_8_nv)
+
ATOMIC_OP_ALIAS(atomic_add_8_nv,_atomic_add_8_nv)
ATOMIC_OP_ALIAS(atomic_add_char_nv,_atomic_add_8_nv)
ATOMIC_OP_ALIAS(atomic_add_uchar_nv,_atomic_add_8_nv)
-CRT_ALIAS(__sync_add_and_fetch_1,_atomic_add_8_nv)
STRONG_ALIAS(_atomic_add_char_nv,_atomic_add_8_nv)
STRONG_ALIAS(_atomic_add_uchar_nv,_atomic_add_8_nv)
ATOMIC_OP_ALIAS(atomic_sub_8_nv,_atomic_sub_8_nv)
ATOMIC_OP_ALIAS(atomic_sub_char_nv,_atomic_sub_8_nv)
ATOMIC_OP_ALIAS(atomic_sub_uchar_nv,_atomic_sub_8_nv)
-CRT_ALIAS(__sync_sub_and_fetch_1,_atomic_sub_8_nv)
STRONG_ALIAS(_atomic_sub_char_nv,_atomic_sub_8_nv)
STRONG_ALIAS(_atomic_sub_uchar_nv,_atomic_sub_8_nv)
+
+ENTRY_NP(__sync_add_and_fetch_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_add_8_nv
+ DMB
+ pop {r4, pc}
+END(__sync_add_and_fetch_1)
+
+ENTRY_NP(__sync_sub_and_fetch_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_sub_8_nv
+ DMB
+ pop {r4, pc}
+END(__sync_sub_and_fetch_1)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_and_16.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_and_16.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_and_16.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_and_16.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_and_16.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_and_16.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_and_16.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,20 +40,23 @@ ENTRY_NP(_atomic_and_16)
strexh r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_and_16)
ATOMIC_OP_ALIAS(atomic_and_16,_atomic_and_16)
ATOMIC_OP_ALIAS(atomic_and_ushort,_atomic_and_16)
-CRT_ALIAS(__sync_fetch_and_and_2,_atomic_and_16)
CRT_ALIAS(__atomic_fetch_and_2,_atomic_and_16)
STRONG_ALIAS(_atomic_and_ushort,_atomic_and_16)
+ENTRY_NP(__sync_fetch_and_and_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_and_16
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_and_2)
+
+
ENTRY_NP(_atomic_and_16_nv)
mov ip, r0 /* need r0 for return value */
1: ldrexh r0, [ip] /* load old value */
@@ -61,17 +64,20 @@ ENTRY_NP(_atomic_and_16_nv)
strexh r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_and_16_nv)
ATOMIC_OP_ALIAS(atomic_and_16_nv,_atomic_and_16_nv)
ATOMIC_OP_ALIAS(atomic_and_ushort_nv,_atomic_and_16_nv)
-CRT_ALIAS(__sync_and_and_fetch_2,_atomic_and_16_nv)
STRONG_ALIAS(_atomic_and_ushort_nv,_atomic_and_16_nv)
+ENTRY_NP(__sync_and_and_fetch_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_and_16_nv
+ DMB
+ pop {r4, pc}
+END(__sync_and_and_fetch_2)
+
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_and_8.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_and_8.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_and_8.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_and_8.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_and_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_and_8.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_and_8.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,20 +40,23 @@ ENTRY_NP(_atomic_and_8)
strexb r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_and_8)
ATOMIC_OP_ALIAS(atomic_and_8,_atomic_and_8)
ATOMIC_OP_ALIAS(atomic_and_uchar,_atomic_and_8)
-CRT_ALIAS(__sync_fetch_and_and_1,_atomic_and_8)
CRT_ALIAS(__atomic_fetch_and_1,_atomic_and_8)
STRONG_ALIAS(_atomic_and_uchar,_atomic_and_8)
+ENTRY_NP(__sync_fetch_and_and_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_and_8
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_and_1)
+
+
ENTRY_NP(_atomic_and_8_nv)
mov ip, r0 /* need r0 for return value */
1: ldrexb r0, [ip] /* load old value */
@@ -61,17 +64,20 @@ ENTRY_NP(_atomic_and_8_nv)
strexb r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_and_8_nv)
ATOMIC_OP_ALIAS(atomic_and_8_nv,_atomic_and_8_nv)
ATOMIC_OP_ALIAS(atomic_and_uchar_nv,_atomic_and_8_nv)
-CRT_ALIAS(__sync_and_and_fetch_1,_atomic_and_8_nv)
STRONG_ALIAS(_atomic_and_uchar_nv,_atomic_and_8_nv)
+ENTRY_NP(__sync_and_and_fetch_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_and_8_nv
+ DMB
+ pop {r4, pc}
+END(__sync_and_and_fetch_1)
+
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_nand_16.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_nand_16.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_nand_16.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_nand_16.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_nand_16.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_nand_16.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_nand_16.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -41,19 +41,22 @@ ENTRY_NP(_atomic_nand_16)
strexh r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_nand_16)
ATOMIC_OP_ALIAS(atomic_nand_16,_atomic_nand_16)
ATOMIC_OP_ALIAS(atomic_nand_ushort,_atomic_nand_16)
-CRT_ALIAS(__sync_fetch_and_nand_2,_atomic_nand_16)
STRONG_ALIAS(_atomic_nand_ushort,_atomic_nand_16)
+ENTRY_NP(__sync_fetch_and_nand_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_nand_16
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_nand_2)
+
+
ENTRY_NP(_atomic_nand_16_nv)
mov ip, r0 /* need r0 for return value */
1: ldrexh r0, [ip] /* load old value */
@@ -62,17 +65,20 @@ ENTRY_NP(_atomic_nand_16_nv)
strexh r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_nand_16_nv)
ATOMIC_OP_ALIAS(atomic_nand_16_nv,_atomic_nand_16_nv)
ATOMIC_OP_ALIAS(atomic_nand_ushort_nv,_atomic_nand_16_nv)
-CRT_ALIAS(__sync_nand_and_fetch_2,_atomic_nand_16_nv)
STRONG_ALIAS(_atomic_nand_ushort_nv,_atomic_nand_16_nv)
+ENTRY_NP(__sync_nand_and_fetch_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_nand_16_nv
+ DMB
+ pop {r4, pc}
+END(__sync_nand_and_fetch_2)
+
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_nand_32.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_nand_32.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_nand_32.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_nand_32.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_nand_32.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_nand_32.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_nand_32.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -41,21 +41,24 @@ ENTRY_NP(_atomic_nand_32)
strex r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_nand_32)
ATOMIC_OP_ALIAS(atomic_nand_32,_atomic_nand_32)
ATOMIC_OP_ALIAS(atomic_nand_uint,_atomic_nand_32)
ATOMIC_OP_ALIAS(atomic_nand_ulong,_atomic_nand_32)
-CRT_ALIAS(__sync_fetch_and_nand_4,_atomic_nand_32)
STRONG_ALIAS(_atomic_nand_uint,_atomic_nand_32)
STRONG_ALIAS(_atomic_nand_ulong,_atomic_nand_32)
+ENTRY_NP(__sync_fetch_and_nand_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_nand_32
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_nand_4)
+
+
ENTRY_NP(_atomic_nand_32_nv)
mov ip, r0 /* need r0 for return value */
1: ldrex r0, [ip] /* load old value */
@@ -64,19 +67,22 @@ ENTRY_NP(_atomic_nand_32_nv)
strex r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_nand_32_nv)
ATOMIC_OP_ALIAS(atomic_nand_32_nv,_atomic_nand_32_nv)
ATOMIC_OP_ALIAS(atomic_nand_uint_nv,_atomic_nand_32_nv)
ATOMIC_OP_ALIAS(atomic_nand_ulong_nv,_atomic_nand_32_nv)
-CRT_ALIAS(__sync_nand_and_fetch_4,_atomic_nand_32_nv)
STRONG_ALIAS(_atomic_nand_uint_nv,_atomic_nand_32_nv)
STRONG_ALIAS(_atomic_nand_ulong_nv,_atomic_nand_32_nv)
+ENTRY_NP(__sync_nand_and_fetch_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_nand_32_nv
+ DMB
+ pop {r4, pc}
+END(__sync_nand_and_fetch_4)
+
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_nand_8.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_nand_8.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_nand_8.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_nand_8.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_nand_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_nand_8.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_nand_8.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -41,19 +41,22 @@ ENTRY_NP(_atomic_nand_8)
strexb r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_nand_8)
ATOMIC_OP_ALIAS(atomic_nand_8,_atomic_nand_8)
ATOMIC_OP_ALIAS(atomic_nand_uchar,_atomic_nand_8)
-CRT_ALIAS(__sync_fetch_and_nand_1,_atomic_nand_8)
STRONG_ALIAS(_atomic_nand_uchar,_atomic_nand_8)
+ENTRY_NP(__sync_fetch_and_nand_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_nand_8
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_nand_1)
+
+
ENTRY_NP(_atomic_nand_8_nv)
mov ip, r0 /* need r0 for return value */
1: ldrexb r0, [ip] /* load old value */
@@ -62,17 +65,20 @@ ENTRY_NP(_atomic_nand_8_nv)
strexb r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_nand_8_nv)
ATOMIC_OP_ALIAS(atomic_nand_8_nv,_atomic_nand_8_nv)
ATOMIC_OP_ALIAS(atomic_nand_uchar_nv,_atomic_nand_8_nv)
-CRT_ALIAS(__sync_nand_and_fetch_1,_atomic_nand_8_nv)
STRONG_ALIAS(_atomic_nand_uchar_nv,_atomic_nand_8_nv)
+ENTRY_NP(__sync_nand_and_fetch_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_nand_8_nv
+ DMB
+ pop {r4, pc}
+END(__sync_nand_and_fetch_1)
+
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_or_16.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_or_16.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_or_16.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_or_16.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_or_16.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_or_16.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_or_16.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,20 +39,23 @@ ENTRY_NP(_atomic_or_16)
strexh r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_or_16)
ATOMIC_OP_ALIAS(atomic_or_16,_atomic_or_16)
ATOMIC_OP_ALIAS(atomic_or_ushort,_atomic_or_16)
-CRT_ALIAS(__sync_fetch_and_or_2,_atomic_or_16)
CRT_ALIAS(__atomic_fetch_or_2,_atomic_or_16)
STRONG_ALIAS(_atomic_or_ushort,_atomic_or_16)
+ENTRY_NP(__sync_fetch_and_or_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_or_16
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_or_2)
+
+
ENTRY_NP(_atomic_or_16_nv)
mov ip, r0 /* need r0 for return value */
1: ldrexh r0, [ip] /* load old value */
@@ -60,17 +63,19 @@ ENTRY_NP(_atomic_or_16_nv)
strexh r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_or_16_nv)
ATOMIC_OP_ALIAS(atomic_or_16_nv,_atomic_or_16_nv)
ATOMIC_OP_ALIAS(atomic_or_ushort_nv,_atomic_or_16_nv)
-CRT_ALIAS(__sync_or_and_fetch_2,_atomic_or_16_nv)
STRONG_ALIAS(_atomic_or_ushort_nv,_atomic_or_16_nv)
+ENTRY_NP(__sync_or_and_fetch_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_or_16_nv
+ DMB
+ pop {r4, pc}
+END(__sync_or_and_fetch_2)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_or_8.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_or_8.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_or_8.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_or_8.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_or_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_or_8.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_or_8.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,20 +40,23 @@ ENTRY_NP(_atomic_or_8)
strexb r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_or_8)
ATOMIC_OP_ALIAS(atomic_or_8,_atomic_or_8)
ATOMIC_OP_ALIAS(atomic_or_char,_atomic_or_8)
-CRT_ALIAS(__sync_fetch_and_or_1,_atomic_or_8)
CRT_ALIAS(__atomic_fetch_or_1,_atomic_or_8)
STRONG_ALIAS(_atomic_or_char,_atomic_or_8)
+ENTRY_NP(__sync_fetch_and_or_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_or_8
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_or_1)
+
+
ENTRY_NP(_atomic_or_8_nv)
mov ip, r0 /* need r0 for return value */
1: ldrexb r0, [ip] /* load old value */
@@ -61,17 +64,19 @@ ENTRY_NP(_atomic_or_8_nv)
strexb r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_or_8_nv)
ATOMIC_OP_ALIAS(atomic_or_8_nv,_atomic_or_8_nv)
ATOMIC_OP_ALIAS(atomic_or_char_nv,_atomic_or_8_nv)
-CRT_ALIAS(__sync_or_and_fetch_1,_atomic_or_8_nv)
STRONG_ALIAS(_atomic_or_char_nv,_atomic_or_8_nv)
+ENTRY_NP(__sync_or_and_fetch_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_or_8_nv
+ DMB
+ pop {r4, pc}
+END(__sync_or_and_fetch_1)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_sub_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_sub_64.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_sub_64.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_sub_64.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_sub_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_sub_64.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_sub_64.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -46,11 +46,6 @@ ENTRY_NP(_atomic_sub_64_nv)
strexd r4, r0, [ip] /* try to store */
cmp r4, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r4, c7, c10, 5 /* data memory barrier */
-#endif
pop {r3, r4} /* restore temporary */
RET /* return new value */
END(_atomic_sub_64_nv)
@@ -58,6 +53,14 @@ END(_atomic_sub_64_nv)
STRONG_ALIAS(_atomic_sub_64,_atomic_sub_64_nv)
ATOMIC_OP_ALIAS(atomic_sub_64_nv,_atomic_sub_64_nv)
ATOMIC_OP_ALIAS(atomic_sub_64,_atomic_sub_64)
-CRT_ALIAS(__sync_sub_and_fetch_8,_atomic_sub_64_nv)
+
+ENTRY_NP(__sync_sub_and_fetch_8)
+ push {r4, lr}
+ DMB
+ bl _atomic_sub_64_nv
+ DMB
+ pop {r4, pc}
+END(__sync_sub_and_fetch_8)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_xor_16.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_xor_16.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_xor_16.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_xor_16.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_xor_16.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_xor_16.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_xor_16.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,20 +40,23 @@ ENTRY_NP(_atomic_xor_16)
strexh r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_xor_16)
ATOMIC_OP_ALIAS(atomic_xor_16,_atomic_xor_16)
ATOMIC_OP_ALIAS(atomic_xor_ushort,_atomic_xor_16)
-CRT_ALIAS(__sync_fetch_and_xor_2,_atomic_xor_16)
CRT_ALIAS(__atomic_fetch_xor_2,_atomic_xor_16)
STRONG_ALIAS(_atomic_xor_ushort,_atomic_xor_16)
+ENTRY_NP(__sync_fetch_and_xor_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_xor_16
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_xor_2)
+
+
ENTRY_NP(_atomic_xor_16_nv)
mov ip, r0 /* need r0 for return value */
1: ldrexh r0, [ip] /* load old value */
@@ -61,17 +64,19 @@ ENTRY_NP(_atomic_xor_16_nv)
strexh r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_xor_16_nv)
ATOMIC_OP_ALIAS(atomic_xor_16_nv,_atomic_xor_16_nv)
ATOMIC_OP_ALIAS(atomic_xor_ushort_nv,_atomic_xor_16_nv)
-CRT_ALIAS(__sync_xor_and_fetch_2,_atomic_xor_16_nv)
STRONG_ALIAS(_atomic_xor_ushort_nv,_atomic_xor_16_nv)
+ENTRY_NP(__sync_xor_and_fetch_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_xor_16_nv
+ DMB
+ pop {r4, pc}
+END(__sync_xor_and_fetch_2)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_xor_32.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_xor_32.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_xor_32.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_xor_32.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_xor_32.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_xor_32.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_xor_32.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,22 +39,24 @@ ENTRY_NP(_atomic_xor_32)
strex r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_xor_32)
ATOMIC_OP_ALIAS(atomic_xor_32,_atomic_xor_32)
ATOMIC_OP_ALIAS(atomic_xor_uint,_atomic_xor_32)
ATOMIC_OP_ALIAS(atomic_xor_ulong,_atomic_xor_32)
-CRT_ALIAS(__sync_fetch_and_xor_4,_atomic_xor_32)
CRT_ALIAS(__atomic_fetch_xor_4,_atomic_xor_32)
STRONG_ALIAS(_atomic_xor_uint,_atomic_xor_32)
STRONG_ALIAS(_atomic_xor_ulong,_atomic_xor_32)
+ENTRY_NP(__sync_fetch_and_xor_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_xor_32
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_xor_4)
+
ENTRY_NP(_atomic_xor_32_nv)
mov ip, r0 /* need r0 for return value */
1: ldrex r0, [ip] /* load old value */
@@ -62,19 +64,22 @@ ENTRY_NP(_atomic_xor_32_nv)
strex r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_xor_32_nv)
ATOMIC_OP_ALIAS(atomic_xor_32_nv,_atomic_xor_32_nv)
ATOMIC_OP_ALIAS(atomic_xor_uint_nv,_atomic_xor_32_nv)
ATOMIC_OP_ALIAS(atomic_xor_ulong_nv,_atomic_xor_32_nv)
-CRT_ALIAS(__sync_xor_and_fetch_4,_atomic_xor_32_nv)
STRONG_ALIAS(_atomic_xor_uint_nv,_atomic_xor_32_nv)
STRONG_ALIAS(_atomic_xor_ulong_nv,_atomic_xor_32_nv)
+ENTRY_NP(__sync_xor_and_fetch_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_xor_32_nv
+ DMB
+ pop {r4, pc}
+END(__sync_xor_and_fetch_4)
+
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_xor_8.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_xor_8.S:1.4 src/common/lib/libc/arch/arm/atomic/atomic_xor_8.S:1.5
--- src/common/lib/libc/arch/arm/atomic/atomic_xor_8.S:1.4 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_xor_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_xor_8.S,v 1.4 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_xor_8.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,20 +40,23 @@ ENTRY_NP(_atomic_xor_8)
strexb r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_xor_8)
ATOMIC_OP_ALIAS(atomic_xor_8,_atomic_xor_8)
ATOMIC_OP_ALIAS(atomic_xor_uchar,_atomic_xor_8)
-CRT_ALIAS(__sync_fetch_and_xor_1,_atomic_xor_8)
CRT_ALIAS(__atomic_fetch_xor_1,_atomic_xor_8)
STRONG_ALIAS(_atomic_xor_uchar,_atomic_xor_8)
+ENTRY_NP(__sync_fetch_and_xor_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_xor_8
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_xor_1)
+
+
ENTRY_NP(_atomic_xor_8_nv)
mov ip, r0 /* need r0 for return value */
1: ldrexb r0, [ip] /* load old value */
@@ -61,17 +64,19 @@ ENTRY_NP(_atomic_xor_8_nv)
strexb r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_xor_8_nv)
ATOMIC_OP_ALIAS(atomic_xor_8_nv,_atomic_xor_8_nv)
ATOMIC_OP_ALIAS(atomic_xor_uchar_nv,_atomic_xor_8_nv)
-CRT_ALIAS(__sync_xor_and_fetch_1,_atomic_xor_8_nv)
STRONG_ALIAS(_atomic_xor_uchar_nv,_atomic_xor_8_nv)
+ENTRY_NP(__sync_xor_and_fetch_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_xor_8_nv
+ DMB
+ pop {r4, pc}
+END(__sync_xor_and_fetch_1)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S:1.4 src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S:1.5
--- src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S:1.4 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_bool_compare_and_swap_8.S,v 1.4 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_bool_compare_and_swap_8.S,v 1.5 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,6 +31,7 @@
#include "atomic_op_asm.h"
#if defined(_ARM_ARCH_6)
+
/*
* ARMv6 has load-exclusive/store-exclusive which works for both user
* and kernel.
@@ -61,11 +62,6 @@ ENTRY_NP(__sync_bool_compare_and_swap_8)
cmp r0, #0 /* succeed? */
bne 1b /* nope, try again. */
movs r0, #1 /* indicate success */
-#ifdef _ARM_ARCH_7
- dsb
-#else
- mcr p15, 0, ip, c7, c10, 4 /* data synchronization barrier */
-#endif
2: pop {r4-r7} /* restore temporaries */
RET /* return. */
END(__sync_bool_compare_and_swap_8)
Index: src/common/lib/libc/arch/arm/atomic/atomic_add_32.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_add_32.S:1.9 src/common/lib/libc/arch/arm/atomic/atomic_add_32.S:1.10
--- src/common/lib/libc/arch/arm/atomic/atomic_add_32.S:1.9 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_add_32.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_add_32.S,v 1.9 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_add_32.S,v 1.10 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -43,20 +43,31 @@ ENTRY_NP(_atomic_add_32)
strex r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_add_32)
END(_atomic_sub_32)
+ENTRY_NP(__sync_fetch_and_add_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_add_32
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_add_4)
+
+ENTRY_NP(__sync_fetch_and_sub_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_add_32
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_sub_4)
+
+
ATOMIC_OP_ALIAS(atomic_add_32,_atomic_add_32)
ATOMIC_OP_ALIAS(atomic_add_int,_atomic_add_32)
ATOMIC_OP_ALIAS(atomic_add_long,_atomic_add_32)
ATOMIC_OP_ALIAS(atomic_add_ptr,_atomic_add_32)
-CRT_ALIAS(__sync_fetch_and_add_4,_atomic_add_32)
CRT_ALIAS(__atomic_fetch_add_4,_atomic_add_32)
STRONG_ALIAS(_atomic_add_int,_atomic_add_32)
STRONG_ALIAS(_atomic_add_long,_atomic_add_32)
@@ -66,7 +77,6 @@ ATOMIC_OP_ALIAS(atomic_sub_32,_atomic_su
ATOMIC_OP_ALIAS(atomic_sub_int,_atomic_sub_32)
ATOMIC_OP_ALIAS(atomic_sub_long,_atomic_sub_32)
ATOMIC_OP_ALIAS(atomic_sub_ptr,_atomic_sub_32)
-CRT_ALIAS(__sync_fetch_and_sub_4,_atomic_sub_32)
CRT_ALIAS(__atomic_fetch_sub_4,_atomic_sub_32)
STRONG_ALIAS(_atomic_sub_int,_atomic_sub_32)
STRONG_ALIAS(_atomic_sub_long,_atomic_sub_32)
@@ -82,19 +92,14 @@ ENTRY_NP(_atomic_add_32_nv)
strex r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_add_32_nv)
END(_atomic_sub_32_nv)
+
ATOMIC_OP_ALIAS(atomic_add_32_nv,_atomic_add_32_nv)
ATOMIC_OP_ALIAS(atomic_add_int_nv,_atomic_add_32_nv)
ATOMIC_OP_ALIAS(atomic_add_long_nv,_atomic_add_32_nv)
ATOMIC_OP_ALIAS(atomic_add_ptr_nv,_atomic_add_32_nv)
-CRT_ALIAS(__sync_add_and_fetch_4,_atomic_add_32_nv)
STRONG_ALIAS(_atomic_add_int_nv,_atomic_add_32_nv)
STRONG_ALIAS(_atomic_add_long_nv,_atomic_add_32_nv)
STRONG_ALIAS(_atomic_add_ptr_nv,_atomic_add_32_nv)
@@ -103,8 +108,24 @@ ATOMIC_OP_ALIAS(atomic_sub_32_nv,_atomic
ATOMIC_OP_ALIAS(atomic_sub_int_nv,_atomic_sub_32_nv)
ATOMIC_OP_ALIAS(atomic_sub_long_nv,_atomic_sub_32_nv)
ATOMIC_OP_ALIAS(atomic_sub_ptr_nv,_atomic_sub_32_nv)
-CRT_ALIAS(__sync_sub_and_fetch_4,_atomic_sub_32_nv)
STRONG_ALIAS(_atomic_sub_int_nv,_atomic_sub_32_nv)
STRONG_ALIAS(_atomic_sub_long_nv,_atomic_sub_32_nv)
STRONG_ALIAS(_atomic_sub_ptr_nv,_atomic_sub_32_nv)
+
+ENTRY_NP(__sync_add_and_fetch_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_add_32_nv
+ DMB
+ pop {r4, pc}
+END(__sync_add_and_fetch_4)
+
+ENTRY_NP(__sync_sub_and_fetch_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_sub_32_nv
+ DMB
+ pop {r4, pc}
+END(__sync_sub_and_fetch_4)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_and_32.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_and_32.S:1.9 src/common/lib/libc/arch/arm/atomic/atomic_and_32.S:1.10
--- src/common/lib/libc/arch/arm/atomic/atomic_and_32.S:1.9 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_and_32.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_and_32.S,v 1.9 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_and_32.S,v 1.10 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -40,22 +40,25 @@ ENTRY_NP(_atomic_and_32)
strex r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_and_32)
ATOMIC_OP_ALIAS(atomic_and_32,_atomic_and_32)
ATOMIC_OP_ALIAS(atomic_and_uint,_atomic_and_32)
ATOMIC_OP_ALIAS(atomic_and_ulong,_atomic_and_32)
-CRT_ALIAS(__sync_fetch_and_and_4,_atomic_and_32)
CRT_ALIAS(__atomic_fetch_and_4,_atomic_and_32)
STRONG_ALIAS(_atomic_and_uint,_atomic_and_32)
STRONG_ALIAS(_atomic_and_ulong,_atomic_and_32)
+ENTRY_NP(__sync_fetch_and_and_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_and_32
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_and_4)
+
+
ENTRY_NP(_atomic_and_32_nv)
mov ip, r0 /* need r0 for return value */
1: ldrex r0, [ip] /* load old value */
@@ -63,19 +66,21 @@ ENTRY_NP(_atomic_and_32_nv)
strex r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_and_32_nv)
ATOMIC_OP_ALIAS(atomic_and_32_nv,_atomic_and_32_nv)
ATOMIC_OP_ALIAS(atomic_and_uint_nv,_atomic_and_32_nv)
ATOMIC_OP_ALIAS(atomic_and_ulong_nv,_atomic_and_32_nv)
-CRT_ALIAS(__sync_and_and_fetch_4,_atomic_and_32_nv)
STRONG_ALIAS(_atomic_and_uint_nv,_atomic_and_32_nv)
STRONG_ALIAS(_atomic_and_ulong_nv,_atomic_and_32_nv)
+ENTRY_NP(__sync_and_and_fetch_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_and_32_nv
+ DMB
+ pop {r4, pc}
+END(__sync_and_and_fetch_4)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_or_32.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_or_32.S:1.9 src/common/lib/libc/arch/arm/atomic/atomic_or_32.S:1.10
--- src/common/lib/libc/arch/arm/atomic/atomic_or_32.S:1.9 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_or_32.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_or_32.S,v 1.9 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_or_32.S,v 1.10 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,22 +39,25 @@ ENTRY_NP(_atomic_or_32)
strex r2, r3, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return old value */
END(_atomic_or_32)
ATOMIC_OP_ALIAS(atomic_or_32,_atomic_or_32)
ATOMIC_OP_ALIAS(atomic_or_uint,_atomic_or_32)
ATOMIC_OP_ALIAS(atomic_or_ulong,_atomic_or_32)
-CRT_ALIAS(__sync_fetch_and_or_4,_atomic_or_32)
CRT_ALIAS(__atomic_fetch_or_4,_atomic_or_32)
STRONG_ALIAS(_atomic_or_uint,_atomic_or_32)
STRONG_ALIAS(_atomic_or_ulong,_atomic_or_32)
+ENTRY_NP(__sync_fetch_and_or_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_or_32
+ DMB
+ pop {r4, pc}
+END(__sync_fetch_and_or_4)
+
+
ENTRY_NP(_atomic_or_32_nv)
mov ip, r0 /* need r0 for return value */
1: ldrex r0, [ip] /* load old value */
@@ -62,19 +65,22 @@ ENTRY_NP(_atomic_or_32_nv)
strex r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_or_32_nv)
ATOMIC_OP_ALIAS(atomic_or_32_nv,_atomic_or_32_nv)
ATOMIC_OP_ALIAS(atomic_or_uint_nv,_atomic_or_32_nv)
ATOMIC_OP_ALIAS(atomic_or_ulong_nv,_atomic_or_32_nv)
-CRT_ALIAS(__sync_or_and_fetch_4,_atomic_or_32_nv)
STRONG_ALIAS(_atomic_or_uint_nv,_atomic_or_32_nv)
STRONG_ALIAS(_atomic_or_ulong_nv,_atomic_or_32_nv)
+ENTRY_NP(__sync_or_and_fetch_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_or_32_nv
+ DMB
+ pop {r4, pc}
+END(__sync_or_and_fetch_4)
+
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_add_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_add_64.S:1.13 src/common/lib/libc/arch/arm/atomic/atomic_add_64.S:1.14
--- src/common/lib/libc/arch/arm/atomic/atomic_add_64.S:1.13 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_add_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_add_64.S,v 1.13 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_add_64.S,v 1.14 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -45,11 +45,6 @@ ENTRY_NP(_atomic_add_64_nv)
strexd r4, r0, r1, [ip] /* try to store */
cmp r4, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r4, c7, c10, 5 /* data memory barrier */
-#endif
pop {r3, r4} /* restore temporary */
RET /* return new value */
END(_atomic_add_64_nv)
@@ -57,6 +52,13 @@ END(_atomic_add_64_nv)
STRONG_ALIAS(_atomic_add_64,_atomic_add_64_nv)
ATOMIC_OP_ALIAS(atomic_add_64_nv,_atomic_add_64_nv)
ATOMIC_OP_ALIAS(atomic_add_64,_atomic_add_64)
-CRT_ALIAS(__sync_add_and_fetch_8,_atomic_add_64_nv)
+
+ENTRY_NP(__sync_add_and_fetch_8)
+ push {r4, lr}
+ DMB
+ bl _atomic_add_64_nv
+ DMB
+ pop {r4, pc}
+END(__sync_add_and_fetch_8)
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_or_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_or_64.S:1.13 src/common/lib/libc/arch/arm/atomic/atomic_or_64.S:1.14
--- src/common/lib/libc/arch/arm/atomic/atomic_or_64.S:1.13 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_or_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_or_64.S,v 1.13 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_or_64.S,v 1.14 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -45,11 +45,6 @@ ENTRY_NP(_atomic_or_64_nv)
strexd r4, r0, r1, [ip] /* try to store */
cmp r4, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r4, c7, c10, 5 /* data memory barrier */
-#endif
pop {r3, r4} /* restore temporary */
RET /* return new value */
END(_atomic_or_64_nv)
@@ -57,6 +52,13 @@ END(_atomic_or_64_nv)
STRONG_ALIAS(_atomic_or_64,_atomic_or_64_nv)
ATOMIC_OP_ALIAS(atomic_or_64_nv,_atomic_or_64_nv)
ATOMIC_OP_ALIAS(atomic_or_64,_atomic_or_64)
-CRT_ALIAS(__sync_or_and_fetch_8,_atomic_or_64_nv)
+
+ENTRY_NP(__sync_or_and_fetch_8)
+ push {r4, lr}
+ DMB
+ bl _atomic_or_64_nv
+ DMB
+ pop {r4, pc}
+END(__sync_or_and_fetch_8)
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_swap_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_swap_64.S:1.13 src/common/lib/libc/arch/arm/atomic/atomic_swap_64.S:1.14
--- src/common/lib/libc/arch/arm/atomic/atomic_swap_64.S:1.13 Mon Jun 28 09:00:45 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_swap_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_swap_64.S,v 1.13 2021/06/28 09:00:45 skrll Exp $ */
+/* $NetBSD: atomic_swap_64.S,v 1.14 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -30,6 +30,10 @@
#include "atomic_op_asm.h"
+ENTRY_NP(__sync_lock_test_and_set_8)
+ DMB
+ /* FALLTHROUGH */
+
ENTRY_NP(_atomic_swap_64)
push {r3, r4} /* save temporary */
mov ip, r0 /* return value will be in r0 */
@@ -41,27 +45,21 @@ ENTRY_NP(_atomic_swap_64)
strexd r4, r2, r3, [ip] /* store new value */
cmp r4, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r4, c7, c10, 5 /* data memory barrier */
-#endif
pop {r3, r4} /* restore temporary */
RET
END(_atomic_swap_64)
+END(__sync_lock_test_and_set_8)
+
+
ATOMIC_OP_ALIAS(atomic_swap_64,_atomic_swap_64)
-CRT_ALIAS(__sync_lock_test_and_set_8,_atomic_swap_64)
CRT_ALIAS(__atomic_exchange_8,_atomic_swap_64)
#if (!defined(_KERNEL) || !defined(_RUMPKERNEL)) && !defined(_STANDALONE)
ENTRY_NP(__sync_lock_release_8)
mov r2, #0
mov r3, #0
-#ifdef _ARM_ARCH_7
- dmb ishst
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
+
+ DMB
strd r2, r3, [r0]
RET
END(__sync_lock_release_8)
Index: src/common/lib/libc/arch/arm/atomic/atomic_and_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_and_64.S:1.12 src/common/lib/libc/arch/arm/atomic/atomic_and_64.S:1.13
--- src/common/lib/libc/arch/arm/atomic/atomic_and_64.S:1.12 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_and_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_and_64.S,v 1.12 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_and_64.S,v 1.13 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -45,11 +45,6 @@ ENTRY_NP(_atomic_and_64_nv)
strexd r4, r0, r1, [ip] /* try to store */
cmp r4, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r4, c7, c10, 5 /* data memory barrier */
-#endif
pop {r3, r4} /* restore temporary */
RET /* return new value */
END(_atomic_and_64_nv)
@@ -57,6 +52,13 @@ END(_atomic_and_64_nv)
STRONG_ALIAS(_atomic_and_64,_atomic_and_64_nv)
ATOMIC_OP_ALIAS(atomic_and_64_nv,_atomic_and_64_nv)
ATOMIC_OP_ALIAS(atomic_and_64,_atomic_and_64_nv)
-CRT_ALIAS(__sync_and_and_fetch_8,_atomic_and_64_nv)
+
+ENTRY_NP(__sync_and_and_fetch_8)
+ push {r4, lr}
+ DMB
+ bl _atomic_and_64_nv
+ DMB
+ pop {r4, pc}
+END(__sync_and_and_fetch_8)
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_cas_16.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_cas_16.S:1.2 src/common/lib/libc/arch/arm/atomic/atomic_cas_16.S:1.3
--- src/common/lib/libc/arch/arm/atomic/atomic_cas_16.S:1.2 Tue Mar 4 16:15:28 2014
+++ src/common/lib/libc/arch/arm/atomic/atomic_cas_16.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_cas_16.S,v 1.2 2014/03/04 16:15:28 matt Exp $ */
+/* $NetBSD: atomic_cas_16.S,v 1.3 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,6 +31,7 @@
#include "atomic_op_asm.h"
#if defined(_ARM_ARCH_6)
+
/*
* ARMv6 has load-exclusive/store-exclusive which works for both user
* and kernel.
@@ -48,17 +49,19 @@ ENTRY_NP(_atomic_cas_16)
strexh r3, r2, [ip] /* store new value */
cmp r3, #0 /* succeed? */
bne 1b /* nope, try again. */
-#ifdef _ARM_ARCH_7
- dsb /* data synchronization barrier */
-#else
- mcr p15, 0, r3, c7, c10, 4 /* data synchronization barrier */
-#endif
2: RET /* return. */
END(_atomic_cas_16)
ATOMIC_OP_ALIAS(atomic_cas_16,_atomic_cas_16)
STRONG_ALIAS(_atomic_cas_short,_atomic_cas_16)
STRONG_ALIAS(_atomic_cas_ushort,_atomic_cas_16)
-CRT_ALIAS(__sync_val_compare_and_swap_2,_atomic_cas_16)
+
+ENTRY_NP(__sync_val_compare_and_swap_2)
+ push {r4, lr}
+ DMB
+ bl _atomic_cas_16
+ DMB
+ pop {r4, pc}
+END(__sync_val_compare_and_swap_2)
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_cas_32.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_cas_32.S:1.7 src/common/lib/libc/arch/arm/atomic/atomic_cas_32.S:1.8
--- src/common/lib/libc/arch/arm/atomic/atomic_cas_32.S:1.7 Tue Mar 4 16:15:28 2014
+++ src/common/lib/libc/arch/arm/atomic/atomic_cas_32.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_cas_32.S,v 1.7 2014/03/04 16:15:28 matt Exp $ */
+/* $NetBSD: atomic_cas_32.S,v 1.8 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,6 +31,7 @@
#include "atomic_op_asm.h"
#if defined(_ARM_ARCH_6)
+
/*
* ARMv6 has load-exclusive/store-exclusive which works for both user
* and kernel.
@@ -48,11 +49,6 @@ ENTRY_NP(_atomic_cas_32)
strex r3, r2, [ip] /* store new value */
cmp r3, #0 /* succeed? */
bne 1b /* nope, try again. */
-#ifdef _ARM_ARCH_7
- dsb
-#else
- mcr p15, 0, r3, c7, c10, 4 /* data synchronization barrier */
-#endif
2: RET /* return. */
END(_atomic_cas_32)
@@ -64,7 +60,6 @@ ATOMIC_OP_ALIAS(atomic_cas_32_ni,_atomic
ATOMIC_OP_ALIAS(atomic_cas_uint_ni,_atomic_cas_32)
ATOMIC_OP_ALIAS(atomic_cas_ulong_ni,_atomic_cas_32)
ATOMIC_OP_ALIAS(atomic_cas_ptr_ni,_atomic_cas_32)
-CRT_ALIAS(__sync_val_compare_and_swap_4,_atomic_cas_32)
STRONG_ALIAS(_atomic_cas_uint,_atomic_cas_32)
STRONG_ALIAS(_atomic_cas_ulong,_atomic_cas_32)
STRONG_ALIAS(_atomic_cas_32_ni,_atomic_cas_32)
@@ -73,4 +68,12 @@ STRONG_ALIAS(_atomic_cas_uint_ni,_atomic
STRONG_ALIAS(_atomic_cas_ulong_ni,_atomic_cas_32)
STRONG_ALIAS(_atomic_cas_ptr,_atomic_cas_32)
+ENTRY_NP(__sync_val_compare_and_swap_4)
+ push {r4, lr}
+ DMB
+ bl _atomic_cas_32
+ DMB
+ pop {r4, pc}
+END(__sync_val_compare_and_swap_4)
+
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_cas_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_cas_64.S:1.11 src/common/lib/libc/arch/arm/atomic/atomic_cas_64.S:1.12
--- src/common/lib/libc/arch/arm/atomic/atomic_cas_64.S:1.11 Mon Feb 18 11:22:56 2019
+++ src/common/lib/libc/arch/arm/atomic/atomic_cas_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_cas_64.S,v 1.11 2019/02/18 11:22:56 martin Exp $ */
+/* $NetBSD: atomic_cas_64.S,v 1.12 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,6 +31,7 @@
#include "atomic_op_asm.h"
#if defined(_ARM_ARCH_6)
+
/*
* ARMv6 has load-exclusive/store-exclusive which works for both user
* and kernel.
@@ -59,11 +60,6 @@ ENTRY_NP(_atomic_cas_64)
strexd r6, r4, r5, [ip] /* store new value */
cmp r6, #0 /* succeed? */
bne 1b /* nope, try again. */
-#ifdef _ARM_ARCH_7
- dsb
-#else
- mcr p15, 0, ip, c7, c10, 4 /* data synchronization barrier */
-#endif
2:
pop {r4-r7} /* restore temporaries */
RET /* return. */
@@ -72,6 +68,13 @@ END(_atomic_cas_64)
ATOMIC_OP_ALIAS(atomic_cas_64,_atomic_cas_64)
ATOMIC_OP_ALIAS(atomic_cas_64_ni,_atomic_cas_64)
STRONG_ALIAS(_atomic_cas_64_ni,_atomic_cas_64)
-CRT_ALIAS(__sync_val_compare_and_swap_8,_atomic_cas_64)
+
+ENTRY_NP(__sync_val_compare_and_swap_8)
+ push {r4, lr}
+ DMB
+ bl _atomic_cas_64
+ DMB
+ pop {r4, pc}
+END(__sync_val_compare_and_swap_8)
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_cas_8.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_cas_8.S:1.8 src/common/lib/libc/arch/arm/atomic/atomic_cas_8.S:1.9
--- src/common/lib/libc/arch/arm/atomic/atomic_cas_8.S:1.8 Tue Jun 29 06:28:07 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_cas_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_cas_8.S,v 1.8 2021/06/29 06:28:07 skrll Exp $ */
+/* $NetBSD: atomic_cas_8.S,v 1.9 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -32,6 +32,7 @@
#include "atomic_op_asm.h"
#if defined(_ARM_ARCH_6)
+
/*
* ARMv6 has load-exclusive/store-exclusive which works for both user
* and kernel.
@@ -49,17 +50,19 @@ ENTRY_NP(_atomic_cas_8)
strexb r3, r2, [ip] /* store new value */
cmp r3, #0 /* succeed? */
bne 1b /* nope, try again. */
-#ifdef _ARM_ARCH_7
- dsb /* data synchronization barrier */
-#else
- mcr p15, 0, r3, c7, c10, 4 /* data synchronization barrier */
-#endif
2: RET /* return. */
END(_atomic_cas_8)
ATOMIC_OP_ALIAS(atomic_cas_8,_atomic_cas_8)
STRONG_ALIAS(_atomic_cas_char,_atomic_cas_8)
STRONG_ALIAS(_atomic_cas_uchar,_atomic_cas_8)
-CRT_ALIAS(__sync_val_compare_and_swap_1,_atomic_cas_8)
+
+ENTRY_NP(__sync_val_compare_and_swap_1)
+ push {r4, lr}
+ DMB
+ bl _atomic_cas_8
+ DMB
+ pop {r4, pc}
+END(__sync_val_compare_and_swap_1)
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_dec_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_dec_64.S:1.8 src/common/lib/libc/arch/arm/atomic/atomic_dec_64.S:1.9
--- src/common/lib/libc/arch/arm/atomic/atomic_dec_64.S:1.8 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_dec_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_dec_64.S,v 1.8 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_dec_64.S,v 1.9 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -40,11 +40,6 @@ ENTRY_NP(_atomic_dec_64_nv)
strexd r2, r0, r1, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_dec_64_nv)
Index: src/common/lib/libc/arch/arm/atomic/atomic_inc_32.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_inc_32.S:1.8 src/common/lib/libc/arch/arm/atomic/atomic_inc_32.S:1.9
--- src/common/lib/libc/arch/arm/atomic/atomic_inc_32.S:1.8 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_inc_32.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_inc_32.S,v 1.8 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_inc_32.S,v 1.9 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -38,13 +38,9 @@ ENTRY_NP(_atomic_inc_32)
strex r2, r3, [r0] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_inc_32)
+
ATOMIC_OP_ALIAS(atomic_inc_32,_atomic_inc_32)
ATOMIC_OP_ALIAS(atomic_inc_uint,_atomic_inc_32)
ATOMIC_OP_ALIAS(atomic_inc_ulong,_atomic_inc_32)
@@ -53,6 +49,7 @@ STRONG_ALIAS(_atomic_inc_uint,_atomic_in
STRONG_ALIAS(_atomic_inc_ulong,_atomic_inc_32)
STRONG_ALIAS(_atomic_inc_ptr,_atomic_inc_32)
+
ENTRY_NP(_atomic_inc_32_nv)
mov ip, r0 /* need r0 for return value */
1: ldrex r0, [ip] /* load old value */
@@ -60,11 +57,6 @@ ENTRY_NP(_atomic_inc_32_nv)
strex r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_inc_32_nv)
ATOMIC_OP_ALIAS(atomic_inc_32_nv,_atomic_inc_32_nv)
Index: src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h
diff -u src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.8 src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.9
--- src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.8 Mon Sep 16 12:40:40 2019
+++ src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_op_asm.h,v 1.8 2019/09/16 12:40:40 skrll Exp $ */
+/* $NetBSD: atomic_op_asm.h,v 1.9 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -74,4 +74,12 @@
#define CRT_ALIAS(a,s)
#endif
+#ifdef _ARM_ARCH_7
+#define DMB dmb ish
+#define DMBST dmb ishst
+#else
+#define DMB mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier */
+#define DMBST DMB
+#endif
+
#endif /* _ATOMIC_OP_ASM_H_ */
Index: src/common/lib/libc/arch/arm/atomic/membar_ops.S
diff -u src/common/lib/libc/arch/arm/atomic/membar_ops.S:1.8 src/common/lib/libc/arch/arm/atomic/membar_ops.S:1.9
--- src/common/lib/libc/arch/arm/atomic/membar_ops.S:1.8 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/membar_ops.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: membar_ops.S,v 1.8 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: membar_ops.S,v 1.9 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -33,12 +33,7 @@
#if defined(_ARM_ARCH_6)
ENTRY_NP(_membar_producer)
-#ifdef _ARM_ARCH_7
- dmb ishst
-#else
- mov r0, #0
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier */
-#endif
+ DMBST
RET
END(_membar_producer)
ATOMIC_OP_ALIAS(membar_producer,_membar_producer)
@@ -46,12 +41,7 @@ ATOMIC_OP_ALIAS(membar_write,_membar_pro
STRONG_ALIAS(_membar_write,_membar_producer)
ENTRY_NP(_membar_sync)
-#ifdef _ARM_ARCH_7
- dmb ish
-#else
- mov r0, #0
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier */
-#endif
+ DMB
RET
END(_membar_sync)
ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
@@ -59,7 +49,7 @@ ATOMIC_OP_ALIAS(membar_enter,_membar_syn
ATOMIC_OP_ALIAS(membar_exit,_membar_sync)
ATOMIC_OP_ALIAS(membar_consumer,_membar_sync)
ATOMIC_OP_ALIAS(membar_read,_membar_sync)
-CRT_ALIAS(__sync_synchronize,_membar_sync)
+STRONG_ALIAS(__sync_synchronize,_membar_sync)
STRONG_ALIAS(_membar_enter,_membar_sync)
STRONG_ALIAS(_membar_exit,_membar_sync)
STRONG_ALIAS(_membar_consumer,_membar_sync)
Index: src/common/lib/libc/arch/arm/atomic/atomic_dec_32.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_dec_32.S:1.6 src/common/lib/libc/arch/arm/atomic/atomic_dec_32.S:1.7
--- src/common/lib/libc/arch/arm/atomic/atomic_dec_32.S:1.6 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_dec_32.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_dec_32.S,v 1.6 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_dec_32.S,v 1.7 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -38,11 +38,6 @@ ENTRY_NP(_atomic_dec_32)
strex r2, r3, [r0] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_dec_32)
@@ -54,6 +49,7 @@ STRONG_ALIAS(_atomic_dec_uint,_atomic_de
STRONG_ALIAS(_atomic_dec_ulong,_atomic_dec_32)
STRONG_ALIAS(_atomic_dec_ptr,_atomic_dec_32)
+
ENTRY_NP(_atomic_dec_32_nv)
mov ip, r0 /* need r0 for return value */
1: ldrex r0, [ip] /* load old value */
@@ -61,11 +57,6 @@ ENTRY_NP(_atomic_dec_32_nv)
strex r2, r0, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_dec_32_nv)
Index: src/common/lib/libc/arch/arm/atomic/atomic_nand_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_nand_64.S:1.6 src/common/lib/libc/arch/arm/atomic/atomic_nand_64.S:1.7
--- src/common/lib/libc/arch/arm/atomic/atomic_nand_64.S:1.6 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_nand_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_nand_64.S,v 1.6 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_nand_64.S,v 1.7 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -47,11 +47,6 @@ ENTRY_NP(_atomic_nand_64_nv)
strexd r4, r0, r1, [ip] /* try to store */
cmp r4, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r4, c7, c10, 5 /* data memory barrier */
-#endif
pop {r3, r4} /* restore temporary */
RET /* return new value */
END(_atomic_nand_64_nv)
@@ -59,6 +54,13 @@ END(_atomic_nand_64_nv)
STRONG_ALIAS(_atomic_nand_64,_atomic_nand_64_nv)
ATOMIC_OP_ALIAS(atomic_nand_64_nv,_atomic_nand_64_nv)
ATOMIC_OP_ALIAS(atomic_nand_64,_atomic_nand_64_nv)
-CRT_ALIAS(__sync_nand_and_fetch_8,_atomic_nand_64_nv)
+
+ENTRY_NP(__sync_nand_and_fetch_8)
+ push {r4, lr}
+ DMB
+ bl _atomic_nand_64_nv
+ DMB
+ pop {r4, pc}
+END(__sync_nand_and_fetch_8)
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_swap_16.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_swap_16.S:1.6 src/common/lib/libc/arch/arm/atomic/atomic_swap_16.S:1.7
--- src/common/lib/libc/arch/arm/atomic/atomic_swap_16.S:1.6 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_swap_16.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_swap_16.S,v 1.6 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_swap_16.S,v 1.7 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -33,6 +33,10 @@
#if defined(_ARM_ARCH_6)
+ENTRY_NP(__sync_lock_test_and_set_2)
+ DMB
+ /* FALLTHROUGH */
+
ENTRY_NP(_atomic_swap_16)
mov ip, r0
1:
@@ -40,30 +44,22 @@ ENTRY_NP(_atomic_swap_16)
strexh r3, r1, [ip]
cmp r3, #0
bne 1b
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, ip, c7, c10, 5 /* data memory barrier */
-#endif
RET
END(_atomic_swap_16)
+END(__sync_lock_test_and_set_2)
ATOMIC_OP_ALIAS(atomic_swap_16,_atomic_swap_16)
ATOMIC_OP_ALIAS(atomic_swap_short,_atomic_swap_16)
ATOMIC_OP_ALIAS(atomic_swap_ushort,_atomic_swap_16)
-CRT_ALIAS(__sync_lock_test_and_set_2,_atomic_swap_16)
CRT_ALIAS(__atomic_exchange_2,_atomic_swap_16)
STRONG_ALIAS(_atomic_swap_short,_atomic_swap_16)
STRONG_ALIAS(_atomic_swap_ushort,_atomic_swap_16)
+
#if (!defined(_KERNEL) || !defined(_RUMPKERNEL)) && !defined(_STANDALONE)
ENTRY_NP(__sync_lock_release_2)
mov r1, #0
-#ifdef _ARM_ARCH_7
- dmb ishst
-#else
- mcr p15, 0, r1, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
strh r1, [r0]
RET
END(__sync_lock_release_2)
Index: src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S:1.6 src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S:1.7
--- src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S:1.6 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_xor_64.S,v 1.6 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_xor_64.S,v 1.7 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -45,11 +45,6 @@ ENTRY_NP(_atomic_xor_64_nv)
strexd r4, r0, r1, [ip] /* try to store */
cmp r4, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r4, c7, c10, 5 /* data memory barrier */
-#endif
pop {r3, r4} /* restore temporary */
RET /* return new value */
END(_atomic_xor_64_nv)
Index: src/common/lib/libc/arch/arm/atomic/atomic_inc_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_inc_64.S:1.10 src/common/lib/libc/arch/arm/atomic/atomic_inc_64.S:1.11
--- src/common/lib/libc/arch/arm/atomic/atomic_inc_64.S:1.10 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_inc_64.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_inc_64.S,v 1.10 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_inc_64.S,v 1.11 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -40,11 +40,6 @@ ENTRY_NP(_atomic_inc_64_nv)
strexd r2, r0, r1, [ip] /* try to store */
cmp r2, #0 /* succeed? */
bne 1b /* no, try again? */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
RET /* return new value */
END(_atomic_inc_64_nv)
Index: src/common/lib/libc/arch/arm/atomic/atomic_swap.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_swap.S:1.18 src/common/lib/libc/arch/arm/atomic/atomic_swap.S:1.19
--- src/common/lib/libc/arch/arm/atomic/atomic_swap.S:1.18 Sat Jul 10 06:53:40 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_swap.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_swap.S,v 1.18 2021/07/10 06:53:40 skrll Exp $ */
+/* $NetBSD: atomic_swap.S,v 1.19 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2007,2012 The NetBSD Foundation, Inc.
@@ -44,6 +44,10 @@
* and fix yet again).
*/
+ENTRY_NP(__sync_lock_test_and_set_4)
+ DMB
+ /* FALLTHROUGH */
+
ENTRY_NP(_atomic_swap_32)
mov ip, r0
1:
@@ -65,20 +69,15 @@ ENTRY_NP(_atomic_swap_32)
cmpne r3, #0
#endif
bne 1b
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r3, c7, c10, 5 /* data memory barrier */
-#endif
99:
RET
END(_atomic_swap_32)
+END(__sync_lock_test_and_set_4)
ATOMIC_OP_ALIAS(atomic_swap_32,_atomic_swap_32)
ATOMIC_OP_ALIAS(atomic_swap_uint,_atomic_swap_32)
ATOMIC_OP_ALIAS(atomic_swap_ulong,_atomic_swap_32)
ATOMIC_OP_ALIAS(atomic_swap_ptr,_atomic_swap_32)
-CRT_ALIAS(__sync_lock_test_and_set_4,_atomic_swap_32)
CRT_ALIAS(__atomic_exchange_4,_atomic_swap_32)
STRONG_ALIAS(_atomic_swap_uint,_atomic_swap_32)
STRONG_ALIAS(_atomic_swap_ulong,_atomic_swap_32)
@@ -87,16 +86,17 @@ STRONG_ALIAS(_atomic_swap_ptr,_atomic_sw
#if (!defined(_KERNEL) || !defined(_RUMPKERNEL)) && !defined(_STANDALONE)
ENTRY_NP(__sync_lock_release_4)
mov r1, #0
-#ifdef _ARM_ARCH_7
- dmb ishst
-#else
- mcr p15, 0, r1, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
+
str r1, [r0]
RET
END(__sync_lock_release_4)
#endif
+ENTRY_NP(__sync_lock_test_and_set_1)
+ DMB
+ /* FALLTHROUGH */
+
ENTRY_NP(_atomic_swap_8)
mov ip, r0
1:
@@ -109,18 +109,13 @@ ENTRY_NP(_atomic_swap_8)
#endif
cmp r3, #0
bne 1b
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, ip, c7, c10, 5 /* data memory barrier */
-#endif
RET
END(_atomic_swap_8)
+END(__sync_lock_test_and_set_1)
ATOMIC_OP_ALIAS(atomic_swap_8,_atomic_swap_8)
ATOMIC_OP_ALIAS(atomic_swap_char,_atomic_swap_8)
ATOMIC_OP_ALIAS(atomic_swap_uchar,_atomic_swap_8)
-CRT_ALIAS(__sync_lock_test_and_set_1,_atomic_swap_8)
CRT_ALIAS(__atomic_exchange_1,_atomic_swap_8)
STRONG_ALIAS(_atomic_swap_char,_atomic_swap_8)
STRONG_ALIAS(_atomic_swap_uchar,_atomic_swap_8)
@@ -128,11 +123,8 @@ STRONG_ALIAS(_atomic_swap_uchar,_atomic_
#if (!defined(_KERNEL) || !defined(_RUMPKERNEL)) && !defined(_STANDALONE)
ENTRY_NP(__sync_lock_release_1)
mov r1, #0
-#ifdef _ARM_ARCH_7
- dmb ishst
-#else
- mcr p15, 0, r1, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
+
strb r1, [r0]
RET
END(__sync_lock_release_1)
Index: src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S:1.3 src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S:1.4
--- src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S:1.3 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_bool_compare_and_swap_1.S,v 1.3 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_bool_compare_and_swap_1.S,v 1.4 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -32,6 +32,7 @@
#include "atomic_op_asm.h"
#if defined(_ARM_ARCH_6)
+
/*
* ARMv6 has load-exclusive/store-exclusive which works for both user
* and kernel.
@@ -51,11 +52,6 @@ ENTRY_NP(__sync_bool_compare_and_swap_1)
cmp r0, #0 /* succeed? */
bne 1b /* nope, try again. */
mov r0, #1 /* it was a success */
-#ifdef _ARM_ARCH_7
- dsb /* data synchronization barrier */
-#else
- mcr p15, 0, r3, c7, c10, 4 /* data synchronization barrier */
-#endif
2: RET /* return. */
END(__sync_bool_compare_and_swap_1)
Index: src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S:1.3 src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S:1.4
--- src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S:1.3 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_bool_compare_and_swap_2.S,v 1.3 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_bool_compare_and_swap_2.S,v 1.4 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,6 +31,7 @@
#include "atomic_op_asm.h"
#if defined(_ARM_ARCH_6)
+
/*
* ARMv6 has load-exclusive/store-exclusive which works for both user
* and kernel.
@@ -50,11 +51,6 @@ ENTRY_NP(__sync_bool_compare_and_swap_2)
cmp r0, #0 /* succeed? */
bne 1b /* nope, try again. */
movs r0, #1 /* indicate success */
-#ifdef _ARM_ARCH_7
- dsb /* data synchronization barrier */
-#else
- mcr p15, 0, r3, c7, c10, 4 /* data synchronization barrier */
-#endif
2: RET /* return. */
END(__sync_bool_compare_and_swap_2)
Index: src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S:1.3 src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S:1.4
--- src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S:1.3 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_bool_compare_and_swap_4.S,v 1.3 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_bool_compare_and_swap_4.S,v 1.4 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -31,6 +31,7 @@
#include "atomic_op_asm.h"
#if defined(_ARM_ARCH_6)
+
/*
* ARMv6 has load-exclusive/store-exclusive which works for both user
* and kernel.
@@ -50,11 +51,6 @@ ENTRY_NP(__sync_bool_compare_and_swap_4)
cmp r0, #0 /* succeed? */
bne 1b /* nope, try again. */
movs r0, #1 /* indicate success */
-#ifdef _ARM_ARCH_7
- dsb
-#else
- mcr p15, 0, r3, c7, c10, 4 /* data synchronization barrier */
-#endif
2: RET /* return. */
END(__sync_bool_compare_and_swap_4)
Index: src/common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S:1.5 src/common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S:1.6
--- src/common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S:1.5 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_fetch_and_add_8.S,v 1.5 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_fetch_and_add_8.S,v 1.6 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,17 +40,14 @@ ENTRY_NP(__sync_fetch_and_add_8)
mov r3, r2
mov r2, r1
#endif
+ DMB
1: ldrexd r0, r1, [ip] /* load old value */
adds TLO, LO, NLO /* calculate new value */
adcs THI, HI, NHI /* calculate new value */
strexd r6, r4, r5, [ip] /* try to store */
cmp r6, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
pop {r4-r7}
RET /* return old value */
END(__sync_fetch_and_add_8)
Index: src/common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S:1.5 src/common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S:1.6
--- src/common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S:1.5 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_fetch_and_and_8.S,v 1.5 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_fetch_and_and_8.S,v 1.6 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,17 +40,14 @@ ENTRY_NP(__sync_fetch_and_and_8)
mov r3, r2
mov r2, r1
#endif
+ DMB
1: ldrexd r0, r1, [ip] /* load old value */
ands r4, r0, r2 /* calculate new value */
ands r5, r1, r3 /* calculate new value */
strexd r6, r4, r5, [ip] /* try to store */
cmp r6, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
pop {r4-r7}
RET /* return old value */
END(__sync_fetch_and_and_8)
Index: src/common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S:1.5 src/common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S:1.6
--- src/common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S:1.5 Fri Dec 11 12:41:10 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_fetch_and_nand_8.S,v 1.5 2015/12/11 12:41:10 skrll Exp $ */
+/* $NetBSD: sync_fetch_and_nand_8.S,v 1.6 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,6 +40,7 @@ ENTRY_NP(__sync_fetch_and_nand_8)
mov r3, r2
mov r2, r1
#endif
+ DMB
1: ldrexd r0, r1, [ip] /* load old value */
ands r4, r0, r2 /* calculate new value step 1 */
ands r5, r1, r3 /* calculate new value step 1 */
@@ -48,11 +49,7 @@ ENTRY_NP(__sync_fetch_and_nand_8)
strexd r6, r4, r5, [ip] /* try to store */
cmp r6, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
pop {r4-r7}
RET /* return old value */
END(__sync_fetch_and_nand_8)
Index: src/common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S:1.5 src/common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S:1.6
--- src/common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S:1.5 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_fetch_and_or_8.S,v 1.5 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_fetch_and_or_8.S,v 1.6 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,17 +40,14 @@ ENTRY_NP(__sync_fetch_and_or_8)
mov r3, r2
mov r2, r1
#endif
+ DMB
1: ldrexd r0, r1, [ip] /* load old value */
orrs r4, r0, r2 /* calculate new value */
orrs r5, r1, r3 /* calculate new value */
strexd r6, r4, r5, [ip] /* try to store */
cmp r6, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
pop {r4-r7}
RET /* return old value */
END(__sync_fetch_and_or_8)
Index: src/common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S:1.5 src/common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S:1.6
--- src/common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S:1.5 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_fetch_and_sub_8.S,v 1.5 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_fetch_and_sub_8.S,v 1.6 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,17 +40,14 @@ ENTRY_NP(__sync_fetch_and_sub_8)
mov r3, r2
mov r2, r1
#endif
+ DMB
1: ldrexd r0, r1, [ip] /* load old value */
subs TLO, LO, NLO /* calculate new value */
sbcs THI, HI, NHI /* calculate new value */
strexd r6, r4, r5, [ip] /* try to store */
cmp r6, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
pop {r4-r7}
RET /* return old value */
END(__sync_fetch_and_sub_8)
Index: src/common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S
diff -u src/common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S:1.5 src/common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S:1.6
--- src/common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S:1.5 Sun May 17 22:08:24 2015
+++ src/common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S Wed Jul 28 07:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sync_fetch_and_xor_8.S,v 1.5 2015/05/17 22:08:24 justin Exp $ */
+/* $NetBSD: sync_fetch_and_xor_8.S,v 1.6 2021/07/28 07:32:20 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -40,17 +40,14 @@ ENTRY_NP(__sync_fetch_and_xor_8)
mov r3, r2
mov r2, r1
#endif
+ DMB
1: ldrexd r0, r1, [ip] /* load old value */
eors r4, r0, r2 /* calculate new value */
eors r5, r1, r3 /* calculate new value */
strexd r6, r4, r5, [ip] /* try to store */
cmp r6, #0 /* succeed? */
bne 1b /* no, try again */
-#ifdef _ARM_ARCH_7
- dmb
-#else
- mcr p15, 0, r2, c7, c10, 5 /* data memory barrier */
-#endif
+ DMB
pop {r4-r7}
RET /* return old value */
END(__sync_fetch_and_xor_8)
