Module Name:    src
Committed By:   simonb
Date:           Wed Jul 28 08:01:10 UTC 2021

Modified Files:
        src/common/lib/libc/arch/arm/atomic: atomic_op_asm.h

Log Message:
#define<tab> consistency.


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h
diff -u src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.9 src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.10
--- src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.9	Wed Jul 28 07:32:20 2021
+++ src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h	Wed Jul 28 08:01:10 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: atomic_op_asm.h,v 1.9 2021/07/28 07:32:20 skrll Exp $	*/
+/*	$NetBSD: atomic_op_asm.h,v 1.10 2021/07/28 08:01:10 simonb Exp $	*/
 
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -75,11 +75,11 @@
 #endif
 
 #ifdef _ARM_ARCH_7
-#define DMB	dmb	ish
+#define	DMB	dmb	ish
 #define	DMBST	dmb	ishst
 #else
-#define DMB	mcr	p15, 0, r0, c7, c10, 5	/* Data Memory Barrier */
-#define DMBST	DMB
+#define	DMB	mcr	p15, 0, r0, c7, c10, 5	/* Data Memory Barrier */
+#define	DMBST	DMB
 #endif
 
 #endif /* _ATOMIC_OP_ASM_H_ */

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