Module Name: src
Committed By: cliff
Date: Mon Mar 22 07:45:19 UTC 2010
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_subr.S
Log Message:
- in rmixlfw_wakeup_cpu, properly nuke the upper half of sp
before OR-ing in KSEG0_START. This is only needed in _LP64 case.
- in rmixl_cpu_trampoline:
trampoline args addr needs reconstructing the upper half only in _LP64 case.
delete set of MIPS_SR_INT_IE bit.
use REG_L instead of PTR_L to load trampoline args
so we get 64 bit loads in both 32 and 64 bit kernels.
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/mips/rmi/rmixl_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixl_subr.S
diff -u src/sys/arch/mips/rmi/rmixl_subr.S:1.1.2.5 src/sys/arch/mips/rmi/rmixl_subr.S:1.1.2.6
--- src/sys/arch/mips/rmi/rmixl_subr.S:1.1.2.5 Sun Mar 21 21:29:45 2010
+++ src/sys/arch/mips/rmi/rmixl_subr.S Mon Mar 22 07:45:19 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_subr.S,v 1.1.2.5 2010/03/21 21:29:45 cliff Exp $ */
+/* $NetBSD: rmixl_subr.S,v 1.1.2.6 2010/03/22 07:45:19 cliff Exp $ */
#include "opt_cputype.h"
#include "opt_multiprocessor.h"
@@ -55,10 +55,14 @@
REG_S t0, CALLFRAME_SIZ+2*SZREG(sp)
move s0, sp /* save sp */
- srl t0, sp, 0 /* nuke upper half */
+#ifdef _LP64
+ dsll32 t0, sp, 0 /* nuke upper half */
+ dsrl32 t0, t0, 0 /* " " " */
li t1, MIPS_KSEG0_START
+ or sp, t0, t1 /* set MIPS_KSEG0_START */
+#endif
jalr a3 /* callback to firmware */
- or sp, t0, t1 /* set MIPS_KSEG0_START */
+ nop
move sp, s0 /* restore sp */
REG_L t0, CALLFRAME_SIZ+2*SZREG(sp)
@@ -77,13 +81,14 @@
NESTED(rmixl_cpu_trampoline, CALLFRAME_SIZ, ra)
#ifdef _LP64
li t0, MIPS_SR_KX
+ li t1, MIPS_KSEG0_START /* reconstruct presumed upper half ... */
+ or a0, a0, t1 /* ... of trampoline args addr */
#else
li t0, 0
#endif
mtc0 zero, $9, 7 /* disable all in MIPS_COP_0_EIMR */
- or t0, MIPS_SR_INT_IE
mtc0 t0, MIPS_COP_0_STATUS
/* ensure COP_0_EBASE field 'EBASE' is 0 */
@@ -91,26 +96,22 @@
and t0, t0, 0x3ff
mtc0 t0, $15, 1 /* MIPS_COP_0_EBASE */
- /* XXX reconstruct presumed upper half of trampoline args addr */
- li t1, MIPS_KSEG0_START
- or a0, a0, t1
-
/*
* load our stack pointer from trampoline args
*/
- PTR_L sp, 0*SZREG(a0) /* XXX ta_sp */
+ REG_L sp, 0*SZREG(a0) /* XXX ta_sp */
/*
* load our (idle) lwp from trampoline args
* save in t8 reg dedicated as 'mips_curlwp'
*/
- PTR_L t8, 1*SZREG(a0) /* XXX ta_lwp */
+ REG_L t8, 1*SZREG(a0) /* XXX ta_lwp */
/*
* load our ta_cpuinfo from trampoline args and pass in a1
* jump to common mips cpu_trampoline
*/
- PTR_L a1, 2*SZREG(a0) /* XXX ta_cpuinfo */
+ REG_L a1, 2*SZREG(a0) /* XXX ta_cpuinfo */
j cpu_trampoline
mtc0 a1, $22, 0 /* MIPS_COP_0_OSSCRATCH */
