Module Name: src
Committed By: cliff
Date: Wed Mar 24 19:14:09 UTC 2010
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixlreg.h
Log Message:
shift enable bits into correct field in RMIXL_PIC_CONTROL_TIMER_ENBn() macro
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.9 -r1.1.2.10 src/sys/arch/mips/rmi/rmixlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixlreg.h
diff -u src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.9 src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.10
--- src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.9 Sun Mar 21 21:30:35 2010
+++ src/sys/arch/mips/rmi/rmixlreg.h Wed Mar 24 19:14:09 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlreg.h,v 1.1.2.9 2010/03/21 21:30:35 cliff Exp $ */
+/* $NetBSD: rmixlreg.h,v 1.1.2.10 2010/03/24 19:14:09 cliff Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -453,7 +453,7 @@
#define RMIXL_PIC_CONTROL_GEN_NMIn(n) (((n) << 1) & RMIXL_PIC_CONTROL_GEN_NMI)
#define RMIXL_PIC_CONTROL_RESa __BITS(7,3)
#define RMIXL_PIC_CONTROL_TIMER_ENB __BITS(15,8) /* per-Timer enable bits */
-#define RMIXL_PIC_CONTROL_TIMER_ENBn(n) ((1 << (n)) & RMIXL_PIC_CONTROL_TIMER_ENB)
+#define RMIXL_PIC_CONTROL_TIMER_ENBn(n) ((1 << (8 + (n))) & RMIXL_PIC_CONTROL_TIMER_ENB)
#define RMIXL_PIC_CONTROL_RESb __BITS(31,16)
#define RMIXL_PIC_CONTROL_RESV \
(RMIXL_PIC_CONTROL_RESa|RMIXL_PIC_CONTROL_RESb)
