Module Name:    src
Committed By:   cliff
Date:           Mon Mar 29 23:33:37 UTC 2010

Modified Files:
        src/sys/arch/mips/mips [matt-nb5-mips64]: mips_machdep.c

Log Message:
- add a cputab[] entry for RMI XLR732 (other XLR models are TBD)


To generate a diff of this commit:
cvs rdiff -u -r1.205.4.1.2.1.2.41 -r1.205.4.1.2.1.2.42 \
    src/sys/arch/mips/mips/mips_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.41 src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.42
--- src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.41	Sun Mar 21 17:38:32 2010
+++ src/sys/arch/mips/mips/mips_machdep.c	Mon Mar 29 23:33:37 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.41 2010/03/21 17:38:32 cliff Exp $	*/
+/*	$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.42 2010/03/29 23:33:37 cliff Exp $	*/
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.41 2010/03/21 17:38:32 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.42 2010/03/29 23:33:37 cliff Exp $");
 
 #define	__INTR_PRIVATE
 
@@ -441,6 +441,14 @@
 	  CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT), 0, 0,
 						"SB-1"			},
 
+	{ MIPS_PRID_CID_RMI, MIPS_XLR732B, MIPS_XLR_B2,	-1, -1, 0,
+	  MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
+	  CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
+	  MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+	  MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+	  CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB),
+	  "XLR732B"		},
+
 	{ MIPS_PRID_CID_RMI, MIPS_XLS616, -1,	-1, -1, 0,
 	  MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
 	  CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,

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