Module Name: src
Committed By: cliff
Date: Tue Apr 27 05:45:22 UTC 2010
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: mips_machdep.c
Log Message:
add cputab[] entry for RMI CPU MIPS_XLR732C
To generate a diff of this commit:
cvs rdiff -u -r1.205.4.1.2.1.2.43 -r1.205.4.1.2.1.2.44 \
src/sys/arch/mips/mips/mips_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.43 src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.44
--- src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.43 Mon Apr 12 22:01:41 2010
+++ src/sys/arch/mips/mips/mips_machdep.c Tue Apr 27 05:45:22 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.43 2010/04/12 22:01:41 cliff Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.44 2010/04/27 05:45:22 cliff Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.43 2010/04/12 22:01:41 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.44 2010/04/27 05:45:22 cliff Exp $");
#define __INTR_PRIVATE
@@ -441,7 +441,7 @@
CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT), 0, 0,
"SB-1" },
- { MIPS_PRID_CID_RMI, MIPS_XLR732B, MIPS_XLR_B2, -1, -1, 0,
+ { MIPS_PRID_CID_RMI, MIPS_XLR732B, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
@@ -449,6 +449,14 @@
CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB),
"XLR732B" },
+ { MIPS_PRID_CID_RMI, MIPS_XLR732C, -1, -1, -1, 0,
+ MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
+ CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
+ MIPS_CP0FL_USE |MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE |
+ MIPS_CP0FL_CONFIGn(0) | MIPS_CP0FL_CONFIGn(1) | MIPS_CP0FL_CONFIGn(7),
+ CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB),
+ "XLR732C" },
+
{ MIPS_PRID_CID_RMI, MIPS_XLS616, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR |
CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR,
