Module Name: src
Committed By: cliff
Date: Mon Apr 12 22:40:55 UTC 2010
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c rmixl_intr.h
Log Message:
- establishing an ISR now takes 'mpsafe' arg
- obtain/release kernel lock around calls to non-mpsafe ISRs
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.16 -r1.1.2.17 src/sys/arch/mips/rmi/rmixl_intr.c
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/rmi/rmixl_intr.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixl_intr.c
diff -u src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.16 src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.17
--- src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.16 Mon Mar 29 23:35:24 2010
+++ src/sys/arch/mips/rmi/rmixl_intr.c Mon Apr 12 22:40:55 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_intr.c,v 1.1.2.16 2010/03/29 23:35:24 cliff Exp $ */
+/* $NetBSD: rmixl_intr.c,v 1.1.2.17 2010/04/12 22:40:55 cliff Exp $ */
/*-
* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
@@ -64,7 +64,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.16 2010/03/29 23:35:24 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.17 2010/04/12 22:40:55 cliff Exp $");
#include "opt_ddb.h"
#define __INTR_PRIVATE
@@ -422,12 +422,13 @@
* establish vector for mips3 count/compare clock interrupt
* this ensures we enable in EIRR,
* even though cpu_intr() handles the interrupt
+ * note the 'mpsafe' arg here is a placeholder only
*/
void *
rmixl_intr_init_clk(void)
{
int vec = ffs(MIPS_INT_MASK_5 >> 8) - 1;
- void *ih = rmixl_vec_establish(vec, 0, IPL_SCHED, NULL, NULL);
+ void *ih = rmixl_vec_establish(vec, 0, IPL_SCHED, NULL, NULL, false);
if (ih == NULL)
panic("%s: establish vec %d failed", __func__, vec);
@@ -442,7 +443,7 @@
rmixl_intr_init_ipi(void)
{
void *ih = rmixl_vec_establish(RMIXL_INTRVEC_IPI, -1, IPL_SCHED,
- rmixl_ipi_intr, NULL);
+ rmixl_ipi_intr, NULL, false);
if (ih == NULL)
panic("%s: establish vec %d failed",
__func__, RMIXL_INTRVEC_IPI);
@@ -671,7 +672,7 @@
void *
rmixl_vec_establish(int vec, int cpumask, int ipl,
- int (*func)(void *), void *arg)
+ int (*func)(void *), void *arg, bool mpsafe)
{
rmixl_intrhand_t *ih;
int s;
@@ -700,6 +701,7 @@
ih->ih_func = func;
ih->ih_arg = arg;
+ ih->ih_mpsafe = mpsafe;
ih->ih_irq = vec;
ih->ih_ipl = ipl;
ih->ih_cpumask = cpumask;
@@ -710,8 +712,9 @@
}
void *
-rmixl_intr_establish(int irq, int cpumask, int ipl, rmixl_intr_trigger_t trigger,
- rmixl_intr_polarity_t polarity, int (*func)(void *), void *arg)
+rmixl_intr_establish(int irq, int cpumask, int ipl,
+ rmixl_intr_trigger_t trigger, rmixl_intr_polarity_t polarity,
+ int (*func)(void *), void *arg, bool mpsafe)
{
rmixl_intrhand_t *ih;
int s;
@@ -738,7 +741,7 @@
/*
* establish vector
*/
- ih = rmixl_vec_establish(irq, cpumask, ipl, func, arg);
+ ih = rmixl_vec_establish(irq, cpumask, ipl, func, arg, mpsafe);
/*
* establish IRT Entry
@@ -843,8 +846,19 @@
RMIXL_PICREG_WRITE(RMIXL_PIC_INTRACK,
(uint32_t)vecbit);
- if (ih->ih_func != NULL)
+ if (ih->ih_func != NULL) {
+#ifdef MULTIPROCESSOR
+ if (ih->ih_mpsafe) {
+ (void)(*ih->ih_func)(ih->ih_arg);
+ } else {
+ KERNEL_LOCK(1, NULL);
+ (void)(*ih->ih_func)(ih->ih_arg);
+ KERNEL_UNLOCK_ONE(NULL);
+ }
+#else
(void)(*ih->ih_func)(ih->ih_arg);
+#endif /* MULTIPROCESSOR */
+ }
sc->sc_vec_evcnts[vec].ev_count++;
}
Index: src/sys/arch/mips/rmi/rmixl_intr.h
diff -u src/sys/arch/mips/rmi/rmixl_intr.h:1.1.2.1 src/sys/arch/mips/rmi/rmixl_intr.h:1.1.2.2
--- src/sys/arch/mips/rmi/rmixl_intr.h:1.1.2.1 Sun Mar 21 19:28:01 2010
+++ src/sys/arch/mips/rmi/rmixl_intr.h Mon Apr 12 22:40:55 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_intr.h,v 1.1.2.1 2010/03/21 19:28:01 cliff Exp $ */
+/* $NetBSD: rmixl_intr.h,v 1.1.2.2 2010/04/12 22:40:55 cliff Exp $ */
#ifndef _MIPS_RMI_RMIXL_INTR_H_
#define _MIPS_RMI_RMIXL_INTR_H_
@@ -40,6 +40,7 @@
typedef struct rmixl_intrhand {
int (*ih_func)(void *);
void *ih_arg;
+ int ih_mpsafe; /* true if does not need kernel lock */
int ih_irq; /* >=32 if not-PIC-based */
int ih_ipl; /* interrupt priority */
int ih_cpumask; /* CPUs which may handle this irpt */
@@ -53,10 +54,10 @@
extern void *rmixl_intr_establish(int, int, int,
rmixl_intr_trigger_t, rmixl_intr_polarity_t,
- int (*)(void *), void *);
+ int (*)(void *), void *, bool);
extern void rmixl_intr_disestablish(void *);
extern void *rmixl_vec_establish(int, int, int,
- int (*)(void *), void *);
+ int (*)(void *), void *, bool);
extern void rmixl_vec_disestablish(void *);
extern const char *rmixl_intr_string(int);
extern void rmixl_intr_init_cpu(struct cpu_info *);
