CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips

[Matt Thomas]

Module Name:    src
Committed By:   matt
Date:           Tue Jun  1 19:10:45 UTC 2010

Modified Files:
        src/sys/arch/mips/mips [matt-nb5-mips64]: mips_emul.c

Log Message:
>From Manuel Bouyer:

In the matt-nb5-mips64 branch, in mips_emul.c:MachEmulateBranch(), the
BRANCHTARGET macro was changed to take the value instead of a pointer to
instruction. But the effect of this change is that now, the instruction's word
value is used to compute the new PC, instead of the instruction's address. Of
course this can't give good results, and in my case this gave an unaligned PC.


To generate a diff of this commit:
cvs rdiff -u -r1.14.78.10 -r1.14.78.11 src/sys/arch/mips/mips/mips_emul.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/mips/mips/mips_emul.c
diff -u src/sys/arch/mips/mips/mips_emul.c:1.14.78.10 src/sys/arch/mips/mips/mips_emul.c:1.14.78.11
--- src/sys/arch/mips/mips/mips_emul.c:1.14.78.10	Sat May 15 20:27:48 2010
+++ src/sys/arch/mips/mips/mips_emul.c	Tue Jun  1 19:10:45 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: mips_emul.c,v 1.14.78.10 2010/05/15 20:27:48 matt Exp $ */
+/*	$NetBSD: mips_emul.c,v 1.14.78.11 2010/06/01 19:10:45 matt Exp $ */
 
 /*
  * Copyright (c) 1999 Shuichiro URATA.  All rights reserved.
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.14.78.10 2010/05/15 20:27:48 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_emul.c,v 1.14.78.11 2010/06/01 19:10:45 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -102,7 +102,7 @@
 MachEmulateBranch(struct trapframe *tf, vaddr_t instpc, unsigned fpuCSR,
     int allowNonBranch)
 {
-#define	BRANCHTARGET(i) (4 + ((i).word) + ((short)(i).IType.imm << 2))
+#define	BRANCHTARGET(pc, i) (4 + (pc) + ((short)(i).IType.imm << 2))
 	InstFmt inst;
 	vaddr_t nextpc;
 
@@ -129,7 +129,7 @@
 		case OP_BLTZL:		/* squashed */
 		case OP_BLTZALL:	/* squashed */
 			if ((int)(tf->tf_regs[inst.RType.rs]) < 0)
-				nextpc = BRANCHTARGET(inst);
+				nextpc = BRANCHTARGET(instpc, inst);
 			else
 				nextpc = instpc + 8;
 			break;
@@ -139,7 +139,7 @@
 		case OP_BGEZL:		/* squashed */
 		case OP_BGEZALL:	/* squashed */
 			if ((int)(tf->tf_regs[inst.RType.rs]) >= 0)
-				nextpc = BRANCHTARGET(inst);
+				nextpc = BRANCHTARGET(instpc, inst);
 			else
 				nextpc = instpc + 8;
 			break;
@@ -159,7 +159,7 @@
 	case OP_BEQ:
 	case OP_BEQL:	/* squashed */
 		if (tf->tf_regs[inst.RType.rs] == tf->tf_regs[inst.RType.rt])
-			nextpc = BRANCHTARGET(inst);
+			nextpc = BRANCHTARGET(instpc, inst);
 		else
 			nextpc = instpc + 8;
 		break;
@@ -167,7 +167,7 @@
 	case OP_BNE:
 	case OP_BNEL:	/* squashed */
 		if (tf->tf_regs[inst.RType.rs] != tf->tf_regs[inst.RType.rt])
-			nextpc = BRANCHTARGET(inst);
+			nextpc = BRANCHTARGET(instpc, inst);
 		else
 			nextpc = instpc + 8;
 		break;
@@ -175,7 +175,7 @@
 	case OP_BLEZ:
 	case OP_BLEZL:	/* squashed */
 		if ((int)(tf->tf_regs[inst.RType.rs]) <= 0)
-			nextpc = BRANCHTARGET(inst);
+			nextpc = BRANCHTARGET(instpc, inst);
 		else
 			nextpc = instpc + 8;
 		break;
@@ -183,7 +183,7 @@
 	case OP_BGTZ:
 	case OP_BGTZL:	/* squashed */
 		if ((int)(tf->tf_regs[inst.RType.rs]) > 0)
-			nextpc = BRANCHTARGET(inst);
+			nextpc = BRANCHTARGET(instpc, inst);
 		else
 			nextpc = instpc + 8;
 		break;
@@ -194,7 +194,7 @@
 			if ((inst.RType.rt & COPz_BC_TF_MASK) != COPz_BC_TRUE)
 				condition = !condition;
 			if (condition)
-				nextpc = BRANCHTARGET(inst);
+				nextpc = BRANCHTARGET(instpc, inst);
 			else
 				nextpc = instpc + 8;
 		}
@@ -211,6 +211,7 @@
 			    __func__, "non-branch", inst.word, instpc);
 		nextpc = instpc + 4;
 	}
+	KASSERT((nextpc & 0x3) == 0);
 	return nextpc;
 #undef	BRANCHTARGET
 }