Module Name: src
Committed By: kiyohara
Date: Wed Jun 9 04:41:43 UTC 2010
Modified Files:
src/sys/arch/ofppc/conf: GENERIC files.ofppc
src/sys/arch/ofppc/include: pegasosreg.h
src/sys/arch/ofppc/ofppc: mainbus.c
src/sys/arch/powerpc/oea: ofw_autoconf.c
Added Files:
src/sys/arch/ofppc/pci: gt_mainbus.c
Removed Files:
src/sys/arch/ofppc/pci: pegasospci.c
Log Message:
Support MV64361 on PegasosII by gt(4).
+ Support gt...@gt instead of pegasospci more smartly.
+ Support Gigabit Ethernet by mv...@gt.
To generate a diff of this commit:
cvs rdiff -u -r1.129 -r1.130 src/sys/arch/ofppc/conf/GENERIC
cvs rdiff -u -r1.41 -r1.42 src/sys/arch/ofppc/conf/files.ofppc
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/ofppc/include/pegasosreg.h
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/ofppc/ofppc/mainbus.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/ofppc/pci/gt_mainbus.c
cvs rdiff -u -r1.14 -r0 src/sys/arch/ofppc/pci/pegasospci.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/powerpc/oea/ofw_autoconf.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/ofppc/conf/GENERIC
diff -u src/sys/arch/ofppc/conf/GENERIC:1.129 src/sys/arch/ofppc/conf/GENERIC:1.130
--- src/sys/arch/ofppc/conf/GENERIC:1.129 Sat May 8 22:16:29 2010
+++ src/sys/arch/ofppc/conf/GENERIC Wed Jun 9 04:41:42 2010
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.129 2010/05/08 22:16:29 mrg Exp $
+# $NetBSD: GENERIC,v 1.130 2010/06/09 04:41:42 kiyohara Exp $
#
# GENERIC machine description file
#
@@ -22,7 +22,7 @@
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.129 $"
+#ident "GENERIC-$Revision: 1.130 $"
maxusers 32
@@ -180,11 +180,15 @@
# Generic OpenFirmware console support
rtas* at mainbus?
+gt* at mainbus? # Marvell MV64361 Discovery II
+mvgbec* at gt? offset ? # Gigabit Ethernet
+mvgbe0 at mvgbec? port 1 irq 9
+
# PCI root nodes
ofwpci* at mainbus?
pci* at ofwpci? bus ?
-pegasospci* at mainbus?
-pci* at pegasospci? bus ?
+gtpci* at gt? unit ?
+pci* at gtpci? bus ?
# PCI bridges
pchb* at pci? dev ? function ?
Index: src/sys/arch/ofppc/conf/files.ofppc
diff -u src/sys/arch/ofppc/conf/files.ofppc:1.41 src/sys/arch/ofppc/conf/files.ofppc:1.42
--- src/sys/arch/ofppc/conf/files.ofppc:1.41 Sun Mar 14 10:14:14 2010
+++ src/sys/arch/ofppc/conf/files.ofppc Wed Jun 9 04:41:42 2010
@@ -1,4 +1,4 @@
-# $NetBSD: files.ofppc,v 1.41 2010/03/14 10:14:14 kiyohara Exp $
+# $NetBSD: files.ofppc,v 1.42 2010/06/09 04:41:42 kiyohara Exp $
#
# NetBSD/ofppc configuration info
#
@@ -89,9 +89,11 @@
attach ofwpci at mainbus
file arch/ofppc/pci/ofwpci.c ofwpci
-device pegasospci: pcibus
-attach pegasospci at mainbus
-file arch/ofppc/pci/pegasospci.c pegasospci
+# Marvell System-Controller MV64361(Discovery II) (on PegasosII)
+include "dev/marvell/files.discovery"
+attach gt at mainbus
+file arch/ofppc/pci/gt_mainbus.c gt
+file arch/powerpc/marvell/pci_machdep.c gtpci
device pchb: pcibus
attach pchb at pci
Index: src/sys/arch/ofppc/include/pegasosreg.h
diff -u src/sys/arch/ofppc/include/pegasosreg.h:1.1 src/sys/arch/ofppc/include/pegasosreg.h:1.2
--- src/sys/arch/ofppc/include/pegasosreg.h:1.1 Sun Nov 4 17:07:10 2007
+++ src/sys/arch/ofppc/include/pegasosreg.h Wed Jun 9 04:41:42 2010
@@ -1,20 +1,10 @@
-/* $NetBSD: pegasosreg.h,v 1.1 2007/11/04 17:07:10 garbled Exp $ */
+/* $NetBSD: pegasosreg.h,v 1.2 2010/06/09 04:41:42 kiyohara Exp $ */
#ifndef _MACHINE_PEGASOSREG_H_
#define _MACHINE_PEGASOSREG_H_
-#define PEGASOS2_MARVELL_REGBASE 0xf1000000
-#define PEGASOS2_MARVELL_REGSIZE 0x4000
+#define PEGASOS2_GT_REGBASE 0xf1000000
#define PEGASOS2_SRAM_BASE 0xf2000000
#define PEGASOS2_SRAM_SIZE 0x40000
-#define PEGASOS2_PCI0_ADDR (PEGASOS2_MARVELL_REGBASE | 0xc78)
-#define PEGASOS2_PCI0_DATA (PEGASOS2_MARVELL_REGBASE | 0xc7c)
-
-#define PEGASOS2_PCI1_ADDR (PEGASOS2_MARVELL_REGBASE | 0xcf8)
-#define PEGASOS2_PCI1_DATA (PEGASOS2_MARVELL_REGBASE | 0xcfc)
-#define PEGASOS2_AGP_MAGIC (PEGASOS2_MARVELL_REGBASE | 0xf118)
-
-#define PEGASOS2_AGP_MAGIC_COOKIE 0x00800000
-
#endif /*_MACHINE_PEGASOSREG_H_*/
Index: src/sys/arch/ofppc/ofppc/mainbus.c
diff -u src/sys/arch/ofppc/ofppc/mainbus.c:1.25 src/sys/arch/ofppc/ofppc/mainbus.c:1.26
--- src/sys/arch/ofppc/ofppc/mainbus.c:1.25 Wed Mar 10 18:06:57 2010
+++ src/sys/arch/ofppc/ofppc/mainbus.c Wed Jun 9 04:41:42 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.c,v 1.25 2010/03/10 18:06:57 kiyohara Exp $ */
+/* $NetBSD: mainbus.c,v 1.26 2010/06/09 04:41:42 kiyohara Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.25 2010/03/10 18:06:57 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.26 2010/06/09 04:41:42 kiyohara Exp $");
#include "opt_interrupt.h"
#include "opt_multiprocessor.h"
@@ -260,6 +260,18 @@
config_found(self, &oba, NULL);
}
+ if (strcmp(model_name, "Pegasos2") == 0) {
+ /*
+ * Configure to System Controller MV64361.
+ * And skip other devices. These attached from it.
+ */
+ ca.ca_name = "gt";
+
+ config_found(self, &ca, NULL);
+
+ goto config_fin;
+ }
+
/* this primarily searches for pci bridges on the root bus */
for (node = OF_child(OF_finddevice("/")); node; node = OF_peer(node)) {
memset(name, 0, sizeof(name));
@@ -273,9 +285,11 @@
ca.ca_node = node;
ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg));
ca.ca_reg = reg;
- config_found(self, &ca, NULL);
+ config_found(self, &ca, NULL);
}
+
+config_fin:
pic_finish_setup();
}
Index: src/sys/arch/powerpc/oea/ofw_autoconf.c
diff -u src/sys/arch/powerpc/oea/ofw_autoconf.c:1.11 src/sys/arch/powerpc/oea/ofw_autoconf.c:1.12
--- src/sys/arch/powerpc/oea/ofw_autoconf.c:1.11 Wed Jan 20 16:36:55 2010
+++ src/sys/arch/powerpc/oea/ofw_autoconf.c Wed Jun 9 04:41:43 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: ofw_autoconf.c,v 1.11 2010/01/20 16:36:55 macallan Exp $ */
+/* $NetBSD: ofw_autoconf.c,v 1.12 2010/06/09 04:41:43 kiyohara Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
* Copyright (C) 1995, 1996 TooLs GmbH.
@@ -31,7 +31,11 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ofw_autoconf.c,v 1.11 2010/01/20 16:36:55 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ofw_autoconf.c,v 1.12 2010/06/09 04:41:43 kiyohara Exp $");
+
+#ifdef ofppc
+#include "gtpci.h"
+#endif
#include <sys/param.h>
#include <sys/conf.h>
@@ -46,14 +50,22 @@
#include <machine/stdarg.h>
#include <dev/ofw/openfirm.h>
+#include <dev/marvell/marvellvar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
+#if NGTPCI > 0
+#include <dev/marvell/gtpcivar.h>
+#endif
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
#include <dev/ata/atavar.h>
#include <dev/ic/wdcvar.h>
+#include <machine/pci_machdep.h>
+
+#include <prop/proplib.h>
+
extern char bootpath[256];
char cbootpath[256];
int console_node = 0, console_instance = 0;
@@ -199,12 +211,82 @@
static char *bp = bootpath + 1, *cp = cbootpath;
unsigned long addr, addr2;
char *p;
+#if NGTPCI > 0
+ struct powerpc_bus_space *gtpci_mem_bs_tag = NULL;
+#endif
/* Skip over devices not represented in the OF tree. */
if (device_is_a(dev, "mainbus")) {
parent = dev;
return;
}
+#if NGTPCI > 0
+ if (device_is_a(dev, "gtpci")) {
+ extern struct gtpci_prot gtpci0_prot, gtpci1_prot;
+ extern struct powerpc_bus_space
+ gtpci0_io_bs_tag, gtpci0_mem_bs_tag,
+ gtpci1_io_bs_tag, gtpci1_mem_bs_tag;
+ extern struct genppc_pci_chipset
+ genppc_gtpci0_chipset, genppc_gtpci1_chipset;
+
+ struct marvell_attach_args *mva = aux;
+ struct gtpci_prot *gtpci_prot;
+ struct powerpc_bus_space *gtpci_io_bs_tag;
+ struct genppc_pci_chipset *genppc_gtpci_chipset;
+ prop_dictionary_t dict = device_properties(dev);
+ prop_data_t prot, io_bs_tag, mem_bs_tag, pc;
+ int iostart, ioend;
+
+ if (mva->mva_unit == 0) {
+ gtpci_prot = >pci0_prot;
+ gtpci_io_bs_tag = >pci0_io_bs_tag;
+ gtpci_mem_bs_tag = >pci0_mem_bs_tag;
+ genppc_gtpci_chipset = &genppc_gtpci0_chipset;
+ iostart = 0;
+ ioend = 0;
+ } else {
+ gtpci_prot = >pci1_prot;
+ gtpci_io_bs_tag = >pci1_io_bs_tag;
+ gtpci_mem_bs_tag = >pci1_mem_bs_tag;
+ genppc_gtpci_chipset = &genppc_gtpci1_chipset;
+ iostart = 0x1400;
+ ioend = 0xffff;
+ }
+
+ prot = prop_data_create_data_nocopy(
+ gtpci_prot, sizeof(struct gtpci_prot));
+ KASSERT(prot != NULL);
+ prop_dictionary_set(dict, "prot", prot);
+ prop_object_release(prot);
+
+ io_bs_tag = prop_data_create_data_nocopy(
+ gtpci_io_bs_tag, sizeof(struct powerpc_bus_space));
+ KASSERT(io_bs_tag != NULL);
+ prop_dictionary_set(dict, "io-bus-tag", io_bs_tag);
+ prop_object_release(io_bs_tag);
+ mem_bs_tag = prop_data_create_data_nocopy(
+ gtpci_mem_bs_tag, sizeof(struct powerpc_bus_space));
+ KASSERT(mem_bs_tag != NULL);
+ prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag);
+ prop_object_release(mem_bs_tag);
+
+ genppc_gtpci_chipset->pc_conf_v = device_private(dev);
+ pc = prop_data_create_data_nocopy(genppc_gtpci_chipset,
+ sizeof(struct genppc_pci_chipset));
+ KASSERT(pc != NULL);
+ prop_dictionary_set(dict, "pci-chipset", pc);
+ prop_object_release(pc);
+
+ prop_dictionary_set_uint64(dict, "iostart", iostart);
+ prop_dictionary_set_uint64(dict, "ioend", ioend);
+ prop_dictionary_set_uint64(dict, "memstart",
+ gtpci_mem_bs_tag->pbs_base);
+ prop_dictionary_set_uint64(dict, "memend",
+ gtpci_mem_bs_tag->pbs_limit - 1);
+ prop_dictionary_set_uint32(dict, "cache-line-size",
+ CACHELINESIZE);
+ }
+#endif
if (device_is_a(dev, "atapibus") || device_is_a(dev, "pci") ||
device_is_a(dev, "scsibus") || device_is_a(dev, "atabus"))
return;
@@ -305,8 +387,33 @@
if (strcmp(ca->ca_name, "ofw") == 0) /* XXX */
return;
+ if (strcmp(ca->ca_name, "gt") == 0)
+ parent = dev;
if (addr != ca->ca_reg[0])
return;
+ } else if (device_is_a(device_parent(dev), "gt")) {
+ /*
+ * Special handle for MV64361 on PegasosII(ofppc).
+ */
+ if (device_is_a(dev, "mvgbec")) {
+ /*
+ * Fix cp to /p...@n from /ethernet/portN. (N is 0...2)
+ */
+ static char fix_cp[8] = "/p...@n";
+
+ if (strlen(cp) != 15 ||
+ strncmp(cp, "/ethernet/port", 14) != 0)
+ return;
+ fix_cp[7] = *(cp + 15);
+ p = fix_cp;
+#if NGTPCI > 0
+ } else if (device_is_a(dev, "gtpci")) {
+ if (gtpci_mem_bs_tag != NULL &&
+ addr != gtpci_mem_bs_tag->pbs_base)
+ return;
+#endif
+ } else
+ return;
} else if (device_is_a(device_parent(dev), "pci")) {
struct pci_attach_args *pa = aux;
Added files:
Index: src/sys/arch/ofppc/pci/gt_mainbus.c
diff -u /dev/null src/sys/arch/ofppc/pci/gt_mainbus.c:1.1
--- /dev/null Wed Jun 9 04:41:43 2010
+++ src/sys/arch/ofppc/pci/gt_mainbus.c Wed Jun 9 04:41:42 2010
@@ -0,0 +1,316 @@
+/* $NetBSD: gt_mainbus.c,v 1.1 2010/06/09 04:41:42 kiyohara Exp $ */
+/*
+ * Copyright (c) 2010 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: gt_mainbus.c,v 1.1 2010/06/09 04:41:42 kiyohara Exp $");
+
+#include "opt_pci.h"
+#include "opt_marvell.h"
+#include "gtpci.h"
+#include "pci.h"
+#include "isa.h"
+
+#define _POWERPC_BUS_DMA_PRIVATE
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+#include <sys/extent.h>
+#include <sys/malloc.h>
+
+#include <machine/autoconf.h>
+#include <machine/bus.h>
+#include <machine/isa_machdep.h>
+#include <machine/pegasosreg.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pciconf.h>
+
+#include <dev/marvell/gtreg.h>
+#include <dev/marvell/gtvar.h>
+#include <dev/marvell/gtpcireg.h>
+#include <dev/marvell/gtpcivar.h>
+#include <dev/marvell/marvellvar.h>
+#include <dev/ofw/openfirm.h>
+
+
+static int gt_match(device_t, cfdata_t, void *);
+static void gt_attach(device_t, device_t, void *);
+
+#if NGTPCI > 0
+static void gtpci_md_attach_hook(device_t, device_t,
+ struct pcibus_attach_args *);
+void gtpci_md_conf_interrupt(void *, int, int, int, int, int *);
+int gtpci_md_conf_hook(void *, int, int, int, pcireg_t);
+#endif
+
+CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL);
+
+static struct powerpc_bus_space pegasosii_gt_bs_tag = {
+ .pbs_offset = PEGASOS2_GT_REGBASE,
+ .pbs_base = 0x00000000,
+ .pbs_limit = GT_SIZE,
+};
+static char ex_storage[EXTENT_FIXED_STORAGE_SIZE(8)]
+ __attribute__((aligned(8)));
+
+struct powerpc_bus_dma_tag pegasosii_bus_dma_tag = {
+ 0, /* _bounce_thresh */
+ _bus_dmamap_create,
+ _bus_dmamap_destroy,
+ _bus_dmamap_load,
+ _bus_dmamap_load_mbuf,
+ _bus_dmamap_load_uio,
+ _bus_dmamap_load_raw,
+ _bus_dmamap_unload,
+ _bus_dmamap_sync,
+ _bus_dmamem_alloc,
+ _bus_dmamem_free,
+ _bus_dmamem_map,
+ _bus_dmamem_unmap,
+ _bus_dmamem_mmap,
+};
+
+#if NGTPCI > 0
+struct powerpc_bus_space
+ gtpci0_io_bs_tag, gtpci0_mem_bs_tag,
+ gtpci1_io_bs_tag, gtpci1_mem_bs_tag;
+#endif
+
+struct gtpci_prot gtpci0_prot = {
+ GTPCI_ACBL_RDSIZE_32BYTE |
+ GTPCI_ACBL_RDMBURST_32BYTE |
+ GTPCI_ACBL_PCISWAP_BYTESWAP |
+ GTPCI_ACBL_SNOOP_WB |
+ GTPCI_ACBL_EN,
+ 0,
+}, gtpci1_prot = {
+ GTPCI_ACBL_RDSIZE_128BYTE |
+ GTPCI_ACBL_RDMBURST_32BYTE |
+ GTPCI_ACBL_PCISWAP_BYTESWAP |
+ GTPCI_ACBL_SNOOP_WB |
+ GTPCI_ACBL_EN,
+ 0,
+};
+
+
+int
+gt_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct confargs *ca = aux;
+ int node, pci, ethernet;
+ char name[32];
+
+ if (strcmp(ca->ca_name, "gt") != 0 ||
+ strcmp(model_name, "Pegasos2") != 0)
+ return 0;
+
+ /* Paranoid check... */
+
+ pci = ethernet = 0;
+ for (node = OF_child(OF_finddevice("/")); node; node = OF_peer(node)) {
+ memset(name, 0, sizeof(name));
+ if (OF_getprop(node, "name", name, sizeof(name)) == -1)
+ continue;
+ if (strcmp(name, "pci") == 0)
+ pci++;
+ else if (strcmp(name, "ethernet") == 0)
+ ethernet++;
+
+ }
+ if (pci == 2 && ethernet == 1)
+ return 1;
+ return 0;
+}
+
+/* ARGSUSED */
+void
+gt_attach(device_t parent, device_t self, void *aux)
+{
+ struct gt_softc *sc = device_private(self);
+#if NGTPCI > 0
+ uint32_t busrange[2];
+ int node;
+ extern struct genppc_pci_chipset
+ genppc_gtpci0_chipset, genppc_gtpci1_chipset;
+#endif
+
+ bus_space_init(&pegasosii_gt_bs_tag, "gt",
+ ex_storage, sizeof(ex_storage));
+
+ sc->sc_dev = self;
+ sc->sc_addr = 0x00000000;
+ sc->sc_iot = &pegasosii_gt_bs_tag;
+ sc->sc_dmat = &pegasosii_bus_dma_tag;
+
+ if (bus_space_map(sc->sc_iot, sc->sc_addr, GT_SIZE, 0, &sc->sc_ioh) !=
+ 0) {
+ aprint_error(": registers map failed\n");
+ return;
+ }
+
+ init_ofppc_interrupt();
+
+#if NGTPCI > 0
+ /* bus space map the I/O and Memory ranges of PCI unit 1(PCI bus) */
+ node = of_find_firstchild_byname(OF_finddevice("/"), "pci");
+ if (node != -1) {
+ gtpci1_io_bs_tag.pbs_flags =
+ _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_IO_TYPE;
+ gtpci1_io_bs_tag.pbs_base = 0x00000000;
+ if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node,
+ >pci1_io_bs_tag, "gtpci 1 io-space") != 0)
+ panic("Can't init gtpci 1 io tag");
+ gtpci1_mem_bs_tag.pbs_flags =
+ _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE;
+ gtpci1_mem_bs_tag.pbs_base = 0x00000000;
+ if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node,
+ >pci1_mem_bs_tag, "gtpci 1 mem-space") != 0)
+ panic("Can't init gtpci 1 mem tag");
+
+ /* PCI bus number */
+ if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) !=
+ sizeof(busrange)) {
+ aprint_error(": PCI bus range failed\n");
+ return;
+ }
+
+ /* Override some functions */
+ genppc_gtpci1_chipset.pc_attach_hook = gtpci_md_attach_hook;
+ genppc_gtpci1_chipset.pc_intr_map = genofw_pci_intr_map;
+ genppc_gtpci1_chipset.pc_node = node;
+ genppc_gtpci1_chipset.pc_bus = busrange[0];
+ genppc_gtpci1_chipset.pc_iot = >pci1_io_bs_tag;
+ genppc_gtpci1_chipset.pc_memt = >pci1_mem_bs_tag;
+
+#if NISA > 0
+ genppc_isa_io_space_tag = gtpci1_io_bs_tag;
+ genppc_isa_mem_space_tag = gtpci1_mem_bs_tag;
+ map_isa_ioregs();
+ ofppc_init_comcons(of_find_firstchild_byname(node, "isa"));
+#endif
+ }
+
+ /* bus space map the I/O and Memory ranges of PCI unit 0(AGP bus) */
+ if (node != -1)
+ node = of_getnode_byname(OF_peer(node), "pci");
+ if (node != -1 && node != 0) {
+ gtpci0_io_bs_tag.pbs_flags =
+ _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_IO_TYPE;
+ gtpci0_io_bs_tag.pbs_base = 0x00000000;
+ if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node,
+ >pci0_io_bs_tag, "gtpci 0 io-space") != 0)
+ panic("Can't init gtpci 0 io tag");
+ gtpci0_mem_bs_tag.pbs_flags =
+ _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE;
+ gtpci0_mem_bs_tag.pbs_base = 0x00000000;
+ if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node,
+ >pci0_mem_bs_tag, "gtpci 0 mem-space") != 0)
+ panic("Can't init gtpci 0 mem tag");
+
+ /* PCI bus number */
+ if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) !=
+ sizeof(busrange)) {
+ aprint_error(": AGP bus range failed\n");
+ return;
+ }
+
+ genppc_gtpci0_chipset.pc_node = node;
+ genppc_gtpci0_chipset.pc_bus = busrange[0];
+ genppc_gtpci0_chipset.pc_iot = >pci0_io_bs_tag;
+ genppc_gtpci0_chipset.pc_memt = >pci0_mem_bs_tag;
+
+ /* Enable access to space of configuration for AGP. */
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Set,
+ (1 << 23));
+ }
+#endif
+
+ gt_attach_common(sc);
+
+#if NGTPCI > 0
+ /* Disable access to space of configuration for AGP. */
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Clear,
+ (1 << 23));
+#endif
+}
+
+
+#if NGTPCI > 0
+static void
+gtpci_md_attach_hook(device_t parent, device_t self,
+ struct pcibus_attach_args *pba)
+{
+ extern struct genppc_pci_chipset genppc_gtpci1_chipset;
+
+ if (device_is_a(parent, "gtpci") &&
+ pba->pba_pc == &genppc_gtpci1_chipset) {
+ /* Setup interrupts for PCI bus */
+ struct genppc_pci_chipset_businfo *pbi;
+
+ pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
+ M_DEVBUF, M_NOWAIT);
+ KASSERT(pbi != NULL);
+ pbi->pbi_properties = prop_dictionary_create();
+ KASSERT(pbi->pbi_properties != NULL);
+ SIMPLEQ_INIT(&genppc_gtpci1_chipset.pc_pbi);
+ SIMPLEQ_INSERT_TAIL(&genppc_gtpci1_chipset.pc_pbi, pbi, next);
+
+ genofw_setup_pciintr_map(&genppc_gtpci1_chipset, pbi,
+ genppc_gtpci1_chipset.pc_node);
+ }
+ gtpci_attach_hook(parent, self, pba);
+}
+
+/* ARGSUSED */
+void
+gtpci_md_conf_interrupt(void * v, int bus, int dev, int pin, int swiz,
+ int *iline)
+{
+
+ /* do nothing */
+}
+
+int
+gtpci_md_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
+{
+ struct gtpci_softc *sc = v;
+
+ if (gtpci_conf_hook(sc->sc_pc, bus, dev, func, id) == 0)
+ return 0;
+ return genofw_pci_conf_hook(sc->sc_pc, bus, dev, func, id);
+}
+#endif
+
+
+void *
+marvell_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
+{
+
+ /* pass through */
+ return intr_establish(irq, IST_LEVEL, ipl, func, arg);
+}
