Module Name: src
Committed By: matt
Date: Sat Dec 31 04:30:53 UTC 2011
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_gpio_pci.c rmixlreg.h
Log Message:
Deal with the movement of some GPIO registers on the XPL3xx.
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/mips/rmi/rmixl_gpio_pci.c
cvs rdiff -u -r1.1.2.16 -r1.1.2.17 src/sys/arch/mips/rmi/rmixlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixl_gpio_pci.c
diff -u src/sys/arch/mips/rmi/rmixl_gpio_pci.c:1.1.2.2 src/sys/arch/mips/rmi/rmixl_gpio_pci.c:1.1.2.3
--- src/sys/arch/mips/rmi/rmixl_gpio_pci.c:1.1.2.2 Sat Dec 31 03:33:13 2011
+++ src/sys/arch/mips/rmi/rmixl_gpio_pci.c Sat Dec 31 04:30:52 2011
@@ -29,7 +29,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rmixl_gpio_pci.c,v 1.1.2.2 2011/12/31 03:33:13 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rmixl_gpio_pci.c,v 1.1.2.3 2011/12/31 04:30:52 matt Exp $");
#include <sys/param.h>
#include <sys/atomic.h>
@@ -151,9 +151,9 @@ static struct xlgpio_softc xlgpio_sc = {
[2] = RMIXLP_GPIO_INTEN(2, 0),
[3] = RMIXLP_GPIO_INTEN(3, 0),
},
- .gg_r_intpol = RMIXLP_GPIO_INTPOL(0),
- .gg_r_inttype = RMIXLP_GPIO_INTTYPE(0),
- .gg_r_intstat = RMIXLP_GPIO_INTSTAT(0),
+ .gg_r_intpol = RMIXLP_GPIO_8XX_INTPOL(0),
+ .gg_r_inttype = RMIXLP_GPIO_8XX_INTTYPE(0),
+ .gg_r_intstat = RMIXLP_GPIO_8XX_INTSTAT(0),
},
[1] = {
.gg_pins = xlgpio_sc.sc_pins + PINGROUP,
@@ -166,9 +166,9 @@ static struct xlgpio_softc xlgpio_sc = {
[2] = RMIXLP_GPIO_INTEN(2, 1),
[3] = RMIXLP_GPIO_INTEN(3, 1),
},
- .gg_r_intpol = RMIXLP_GPIO_INTPOL(1),
- .gg_r_inttype = RMIXLP_GPIO_INTTYPE(1),
- .gg_r_intstat = RMIXLP_GPIO_INTSTAT(1),
+ .gg_r_intpol = RMIXLP_GPIO_8XX_INTPOL(1),
+ .gg_r_inttype = RMIXLP_GPIO_8XX_INTTYPE(1),
+ .gg_r_intstat = RMIXLP_GPIO_8XX_INTSTAT(1),
},
},
.sc_gpio_chipset = {
@@ -266,10 +266,18 @@ xlgpio_pci_attach(device_t parent, devic
KASSERT(gg->gg_inttype == 0);
/*
+ * These are at different offsets on the 3xx than the 8xx/4xx.
+ */
+ if (rmixl_xlp_variant >= RMIXLP_3XX) {
+ gg->gg_r_intpol = RMIXLP_GPIO_3XX_INTPOL(group);
+ gg->gg_r_inttype = RMIXLP_GPIO_3XX_INTTYPE(group);
+ gg->gg_r_intstat = RMIXLP_GPIO_3XX_INTSTAT(group);
+ }
+
+ /*
* Disable all interrupts for group.
* Get shadow copy of registers.
*/
-
gg->gg_padoe = xlgpio_read_4(sc, gg->gg_r_padoe);
gg->gg_paddrv = xlgpio_read_4(sc, gg->gg_r_paddrv);
xlgpio_write_4(sc, gg->gg_r_intpol, gg->gg_intpol);
@@ -283,6 +291,7 @@ xlgpio_pci_attach(device_t parent, devic
/*
* GPIO has 4 interrupts which map 1:1 on IPL_VM to IPL_HIGH
+ * (12 on 3xx but we only use 4).
*/
const pcireg_t irtinfo = xlgpio_read_4(sc, PCI_RMIXLP_IRTINFO);
@@ -291,8 +300,9 @@ xlgpio_pci_attach(device_t parent, devic
KASSERT(irtcount >= IPL_HIGH - IPL_VM + 1);
- for (size_t irt = 0; irt < irtcount; irt++) {
- if (rmixl_intr_establish(irtstart + irt, IPL_VM + irt,
+ for (size_t ipl = IPL_VM; ipl <= IPL_HIGH ; ipl++) {
+ const size_t irt = ipl - IPL_VM;
+ if (rmixl_intr_establish(irtstart + irt, ipl,
RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH,
xlgpio_intrs[irt], sc, true) == NULL)
panic("%s: failed to establish interrupt %zu",
@@ -469,7 +479,7 @@ gpio_intr_disestablish(void *v)
*inten_p &= ~mask;
xlgpio_write_4(sc, gg->gg_r_inten[gip->gip_ipl - IPL_VM], *inten_p);
- xlgpio_write_4(sc, RMIXLP_GPIO_INTSTAT(group), mask); /* ACK it */
+ xlgpio_write_4(sc, gg->gg_r_intstat, mask); /* ACK it */
gip->gip_ipl = IPL_NONE;
gip->gip_ist = IST_NONE;
Index: src/sys/arch/mips/rmi/rmixlreg.h
diff -u src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.16 src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.17
--- src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.16 Fri Dec 30 06:48:56 2011
+++ src/sys/arch/mips/rmi/rmixlreg.h Sat Dec 31 04:30:52 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlreg.h,v 1.1.2.16 2011/12/30 06:48:56 matt Exp $ */
+/* $NetBSD: rmixlreg.h,v 1.1.2.17 2011/12/31 04:30:52 matt Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -912,23 +912,12 @@
#define RMIXLP_GPIO_INTEN(n,g) _RMIXL_OFFSET(0x46+2*(n)+(g)) // Interrupt 0 Enable Register 0
#define RMIXLP_GPIO_INTEN0(n) _RMIXL_OFFSET(0x46+2*(n)) // Interrupt 0 Enable Register 0
#define RMIXLP_GPIO_INTEN1(n) _RMIXL_OFFSET(0x47+2*(n)) // Interrupt 0 Enable Register 0
-#define RMIXLP_GPIO_INTEN00 _RMIXL_OFFSET(0x46) // Interrupt 0 Enable Register 0
-#define RMIXLP_GPIO_INTEN01 _RMIXL_OFFSET(0x47) // Interrupt 0 Enable Register 1
-#define RMIXLP_GPIO_INTEN10 _RMIXL_OFFSET(0x48) // Interrupt 1 Enable Register 0
-#define RMIXLP_GPIO_INTEN11 _RMIXL_OFFSET(0x49) // Interrupt 1 Enable Register 1
-#define RMIXLP_GPIO_INTEN20 _RMIXL_OFFSET(0x4A) // Interrupt 2 Enable Register 0
-#define RMIXLP_GPIO_INTEN21 _RMIXL_OFFSET(0x4B) // Interrupt 2 Enable Register 1
-#define RMIXLP_GPIO_INTEN30 _RMIXL_OFFSET(0x4C) // Interrupt 3 Enable Register 0
-#define RMIXLP_GPIO_INTEN31 _RMIXL_OFFSET(0x4D) // Interrupt 3 Enable Register 1
-#define RMIXLP_GPIO_INTPOL(g) _RMIXL_OFFSET((0x4E)+(g)) // Interrupt Polarity Register 0
-#define RMIXLP_GPIO_INTPOL0 _RMIXL_OFFSET(0x4E) // Interrupt Polarity Register 0
-#define RMIXLP_GPIO_INTPOL1 _RMIXL_OFFSET(0x4F) // Interrupt Polarity Register 1
-#define RMIXLP_GPIO_INTTYPE(g) _RMIXL_OFFSET(0x50+(g)) // Interrupt Type Register 0
-#define RMIXLP_GPIO_INTTYPE0 _RMIXL_OFFSET(0x50) // Interrupt Type Register 0
-#define RMIXLP_GPIO_INTTYPE1 _RMIXL_OFFSET(0x51) // Interrupt Type Register 1
-#define RMIXLP_GPIO_INTSTAT(g) _RMIXL_OFFSET(0x52+(g)) // Interrupt Status Register 0
-#define RMIXLP_GPIO_INTSTAT0 _RMIXL_OFFSET(0x52) // Interrupt Status Register 0
-#define RMIXLP_GPIO_INTSTAT1 _RMIXL_OFFSET(0x53) // Interrupt Status Register 1
+#define RMIXLP_GPIO_8XX_INTPOL(g) _RMIXL_OFFSET((0x4E)+(g)) // Interrupt Polarity Register 0
+#define RMIXLP_GPIO_8XX_INTTYPE(g) _RMIXL_OFFSET(0x50+(g)) // Interrupt Type Register 0
+#define RMIXLP_GPIO_8XX_INTSTAT(g) _RMIXL_OFFSET(0x52+(g)) // Interrupt Status Register 0
+#define RMIXLP_GPIO_3XX_INTPOL(g) _RMIXL_OFFSET((0x5E)+(g)) // Interrupt Polarity Register 0
+#define RMIXLP_GPIO_3XX_INTTYPE(g) _RMIXL_OFFSET(0x60+(g)) // Interrupt Type Register 0
+#define RMIXLP_GPIO_3XX_INTSTAT(g) _RMIXL_OFFSET(0x62+(g)) // Interrupt Status Register 0
#define RMIXLP_GPIO_8XX_MAXPINS 41 /* 41 GPIO pins */
#define RMIXLP_GPIO_4XX_MAXPINS 41 /* 41 GPIO pins */
