Module Name: src
Committed By: matt
Date: Sat Dec 31 04:54:28 UTC 2011
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_i2creg.h rmixl_naereg.h
rmixlp_pcie.c rmixlreg.h
Log Message:
Consolidate and complete PCITAGs.
Print/Set BARs for AHCI and SRIO.
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/rmi/rmixl_i2creg.h \
src/sys/arch/mips/rmi/rmixl_naereg.h
cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/rmi/rmixlp_pcie.c
cvs rdiff -u -r1.1.2.17 -r1.1.2.18 src/sys/arch/mips/rmi/rmixlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixl_i2creg.h
diff -u src/sys/arch/mips/rmi/rmixl_i2creg.h:1.1.2.1 src/sys/arch/mips/rmi/rmixl_i2creg.h:1.1.2.2
--- src/sys/arch/mips/rmi/rmixl_i2creg.h:1.1.2.1 Sat Dec 24 01:57:54 2011
+++ src/sys/arch/mips/rmi/rmixl_i2creg.h Sat Dec 31 04:54:28 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_i2creg.h,v 1.1.2.1 2011/12/24 01:57:54 matt Exp $ */
+/* $NetBSD: rmixl_i2creg.h,v 1.1.2.2 2011/12/31 04:54:28 matt Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -38,8 +38,8 @@
* XLP I2C Controller defintions
*/
-#define RMIXLP_I2C0_PCITAG _RMIXL_PCITAG(0,6,2)
-#define RMIXLP_I2C1_PCITAG _RMIXL_PCITAG(0,6,3)
+#define RMIXLP_I2C1_PCITAG _RMIXL_PCITAG(0,6,2)
+#define RMIXLP_I2C2_PCITAG _RMIXL_PCITAG(0,6,3)
#define RMIXLP_I2C_CFG_OFFSET _RMIXL_OFFSET(0x40)
#define RMIXLP_I2C_IOSIZE _RMIXL_OFFSET(0x40)
Index: src/sys/arch/mips/rmi/rmixl_naereg.h
diff -u src/sys/arch/mips/rmi/rmixl_naereg.h:1.1.2.1 src/sys/arch/mips/rmi/rmixl_naereg.h:1.1.2.2
--- src/sys/arch/mips/rmi/rmixl_naereg.h:1.1.2.1 Sat Dec 24 01:57:54 2011
+++ src/sys/arch/mips/rmi/rmixl_naereg.h Sat Dec 31 04:54:28 2011
@@ -31,17 +31,38 @@
#define _MIPS_RMI_RMIXL_NAEREG_H
/*
- * RX P2P Descriptor
+ * RX P2P Descriptor (slightly different betewen XLS/XLR and XLP).
*/
-#define RMIXL_NEA_RXD_CONTEXT __BITS(63,54)
+#define RMIXLS_NEA_RXD_EOP __BIT(63)
+#define RMIXLS_NEA_RXD_STATUS __BITS(62,56)
+#define RMIXLS_NEA_RXD_CLASSID __BITS(55,54)
+#define RMIXLP_NEA_RXD_CONTEXT __BITS(59,54)
#define RMIXL_NEA_RXD_LENGTH __BITS(53,40)
-#define RMIXL_NEA_RXD_ADDRESS __BITS(39,6)
-#define RMIXL_NEA_RXD_UP __BIT(5)
-#define RMIXL_NEA_RXD_ERR __BIT(4)
-#define RMIXL_NEA_RXD_IC __BIT(3)
-#define RMIXL_NEA_RXD_TC __BIT(2)
-#define RMIXL_NEA_RXD_PP __BIT(1)
-#define RMIXL_NEA_RXD_P2P __BIT(0)
+/*
+ * L2 cacheline aligned address
+ */
+#define RMIXL_NEA_RXD_ADDRESS __BITS(39,5)
+#define RMIXLP_NEA_RXD_UP __BIT(5)
+#define RMIXLP_NEA_RXD_ERR __BIT(4)
+#define RMIXLS_NEA_RXD_UP __BIT(4)
+#define RMIXLS_NEA_RXD_PORTID __BIT(3,0)
+#define RMIXLP_NEA_RXD_IC __BIT(3) // IP CSUM valid
+#define RMIXLP_NEA_RXD_TC __BIT(2) // TCP CSUM valid
+#define RMIXLP_NEA_RXD_PP __BIT(1) // Prepad present
+#define RMIXLP_NEA_RXD_P2P __BIT(0)
+
+/*
+ * RXD Status field for XLS/XLR.
+ */
+#define RMIXLS_RXD_STATUS_ERROR __BIT(6)
+#define RMIXLS_RXD_STATUS_OK_BROADCAST __BIT(5)
+#define RMIXLS_RXD_STATUS_OK_MULTICAST __BIT(4)
+#define RMIXLS_RXD_STATUS_OK_UNICAST __BIT(3)
+#define RMIXLS_RXD_STATUS_ERROR_CODE __BIT(2)
+#define RMIXLS_RXD_STATUS_ERROR_CRC __BIT(1)
+#define RMIXLS_RXD_STATUS_OK_MACADDR __BITS(2,1)
+#define RMIXLS_RXD_STATUS_ERROR_LENGTH __BIT(0)
+#define RMIXLS_RXD_STATUS_OK_VLAN __BIT(0)
#define RMIXL_NEA_TXD_TYPE __BITS(63,62)
#define RMIXL_NEA_TXD_RDEX __BIT(61)
@@ -88,13 +109,19 @@
#define RMIXL_NEA_MSCD2_CRC_INS_OFFS __BITS(15,0)
#define RMIXL_NEA_TXFBD_TYPE __BITS(63,62)
-#define RMIXL_NEA_TXFBD_RDX __BIT(61)
-#define RMIXL_NEA_TXFBD__RSRVD0 __BITS(60,58)
-#define RMIXL_NEA_TXFBD_TS_VALID __BIT(57)
-#define RMIXL_NEA_TXFBD_TX_DONE __BIT(56)
-#define RMIXL_NEA_TXFBD_MAX_COLL_LATE_ABORT __BIT(55)
-#define RMIXL_NEA_TXFBD_UNDERRUN __BIT(54)
-#define RMIXL_NEA_TXFBD__RSRVD1 __BITS(53,50)
+#define RMIXLP_NEA_TXFBD_RDX __BIT(61)
+#define RMIXLP_NEA_TXFBD__RSRVD0 __BITS(60,58)
+#define RMIXLS_NEA_TXFBD_COLLISION __BIT(61)
+#define RMIXLS_NEA_TXFBD_BUS_ERROR __BIT(60)
+#define RMIXLS_NEA_TXFBD_UNDERRUN __BIT(59)
+#define RMIXLS_NEA_TXFBD_ABORT __BIT(58)
+#define RMIXLP_NEA_TXFBD_TS_VALID __BIT(57)
+#define RMIXLP_NEA_TXFBD_TX_DONE __BIT(56)
+#define RMIXLP_NEA_TXFBD_MAX_COLL_LATE_ABORT __BIT(55)
+#define RMIXLP_NEA_TXFBD_UNDERRUN __BIT(54)
+#define RMIXLS_NEA_TXFBD_PORT_ID __BITS(57,54)
+#define RMIXLP_NEA_TXFBD__RSRVD1 __BITS(53,50)
+#define RMIXLS_NEA_TXFBD_LENGTH __BITS(53,40) // always 0
#define RMIXL_NEA_TXFBD_CONTEXT __BITS(49,40)
#define RMIXL_NEA_TXFBD_ADDRESS __BITS(39,0)
@@ -102,6 +129,16 @@
#define RMIXL_NEA_RXFID_ADDRESS __BITS(39,6)
#define RMIXL_NEA_RXFID__RSRVD1 __BITS(5,0)
+#define RMIXL_NAE_GMAC0_BASE(n) (0x0000 + 0x2000*(n))
+#define RMIXL_NAE_GMAC1_BASE(n) (0x0200 + 0x2000*(n))
+#define RMIXL_NAE_GMAC2_BASE(n) (0x0400 + 0x2000*(n))
+#define RMIXL_NAE_GMAC3_BASE(n) (0x0600 + 0x2000*(n))
+#define RMIXL_NAE_XGMAC0_BASE(n) (0x0800 + 0x2000*(n))
+#define RMIXL_NAE_PHY_BASE(n) (0x1e00 + 0x2000*(n))
+#define RMIXL_NAE_BASE(n) 0xe000
+
+/* SGMII (GMAC) Registers */
+
#define RMIXL_GMAC_CONF1 _RMIXL_OFFSET(0x00) /* MAC Configuration 1 */
#define RMIXL_GMAC_CONF2 _RMIXL_OFFSET(0x01) /* MAC Configuration 2 */
#define RMIXL_GMAC_IPG_IFG _RMIXL_OFFSET(0x02) /* Interpacket Gap/IFG */
@@ -286,4 +323,307 @@ rmixl_gmac_station_addr_lo_make(const ui
#define RMIXL_GMAC_FILTER_CONFIG_MA1V __BIT(1) /* MAC Address 1 Valid */
#define RMIXL_GMAC_FILTER_CONFIG_MA0V __BIT(0) /* MAC Address 0 Valid */
+/* NEA Ingress Path Registers */
+
+#define RMIXL_NAE_RX_CONFIG _RMIXL_OFFSET(0x10) // Receive Configuration
+#define RMIXL_NAE_RX_IF_BASE_CONFIG0 _RMIXL_OFFSET(0x12) // Receive Interface Base Config 0
+#define RMIXL_NAE_RX_IF_BASE_CONFIG1 _RMIXL_OFFSET(0x13) // Receive Interface Base Config 1
+#define RMIXL_NAE_RX_IF_BASE_CONFIG2 _RMIXL_OFFSET(0x14) // Receive Interface Base Config 2
+#define RMIXL_NAE_RX_IF_BASE_CONFIG3 _RMIXL_OFFSET(0x15) // Receive Interface Base Config 3
+#define RMIXL_NAE_RX_IF_BASE_CONFIG4 _RMIXL_OFFSET(0x16) // Receive Interface Base Config 4
+#define RMIXL_NAE_RX_IF_BASE_CONFIG5 _RMIXL_OFFSET(0x17) // Receive Interface Base Config 5
+#define RMIXL_NAE_RX_IF_BASE_CONFIG6 _RMIXL_OFFSET(0x18) // Receive Interface Base Config 6
+#define RMIXL_NAE_RX_IF_BASE_CONFIG7 _RMIXL_OFFSET(0x19) // Receive Interface Base Config 7
+#define RMIXL_NAE_RX_IF_BASE_CONFIG8 _RMIXL_OFFSET(0x1A) // Receive Interface Base Config 8
+#define RMIXL_NAE_RX_IF_BASE_CONFIG9 _RMIXL_OFFSET(0x1B) // Receive Interface Base Config 9
+#define RMIXL_NAE_RX_IF_VEC_VALID _RMIXL_OFFSET(0x1C) // Receive Interface Vector Valid
+#define RMIXL_NAE_RX_IF_SLOT_CAL _RMIXL_OFFSET(0x1D) // Receive Calendar Valid Slots
+#define RMIXL_NAE_PARSER_CONFIG _RMIXL_OFFSET(0x1E) // Parser Configuration
+#define RMIXL_NAE_PARSER_SEQ_FIFO_CFG _RMIXL_OFFSET(0x1F) // Parser Sequence FIFO Carvings
+#define RMIXL_NAE_FREE_IN_LIFO_CFG _RMIXL_OFFSET(0x20) // Free-In LIFO Carvings
+#define RMIXL_NAE_RX_BUFFER_BASE_DEPTH_ADDR _RMIXL_OFFSET(0x21) // Receive Buffer Base Depth Carvings Index
+#define RMIXL_NAE_RX_BUFFER_BASE_DEPTH _RMIXL_OFFSET(0x22) // Receive Buffer Base Depth Carvings
+#define RMIXL_NAE_RX_UCORE_CFG _RMIXL_OFFSET(0x23) // Receive Micro-core Configuration Register
+#define RMIXL_NAE_RX_UCORE_CAM_MASK0_CFG _RMIXL_OFFSET(0x24) // Receive Micro-core CAM Mask0 Configuration Registers
+#define RMIXL_NAE_RX_UCORE_CAM_MASK1_CFG _RMIXL_OFFSET(0x25) // Receive Micro-core CAM Mask1 Configuration Registers
+#define RMIXL_NAE_RX_UCORE_CAM_MASK2_CFG _RMIXL_OFFSET(0x26) // Receive Micro-core CAM Mask2 Configuration Registers
+#define RMIXL_NAE_RX_UCORE_CAM_MASK3_CFG _RMIXL_OFFSET(0x27) // Receive Micro-core CAM Mask3 Configuration Registers
+#define RMIXL_NAE_FREE_IN_LIFO_UNIQ_SZ_CFG _RMIXL_OFFSET(0x28) // Free-In LIFO Descriptor Size Register
+#define RMIXL_NAE_RX_CRC_POLY0_CFG _RMIXL_OFFSET(0x2A) // Receive CRC Polynomial Register 0
+#define RMIXL_NAE_RX_CRC_POLY1_CFG _RMIXL_OFFSET(0x2B) // Receive CRC Polynomial Register 1
+#define RMIXL_NAE_FREE_SPILL0_MEM_CFG _RMIXL_OFFSET(0x2C) // Spill Memory Regioning Register 0
+#define RMIXL_NAE_FREE_SPILL1_MEM_CFG _RMIXL_OFFSET(0x2D) // Spill Memory Regioning Register 1
+#define RMIXL_NAE_FREE_LIFO_THRESHOLD_CFG _RMIXL_OFFSET(0x2E) // Free-In LIFO Threshold Configuration Register
+#define RMIXL_NAE_FLOW_CRC16_POLY_CFG _RMIXL_OFFSET(0x2F) // FlowID CRC16 Polynomial Configuration
+#define RMIXL_NAE_TEST _RMIXL_OFFSET(0x5F) // Test Register
+#define RMIXL_NAE_BIU_TIMEOUT_CFG _RMIXL_OFFSET(0x60) // Bus Interface Unit Timeout Configuration
+#define RMIXL_NAE_BIU_CFG _RMIXL_OFFSET(0x61) // Bus Interface Unit Configuration
+#define RMIXL_NAE_RX_FREE_LIFO_POP _RMIXL_OFFSET(0x62) // Receive Free-In LIFO Pop Configuration
+#define RMIXL_NAE_RX_DSBL_ECC _RMIXL_OFFSET(0x63) // Receive Disable ECC
+#define RMIXL_NAE_FLOW_BASE_MASK_CFG _RMIXL_OFFSET(0x80) // FlowID Base Mask Register
+#define RMIXL_NAE_POE_CLASS_SETUP_CFG _RMIXL_OFFSET(0x81) // POE Class Setup Configuration Register
+#define RMIXL_NAE_UCO_IFACE_MASK_CFG _RMIXL_OFFSET(0x82) // Micro-core Interface Mask Configuraton Register
+#define RMIXL_NAE_RX_BUFFER_XOFFON_THRESH _RMIXL_OFFSET(0x83) // Receive Buffer XOFF/XON Threshold
+#define RMIXL_NAE_FLOW_TABLE1_CFG _RMIXL_OFFSET(0x84) // Flow Table 1
+#define RMIXL_NAE_FLOW_CLASS_BASE_MASK _RMIXL_OFFSET(0x85) // Flow Class Base Mask
+#define RMIXL_NAE_FLOW_TABLE3_CFG _RMIXL_OFFSET(0x86) // Flow Table 3
+#define RMIXL_NAE_RX_FREE_LIFO_THRESH _RMIXL_OFFSET(0x87) // Receive Free-In LIFO Threshold
+#define RMIXL_NAE_RX_PARSER_UNCLA _RMIXL_OFFSET(0x88) // Receive Parser Unclassify
+#define RMIXL_NAE_RX_BUFF_INTR_THRESH _RMIXL_OFFSET(0x89) // Receive Buffer Interrupt Threshold
+#define RMIXL_NAE_IFACE_FIFO_CFG _RMIXL_OFFSET(0x8A) // Interface FIFO Carvings Register
+#define RMIXL_NAE_PARSER_SEQ_FIFOTH_CFG _RMIXL_OFFSET(0x8B) // Parser Sequence FIFO Threshold Configuration Register
+#define RMIXL_NAE_RX_ERRINJ_CTRL0 _RMIXL_OFFSET(0x8C) // Receive Error Injection Control Register 0
+#define RMIXL_NAE_RX_ERRINJ_CTRL1 _RMIXL_OFFSET(0x8D) // Receive Error Injection Control Register 1
+#define RMIXL_NAE_RX_ERR_LATCH0 _RMIXL_OFFSET(0x8E) // Receive Error Latch Register 0
+#define RMIXL_NAE_RX_ERR_LATCH1 _RMIXL_OFFSET(0x8F) // Receive Error Latch Register 1
+#define RMIXL_NAE_RX_PERF_CTR_CFG _RMIXL_OFFSET(0xA0) // Receive Performance Counter Configuration Register
+#define RMIXL_NAE_RX_PERF_CTR_VAL _RMIXL_OFFSET(0xA1) // Receive Performance Counter Value Register
+
+ // NAE Hardware Parser Registers
+
+#define RMIXL_NAE_L2_TYPE_PORTn(n) _RMIXL_OFFSET(0x210+(n)) // L2 Type 0-19
+#define RMIXL_NAE_L3_CTABLE_MASK0 _RMIXL_OFFSET(0x22C) // L3 CAM Table Masks
+#define RMIXL_NAE_L3_CTABLE_MASK1 _RMIXL_OFFSET(0x22D) // L3 CAM Table Masks
+#define RMIXL_NAE_L3_CTABLE_MASK2 _RMIXL_OFFSET(0x22E) // L3 CAM Table Masks
+#define RMIXL_NAE_L3_CTABLE_MASK3 _RMIXL_OFFSET(0x22F) // L3 CAM Table Masks
+#define RMIXL_NAE_L3_CTABLE_EVENn(n) _RMIXL_OFFSET(0x230+2*(n)) // L3 CAM Table Even 0-15
+#define RMIXL_NAE_L3_CTABLE_ODDn(n) _RMIXL_OFFSET(0x231+2*(n)) // L3 CAM Table Odd 0-15
+#define RMIXL_NAE_L4_CTABLEn(n) _RMIXL_OFFSET(0x250+(n)) // L4 CAM Table 0-15
+#define RMIXL_NAE_IPV6_EXT_HEAD0 _RMIXL_OFFSET(0x260) // IPv6 Extension Headers
+#define RMIXL_NAE_IPV6_EXT_HEAD1 _RMIXL_OFFSET(0x261) // IPv6 Extension Headers
+#define RMIXL_NAE_VLAN_TYPES01 _RMIXL_OFFSET(0x262) // VLAN Headers
+#define RMIXL_NAE_VLAN_TYPES23 _RMIXL_OFFSET(0x263) // VLAN Headers
+
+ // Egress Path Registers
+#define RMIXL_NAE_TX_CONFIG _RMIXL_OFFSET(0x11) // Transmit Configuration
+#define RMIXL_NAE_DMA_TX_CREDIT_TH _RMIXL_OFFSET(0x29) // DMA Transmit Credit Threshold
+#define RMIXL_NAE_STG1_STG2CRDT_CMD _RMIXL_OFFSET(0x30) // Stage1 to Stage2 Credit Command
+#define RMIXL_NAE_STG2_EHCRDT_CMD _RMIXL_OFFSET(0x32) // Stage2 to Exit Hold FIFO Credit Command
+#define RMIXL_NAE_STG2_FREECRDT_CMD _RMIXL_OFFSET(0x34) // Stage2 Free FIFO Credit Command
+#define RMIXL_NAE_STG2_STRCRDT_CMD _RMIXL_OFFSET(0x36) // Stage2 to Micro-Struct FIFO Credit Command
+#define RMIXL_NAE_VFBID_DESTMAP_CMD _RMIXL_OFFSET(0x3A) // VFBID to Destination Map Command
+#define RMIXL_NAE_STG1_PMEM_PROG _RMIXL_OFFSET(0x3C) // Stage1 Context Memory Pointer Setup
+#define RMIXL_NAE_STG2_PMEM_PROG _RMIXL_OFFSET(0x3E) // Stage2 Context Memory Pointer Setup
+#define RMIXL_NAE_EH_PMEM_PROG _RMIXL_OFFSET(0x40) // Exit Hold Context Memory Pointer Setup
+#define RMIXL_NAE_FREE_PMEM_PROG _RMIXL_OFFSET(0x42) // Free Context Memory Pointer Setup
+#define RMIXL_NAE_TX_DDR_ACTVLIST_CMD _RMIXL_OFFSET(0x44) // Transmit DRR Active List Setup
+#define RMIXL_NAE_TX_IF_BURSTMAX_CMD _RMIXL_OFFSET(0x46) // Transmit Interface Burst Max Setup
+#define RMIXL_NAE_TX_IF_ENABLE_CMD _RMIXL_OFFSET(0x48) // Transmit Interface Enable Command
+#define RMIXL_NAE_TX_PKTLEN_PMEM_CMD _RMIXL_OFFSET(0x4A) // Transmit Pktlen Pointer Memory Setup
+#define RMIXL_NAE_TX_SCHED_MAP_CMD0 _RMIXL_OFFSET(0x4C) // Transmit Context Scheduling and Mapping Setup
+#define RMIXL_NAE_TX_SCHED_MAP_CMD1 _RMIXL_OFFSET(0x4D) // Transmit Context Scheduling and Mapping Setup
+#define RMIXL_NAE_EGR_NIOR_CAL_LEN _RMIXL_OFFSET(0x4E) // Egress NetIOR Credit Calendar Length
+#define RMIXL_NAE_TX_PKT_PMEM_CMD0 _RMIXL_OFFSET(0x50) // Transmit Packet Pointer Memory Setup 0
+#define RMIXL_NAE_TX_PKT_PMEM_CMD1 _RMIXL_OFFSET(0x51) // Transmit Packet Pointer Memory Setup 1
+#define RMIXL_NAE_EGR_NIOR_CRDT_CAL_CMD _RMIXL_OFFSET(0x52) // Egress NetIOR Credit Calendar Setup
+#define RMIXL_NAE_TX_SCHED_CTRL _RMIXL_OFFSET(0x53) // Transmit Scheduler Control
+#define RMIXL_NAE_TX_CRC_POLY0 _RMIXL_OFFSET(0x54) // Transmit CRC Polynomial 0
+#define RMIXL_NAE_TX_CRC_POLY1 _RMIXL_OFFSET(0x55) // Transmit CRC Polynomial 1
+#define RMIXL_NAE_TX_CRC_POLY2 _RMIXL_OFFSET(0x56) // Transmit CRC Polynomial 2
+#define RMIXL_NAE_TX_CRC_POLY3 _RMIXL_OFFSET(0x57) // Transmit CRC Polynomial 3
+#define RMIXL_NAE_STR_PMEM_CMD _RMIXL_OFFSET(0x58) // MicroStruct Descriptor Pointer
+#define RMIXL_NAE_TX_IORCRDT_INIT _RMIXL_OFFSET(0x59) // Transmit Network Interface Credit Initialization
+#define RMIXL_NAE_TX_DSBL_ECC _RMIXL_OFFSET(0x5A) // Transmit Disable ECC
+#define RMIXL_NAE_TX_IORCRDT_IGNORE _RMIXL_OFFSET(0x5B) // Transmit Network Interface Credit Ignore
+#define RMIXL_NAE_TX_BW_VALUE0 _RMIXL_OFFSET(0x64) // Transmit Bandwidth Value 0
+#define RMIXL_NAE_TX_BW_VALUE1 _RMIXL_OFFSET(0x65) // Transmit Bandwidth Value 1
+#define RMIXL_NAE_TX_BW_VALUE2 _RMIXL_OFFSET(0x66) // Transmit Bandwidth Value 2
+#define RMIXL_NAE_TX_BW_VALUE3 _RMIXL_OFFSET(0x67) // Transmit Bandwidth Value 3
+#define RMIXL_NAE_TX_BW_CHOICE_CMD _RMIXL_OFFSET(0x68) // Transmit Bandwidth Select
+#define RMIXL_NAE_NAE_FREQ_CMD _RMIXL_OFFSET(0x69) // NAE Frequency Select
+#define RMIXL_NAE_NAE_TX_XOFF_RD_CMD _RMIXL_OFFSET(0x6A) // Transmit XOFF Read Command
+#define RMIXL_NAE_IFn_1588_TMSTMP_HI(n) _RMIXL_OFFSET(0x300+2*(n)) // Interface 0-18 1588 Timestamp High
+#define RMIXL_NAE_IFn_1588_TMSTMP_LO(n) _RMIXL_OFFSET(0x301+2*(n)) // Interface 0-18 1588 Timestamp Low
+#define RMIXL_NAE_TX_EL0 _RMIXL_OFFSET(0x328) // Transmit RAM Error Log 0
+#define RMIXL_NAE_TX_EL1 _RMIXL_OFFSET(0x329) // Transmit RAM Error Log 1
+#define RMIXL_NAE_EIC0 _RMIXL_OFFSET(0x32A) // Error Injection Control 0
+#define RMIXL_NAE_EIC1 _RMIXL_OFFSET(0x32B) // Error Injection Control 1
+#define RMIXL_NAE_STG1_STG2CRDT_STATUS _RMIXL_OFFSET(0x32C) // Stage1 to Stage2 Credit Status
+#define RMIXL_NAE_STG2_EHCRDT_STATUS _RMIXL_OFFSET(0x32D) // Stage2 to Exit Hold FIFO Credit Status
+#define RMIXL_NAE_STG2_FREECRDT_STATUS _RMIXL_OFFSET(0x32E) // Stage2 to FreeFIFO Credit Status
+#define RMIXL_NAE_STG2_STRCRDT_STATUS _RMIXL_OFFSET(0x32F) // Stage2 to Micro-Struct FIFO Credit Status
+#define RMIXL_NAE_TX_PERF_CNTR_INTR_STATUS _RMIXL_OFFSET(0x330) // Transmit Performance Counter Interrupt Status
+#define RMIXL_NAE_TX_PERF_CNTR_ROLL_STATUS _RMIXL_OFFSET(0x331) // Transmit Performance Counter Roll Status
+#define RMIXL_NAE_TX_PERF_CNTR0 _RMIXL_OFFSET(0x332) // Transmit Performance Counter 0
+#define RMIXL_NAE_TX_PERF_CTRL0 _RMIXL_OFFSET(0x333) // Transmit Performance Counter 0 Control
+#define RMIXL_NAE_TX_PERF_CNTR1 _RMIXL_OFFSET(0x334) // Transmit Performance Counter 1
+#define RMIXL_NAE_TX_PERF_CTRL1 _RMIXL_OFFSET(0x335) // Transmit Performance Counter 1 Control
+#define RMIXL_NAE_TX_PERF_CNTR2 _RMIXL_OFFSET(0x336) // Transmit Performance Counter 2
+#define RMIXL_NAE_TX_PERF_CTRL2 _RMIXL_OFFSET(0x337) // Transmit Performance Counter 2 Control
+#define RMIXL_NAE_TX_PERF_CNTR3 _RMIXL_OFFSET(0x338) // Transmit Performance Counter 3
+#define RMIXL_NAE_TX_PERF_CTRL3 _RMIXL_OFFSET(0x339) // Transmit Performance Counter 3 Control
+#define RMIXL_NAE_TX_PERF_CNTR4 _RMIXL_OFFSET(0x33A) // Transmit Performance Counter 4
+#define RMIXL_NAE_TX_PERF_CTRL4 _RMIXL_OFFSET(0x33B) // Transmit Performance Counter 4 Control
+#define RMIXL_NAE_TX_BW_CHOICE_STATUS _RMIXL_OFFSET(0x33C) // Transmit Bandwidth Select Status
+#define RMIXL_NAE_NAE_TXOFF_RD_STATUS _RMIXL_OFFSET(0x33D) // NAE Transmit XOFF Read Status
+#define RMIXL_NAE_VFBID_DESTMAP_STATUS _RMIXL_OFFSET(0x380) // VFBID to Destination Map Status
+#define RMIXL_NAE_STG2_PMEM_STATUS _RMIXL_OFFSET(0x381) // Stage2 Context Memory Pointer Status
+#define RMIXL_NAE_EH_PMEM_STATUS _RMIXL_OFFSET(0x382) // Exit Hold Context Memory Pointer Status
+#define RMIXL_NAE_FREE_PMEM_STATUS _RMIXL_OFFSET(0x383) // Free Context Memory Pointer Status
+#define RMIXL_NAE_TX_DDR_ACTVLIST_STATU S _RMIXL_OFFSET(0x384) // Transmit DRR Active List Status
+#define RMIXL_NAE_TX_IF_BURSTMAX_STATUS _RMIXL_OFFSET(0x385) // Transmit Interface Burst Max Status
+#define RMIXL_NAE_TX_PKTLEN_PMEM_STATUS _RMIXL_OFFSET(0x386) // Transmit Pktlen Pointer Memory Status
+#define RMIXL_NAE_TX_SCHED_MAP_STATUS0 _RMIXL_OFFSET(0x387) // Transmit Context Scheduling and Mapping Status0
+#define RMIXL_NAE_TX_SCHED_MAP_STATUS1 _RMIXL_OFFSET(0x388) // Transmit Context Scheduling and Mapping Status1
+#define RMIXL_NAE_TX_PKT_PMEM_STATUS _RMIXL_OFFSET(0x389) // Transmit Packet Pointer Memory Status
+#define RMIXL_NAE_STR_PMEM_STATUS _RMIXL_OFFSET(0x38A) // MicroStruct Pointer Memory Status
+#define RMIXL_NAE_EGR_NIOR_CAL_STATUS _RMIXL_OFFSET(0x38B) // Egress NetIOR Credit Calendar Status
+
+ // Interrupt Registers
+#define RMIXL_NAE_NET_IF_INTR_STATn(n) _RMIXL_OFFSET(0x280+2*(n)) // Interface 0-18 Interrupt Status Registers
+#define RMIXL_NAE_NET_IF_INTR_MASKn(n) _RMIXL_OFFSET(0x281+2*(n)) // Interface 0-18 Interrupt Mask Registers
+#define RMIXL_NAE_NET_COMMON0_INTR_STAT _RMIXL_OFFSET(0x2A8) // Common Interrupt Status Register 0
+#define RMIXL_NAE_NET_COMMON0_INTR_MASK _RMIXL_OFFSET(0x2A9) // Common Interrupt Mask Register 0
+#define RMIXL_NAE_NET_COMMON1_INTR_STAT _RMIXL_OFFSET(0x2AA) // Common Interrupt Status Register 1
+#define RMIXL_NAE_NET_COMMON1_INTR_MASK _RMIXL_OFFSET(0x2AB) // Common Interrupt Mask Register 1
+
+ // Note: In the following registers, registers IDs are in Interface 0xE.
+ // For Block/Interface/Register decoding, see Table 11-14.
+#define RMIXL_NAE_PHY_LANE<0-3>_STATUS _RMIXL_OFFSET(0-3) // PHY Lane <0-3> Status
+#define RMIXL_NAE_PHY_LANE<0-3>_CTRL _RMIXL_OFFSET(4-7) // PHY Lane <0-3> Control
+#define RMIXL_NAE_SYNCE_SEL_REFCLK _RMIXL_OFFSET(8) // Quad Sync-E Reference Clock Select Register
+
+ // Network Interface Top-Block Registers
+#define RMIXL_NAE_LANE_CFG_CPLX_0_1 _RMIXL_OFFSET(0x780) // Lane Configuration Complex 0 and 1
+#define RMIXL_NAE_LANE_CFG_CPLX_2_3 _RMIXL_OFFSET(0x781) // Lane Configuration Complex 2 and 3
+#define RMIXL_NAE_LANE_CFG_CPLX_4 _RMIXL_OFFSET(0x782) // Lane Configuration Complex 4
+
+#define RMIXL_NAE_SOFT_RESET _RMIXL_OFFSET(0x783) // Network Interface Soft Reset Register
+#define RMIXL_NAE_1588_PTP_OFFSET_HI _RMIXL_OFFSET(0x784) // IEEE 1588 Timer Offset High
+#define RMIXL_NAE_1588_PTP_OFFSET_LO _RMIXL_OFFSET(0x785) // IEEE 1588 Timer Offset Low
+#define RMIXL_NAE_1588_PTP_INC_DEN _RMIXL_OFFSET(0x786) // IEEE 1588 Incremental Denominator
+#define RMIXL_NAE_1588_PTP_INC_NUM _RMIXL_OFFSET(0x787) // IEEE 1588 Incremental Numerator
+#define RMIXL_NAE_1588_PTP_INC_INTG _RMIXL_OFFSET(0x788) // IEEE 1588 Incremental Integer
+#define RMIXL_NAE_1588_PTP_CONTROL _RMIXL_OFFSET(0x789) // IEEE 1588 Control
+#define RMIXL_NAE_1588_PTP_STATUS _RMIXL_OFFSET(0x78A) // IEEE 1588 Status
+#define RMIXL_NAE_1588_PTP_USER_VALUE_HI _RMIXL_OFFSET(0x78B) // IEEE 1588 User Value High
+#define RMIXL_NAE_1588_PTP_USER_VALUE_LO _RMIXL_OFFSET(0x78C) // IEEE 1588 User Value Low
+#define RMIXL_NAE_1588_PTP_TMR1_HI _RMIXL_OFFSET(0x78D) // IEEE 1588 Timer 1 High
+#define RMIXL_NAE_1588_PTP_TMR1_LOW _RMIXL_OFFSET(0x78E) // IEEE 1588 Timer 1 Low
+#define RMIXL_NAE_1588_PTP_TMR2_HI _RMIXL_OFFSET(0x78F) // IEEE 1588 Timer 2 High
+#define RMIXL_NAE_1588_PTP_TMR2_LOW _RMIXL_OFFSET(0x790) // IEEE 1588 Timer 2 Low
+#define RMIXL_NAE_1588_PTP_TMR3_HI _RMIXL_OFFSET(0x791) // IEEE 1588 Timer 3 High
+#define RMIXL_NAE_1588_PTP_TMR3_LOW _RMIXL_OFFSET(0x792) // IEEE 1588 Timer 3 Low
+#define RMIXL_NAE_TX_FC_CAL_IDX_TBL_CTRL _RMIXL_OFFSET(0x793) // Tx Flow Control Calendar Index Table Control
+#define RMIXL_NAE_TX_FC_CAL_TBL_CTRL _RMIXL_OFFSET(0x794) // Tx Flow Control Calendar Table Control
+#define RMIXL_NAE_TX_FC_CAL_TBL_DATA0 _RMIXL_OFFSET(0x795) // Tx Flow Control Table Data 0
+#define RMIXL_NAE_TX_FC_CAL_TBL_DATA1 _RMIXL_OFFSET(0x796) // Tx Flow Control Table Data 1
+#define RMIXL_NAE_TX_FC_CAL_TBL_DATA2 _RMIXL_OFFSET(0x797) // Tx Flow Control Table Data 2
+#define RMIXL_NAE_TX_FC_CAL_TBL_DATA3 _RMIXL_OFFSET(0x798) // Tx Flow Control Table Data 3
+#define RMIXL_NAE_INT_MDIO_CTRL _RMIXL_OFFSET(0x799) // Internal MDIO Master Control
+#define RMIXL_NAE_INT_MDIO_CTRL_DATA _RMIXL_OFFSET(0x79A) // Internal MDIO Control Data
+#define RMIXL_NAE_INT_MDIO_RD_STAT _RMIXL_OFFSET(0x79B) // Internal MDIO Read Status
+#define RMIXL_NAE_INT_MDIO_LINK_STAT _RMIXL_OFFSET(0x79C) // Internal MDIO MII Link Fail Status
+#define RMIXL_NAE_EXT_G0_MDIO_CTRL _RMIXL_OFFSET(0x79D) // External Gig 0 MDIO Master Control
+#define RMIXL_NAE_EXT_G0_MDIO_CTRL_DATA _RMIXL_OFFSET(0x79E) // External Gig 0 MDIO Master Control Data
+#define RMIXL_NAE_EXT_G0_MDIO_RD_STAT _RMIXL_OFFSET(0x79F) // External Gig 0 MDIO Master Read Status Data
+#define RMIXL_NAE_EXT_G0_MDIO_LINK_STAT _RMIXL_OFFSET(0x7A0) // External Gig 0 MDIO MII Link Fail Status
+#define RMIXL_NAE_EXT_G1_MDIO_CTRL _RMIXL_OFFSET(0x7A1) // External Gig 1 MDIO Master Control
+#define RMIXL_NAE_EXT_G1_MDIO_CTRL_DATA _RMIXL_OFFSET(0x7A2) // External Gig 1 MDIO Master Control Data
+#define RMIXL_NAE_EXT_G1_MDIO_RD_STAT _RMIXL_OFFSET(0x7A3) // External Gig 1 MDIO Master Read Status Data
+#define RMIXL_NAE_EXT_G1_MDIO_LINK_STAT _RMIXL_OFFSET(0x7A4) // External Gig 1 MDIO MII Link Fail Status
+#define RMIXL_NAE_EXT_XG0_MDIO_CTRL _RMIXL_OFFSET(0x7A5) // External XGig 0 MDIO Control
+#define RMIXL_NAE_EXT_XG0_MDIO_CTRL_DATA _RMIXL_OFFSET(0x7A6) // External XGig 0 MDIO Control Data
+#define RMIXL_NAE_EXT_XG0_MDIO_RD_STAT _RMIXL_OFFSET(0x7A7) // External XGig 0 MDIO Read Status
+#define RMIXL_NAE_EXT_XG0_MDIO_LINK_STAT _RMIXL_OFFSET(0x7A8) // External XGig 0 MDIO MII Link Fail Status
+#define RMIXL_NAE_EXT_XG1_MDIO_CTRL _RMIXL_OFFSET(0x7A9) // External XGig 1 MDIO Control
+#define RMIXL_NAE_EXT_XG1_MDIO_CTRL_DATA _RMIXL_OFFSET(0x7AA) // External XGig 1 MDIO Control Data
+#define RMIXL_NAE_EXT_XG1_MDIO_RD_STAT _RMIXL_OFFSET(0x7AB) // External XGig 1 MDIO Read Status
+#define RMIXL_NAE_EXT_XG1_MDIO_LINK_STAT _RMIXL_OFFSET(0x7AC) // External XGig 1 MDIO MII Link Fail Status
+#define RMIXL_NAE_GMAC_FC_SL0T0 _RMIXL_OFFSET(0x7AD) // GMAC Flow Control Slot 0
+#define RMIXL_NAE_GMAC_FC_SL0T1 _RMIXL_OFFSET(0x7AE) // GMAC Flow Control Slot 1
+#define RMIXL_NAE_GMAC_FC_SL0T2 _RMIXL_OFFSET(0x7AF) // GMAC Flow Control Slot 2
+#define RMIXL_NAE_GMAC_FC_SL0T3 _RMIXL_OFFSET(0x7B0) // GMAC Flow Control Slot 3
+#define RMIXL_NAE_NETIOR_NTB_SLOT _RMIXL_OFFSET(0x7B1) // Network Interface to NAE Ingress Bus Slot
+#define RMIXL_NAE_NETIOR_MISC_CTRL0 _RMIXL_OFFSET(0x7B2) // Miscellaneous Control 0
+#define RMIXL_NAE_NETIOR_INT0 _RMIXL_OFFSET(0x7B3) // Interrupt 0 - Lane Fault
+#define RMIXL_NAE_NETIOR_INT0_MASK _RMIXL_OFFSET(0x7B4) // Interrupt 0 Mask
+#define RMIXL_NAE_NETIOR_INT1 _RMIXL_OFFSET(0x7B5) // Interrupt 1 - Exception
+#define RMIXL_NAE_NETIOR_INT1_MASK _RMIXL_OFFSET(0x7B6) // Interrupt 1 Mask
+#define RMIXL_NAE_GMAC_PFC_REPEAT _RMIXL_OFFSET(0x7B7) // Priority Flow Control Repeat
+#define RMIXL_NAE_XGMAC_PFC_REPEAT _RMIXL_OFFSET(0x7B8) // XGMAC Priority Flow Control Repeat
+#define RMIXL_NAE_NETIOR_MISC_CTRL1 _RMIXL_OFFSET(0x7B9) // Miscellaneous Control 1
+#define RMIXL_NAE_NETIOR_MISC_CTRL2 _RMIXL_OFFSET(0x7BA) // Miscellaneous Control 2
+#define RMIXL_NAE_NETIOR_INT2 _RMIXL_OFFSET(0x7BB) // Interrupt 2 - Transition Not Detected
+#define RMIXL_NAE_NETIOR_INT2_MASK _RMIXL_OFFSET(0x7BC) // Interrupt 2 Mask
+#define RMIXL_NAE_NETIOR_MISC_CTRL3 _RMIXL_OFFSET(0x7BD) // Miscellaneous Control 3
+
+ // Receive Configuration (RX_CONFIG)
+
+ // Free-in descriptor Size Unique.
+ // Free In Descriptor Size is unique per Free-In LIFO pool.
+ // If this is set then FrInDescCLSize is not used.
+ // To program individual Free-In LIFO Sizes use the Free-In LIFO
+ // Descriptor Size Register (FREE_IN_LIFO_UNIQ_SZ_CFG).
+#define RMIXL_NAE_RX_CONFIG_FSU __BIT(31)
+ // Rx Status Mask.
+ // The 7 error status events mask. Set each bit for the error types
+ // shown below so that the Err bit in register
+ // Rx Packet Descriptor Format is set.
+#define RMIXL_NAE_RX_CONFIG_RSM __BITS(30,24)
+ // Bit 6: Truncated - If a packet overflows the NetIor ingress
+ // FIFOs, it will be truncated. This is the only place a packet
+ // can get truncated.
+#define RMIXL_NAE_RX_CONFIG_RSM_TRUNC __BIT(30)
+ // Bit 5: Pause - Only for SGMII/XAUI. Pause Frames can be directly
+ // understood and used by the hardware. If software does not want to
+ // decode these and drops them, then this bit needs to be set.
+#define RMIXL_NAE_RX_CONFIG_RSM_PAUSE __BIT(29)
+ // Bit 4: Rx OK - Good Packet
+#define RMIXL_NAE_RX_CONFIG_RSM_RX_OK __BIT(28)
+ // Bit 3: LengthOutOfRange - (legacy mode, should be 0)
+#define RMIXL_NAE_RX_CONFIG_RSM_LENGTH_RANGE __BIT(27)
+ // Bit 2: LengthCheckError - (legacy mode, should be 0)
+#define RMIXL_NAE_RX_CONFIG_RSM_LENGTH_CHECK __BIT(26)
+ // Bit 1: Link CRC error (bit 1 in INTR_STAT register)
+ // Could also be a "truncated packet"
+#define RMIXL_NAE_RX_CONFIG_RSM_LINK_CRC __BIT(25)
+ // Bit 0: Code Error (legacy mode; reserved)
+#define RMIXL_NAE_RX_CONFIG_RSM_CODE_ERROR __BIT(24)
+
+#define RMIXL_NAE_RX_CONFIG_PREPAD_SIZE __BITS(23,22) // Pre-pad Size in 16-byte units.
+#define RMIXL_NAE_RX_CONFIG_PREPAD_WORD3 __BITS(21,20) // Pre-pad Word 3
+#define RMIXL_NAE_RX_CONFIG_PREPAD_WORD2 __BITS(19,18) // Pre-pad Word 2
+#define RMIXL_NAE_RX_CONFIG_PREPAD_WORD1 __BITS(17,16) // Pre-pad Word 1
+#define RMIXL_NAE_RX_CONFIG_PREPAD_WORD0 __BITS(15,14) // Pre-pad Word 0
+#define RMIXL_NAE_RX_CONFIG_PREPAD_EN __BIT(13) // Pre-pad Enable
+
+#define RMIXL_NAE_RX_CONFIG_HPE __BIT(12) // H/W Parser Enable
+
+ // Free-In Descriptor Size (in 64-byte Cache Lines).
+ // If this field is set to 0, the descriptor size is 16 KB.
+#define RMIXL_NAE_RX_CONFIG_FREEIN_DESC_SIZE __BITS(11,4)
+
+#define RMIXL_NAE_RX_CONFIG_DED __BIT(3) // Device ECC Disable
+
+ // Receive Maximum Message Size minus one
+ // The POE adds its own descriptor to the number of descriptors
+#define RMIXL_NAE_RX_CONFIG_MMS __BITS(2,1)
+#define RMIXL_NAE_RX_CONFIG_MMS_ONE 0 // 1 descriptor
+#define RMIXL_NAE_RX_CONFIG_MMS_TWO 1 // 2 descriptors
+#define RMIXL_NAE_RX_CONFIG_MMS_THREE 2 // 3 descriptors
+#define RMIXL_NAE_RX_CONFIG_MMS_INVALID 3 // Invalid
+
+ // Rx Enable.
+#define RMIXL_NAE_RX_CONFIG_RE __BIT(0)
+
+ // Receive Interface Base Config <0-9> (RX_IF_BASE_CONFIG<0-9>)
+ // Block 7, Register 0x12..0x1b (8xx/4xx)
+ // Block 7, Register 0x12..0x16 (3xx)
+ // RX_IF_BASE_CONFIG0: Complex 0 phy0/phy1 (EVEN/ODD) Channel Offset,
+ // RX_IF_BASE_CONFIG1: Complex 0 phy2/phy3 (EVEN/ODD) Channel Offset,
+ // RX_IF_BASE_CONFIG2: Complex 1 phy0/phy1 (EVEN/ODD) Channel Offset,
+ // RX_IF_BASE_CONFIG3: Complex 1 phy2/phy3 (EVEN/ODD) Channel Offset,
+ // RX_IF_BASE_CONFIG4: Complex 2 phy0/phy1 (EVEN/ODD) Channel Offset,
+ // RX_IF_BASE_CONFIG5: Complex 2 phy2/phy3 (EVEN/ODD) Channel Offset,
+ // These are 8xx/4xx only:
+ // RX_IF_BASE_CONFIG6: Complex 3 phy0/phy1 (EVEN/ODD) Channel Offset,
+ // RX_IF_BASE_CONFIG7: Complex 3 phy2/phy3 (EVEN/ODD) Channel Offset,
+ // RX_IF_BASE_CONFIG8: Complex 4 phy0/phy1 (EVEN/ODD) Channel Offset,
+ // RX_IF_BASE_CONFIG9: Complex 4 phy2/phy3 (EVEN/ODD) Channel Offset,
+ // On XLP 800 and 400 processors, the valid range is 0-523.
+ // On XLP 300 and 300-Lite processors, the valid range is 0-127.
+#define RMIXL_NAE_RX_IF_BASE_CONFIG_ODD_LANE_BASE __BITS(25,16)
+#define RMIXL_NAE_RX_IF_BASE_CONFIG_EVEN_LANE_BASE __BITS(9,0)
+
#endif /* _MIPS_RMI_RMIXL_NAEREG_H */
Index: src/sys/arch/mips/rmi/rmixlp_pcie.c
diff -u src/sys/arch/mips/rmi/rmixlp_pcie.c:1.1.2.4 src/sys/arch/mips/rmi/rmixlp_pcie.c:1.1.2.5
--- src/sys/arch/mips/rmi/rmixlp_pcie.c:1.1.2.4 Fri Dec 30 06:42:29 2011
+++ src/sys/arch/mips/rmi/rmixlp_pcie.c Sat Dec 31 04:54:28 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlp_pcie.c,v 1.1.2.4 2011/12/30 06:42:29 matt Exp $ */
+/* $NetBSD: rmixlp_pcie.c,v 1.1.2.5 2011/12/31 04:54:28 matt Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rmixlp_pcie.c,v 1.1.2.4 2011/12/30 06:42:29 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rmixlp_pcie.c,v 1.1.2.5 2011/12/31 04:54:28 matt Exp $");
#include "opt_pci.h"
#include "pci.h"
@@ -655,7 +655,9 @@ rmixlp_pcie_configure_bus(struct rmixlp_
mem = rmixlp_pcie_set_bus0_bar0(sc, RMIXLP_OHCI3_PCITAG, mem);
mem = rmixlp_pcie_set_bus0_bar0(sc, RMIXLP_NAE_PCITAG, mem);
mem = rmixlp_pcie_set_bus0_bar0(sc, RMIXLP_POE_PCITAG, mem);
+ mem = rmixlp_pcie_set_bus0_bar0(sc, RMIXLP_AHCI_PCITAG, mem);
mem = rmixlp_pcie_set_bus0_bar0(sc, RMIXLP_FMN_PCITAG, mem);
+ mem = rmixlp_pcie_set_bus0_bar0(sc, RMIXLP_SRIO_PCITAG, mem);
} else {
rmixlp_pcie_print_bus0_bar0(sc, RMIXLP_EHCI0_PCITAG);
rmixlp_pcie_print_bus0_bar0(sc, RMIXLP_OHCI0_PCITAG);
@@ -665,7 +667,9 @@ rmixlp_pcie_configure_bus(struct rmixlp_
rmixlp_pcie_print_bus0_bar0(sc, RMIXLP_OHCI3_PCITAG);
rmixlp_pcie_print_bus0_bar0(sc, RMIXLP_NAE_PCITAG);
rmixlp_pcie_print_bus0_bar0(sc, RMIXLP_POE_PCITAG);
+ rmixlp_pcie_print_bus0_bar0(sc, RMIXLP_AHCI_PCITAG);
rmixlp_pcie_print_bus0_bar0(sc, RMIXLP_FMN_PCITAG);
+ rmixlp_pcie_print_bus0_bar0(sc, RMIXLP_SRIO_PCITAG);
}
for (size_t i = 0; i < 4; i++) {
Index: src/sys/arch/mips/rmi/rmixlreg.h
diff -u src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.17 src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.18
--- src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.17 Sat Dec 31 04:30:52 2011
+++ src/sys/arch/mips/rmi/rmixlreg.h Sat Dec 31 04:54:28 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlreg.h,v 1.1.2.17 2011/12/31 04:30:52 matt Exp $ */
+/* $NetBSD: rmixlreg.h,v 1.1.2.18 2011/12/31 04:54:28 matt Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -591,7 +591,6 @@
* lists "Reg ID" values not offsets
* Offsets are relative to RMIXL_IO_DEV_BRIDGE
*/
-#define RMIXL_PIC_PCITAG _RMIXL_PCITAG(0, 0, 4)
#define RMIXL_PIC_CONTROL _RMIXL_OFFSET(0x0)
#define RMIXL_PIC_IPIBASE _RMIXL_OFFSET(0x4)
#define RMIXL_PIC_INTRACK _RMIXL_OFFSET(0x6)
@@ -789,16 +788,8 @@
#define RMIXLP_PIC_INT_GPIO_PENDING_PICPENDB __BITS(11,0)
/*
- * RMIXLP Uart
- */
-#define RMIXLP_UART1_PCITAG _RMIXL_PCITAG(0, 6, 0)
-#define RMIXLP_UART2_PCITAG _RMIXL_PCITAG(0, 6, 1)
-
-/*
* GPIO Controller registers
*/
-#define RMIXLP_GPIO_PCITAG _RMIXL_PCITAG(0, 6, 4)
-
/* GPIO Signal Registers */
#define RMIXL_GPIO_INT_ENB _RMIXL_OFFSET(0x0) /* Interrupt Enable register */
#define RMIXL_GPIO_INT_INV _RMIXL_OFFSET(0x1) /* Interrupt Inversion register */
@@ -1257,7 +1248,6 @@
/*
* XLP PCIe Host Bridge Registers
*/
-#define RMIXLP_SBC_PCITAG _RMIXL_PCITAG(0, 0, 0)
#ifndef RMIXLP_SBC_PCIE_ECFG_PBASE
#define RMIXLP_SBC_PCIE_ECFG_PBASE 0x18000000
#endif
@@ -1406,20 +1396,13 @@
#define RMIXLP_SBC_GPIO_TSW _RMIXL_OFFSET(0x309) /* General I/O Time Slot Weight Register */
#define RMIXLP_SBC_FLASH_TSW _RMIXL_OFFSET(0x30A) /* Flash Time Slot Weight Register (NAND/NOR/SPI/MMC/SD) */
#define RMIXLP_SBC_NAE_TSW _RMIXL_OFFSET(0x30B) /* Network Acceleration Engine Time Slot Weight Register */
-#define RMIXLP_SBC_FNM_TSW _RMIXL_OFFSET(0x30C) /* Fast Messaging Network Time Slot Weight Register */
+#define RMIXLP_SBC_FMN_TSW _RMIXL_OFFSET(0x30C) /* Fast Messaging Network Time Slot Weight Register */
#define RMIXLP_SBC_DMAENG_TSW _RMIXL_OFFSET(0x30D) /* Data Transfer and RAID Engine Slot Weight Register */
#define RMIXLP_SBC_SEC_TSW _RMIXL_OFFSET(0x30E) /* Security Engine Slot Weight Register */
#define RMIXLP_SBC_RSAECC_TSW _RMIXL_OFFSET(0x30F) /* RSA/ECC Engine Slot Weight Register */
#define RMIXLP_SBC_BRIDGE_DATA_COUNTER _RMIXL_OFFSET(0x310) /* Bridge Data Counter Register */
#define RMIXLP_SBC_BYTE_SWAP _RMIXL_OFFSET(0x311) /* Byte Swap Register */
-#define RMIXLP_EHCI0_PCITAG _RMIXL_PCITAG(0,2,0)
-#define RMIXLP_OHCI0_PCITAG _RMIXL_PCITAG(0,2,1)
-#define RMIXLP_OHCI1_PCITAG _RMIXL_PCITAG(0,2,2)
-#define RMIXLP_EHCI1_PCITAG _RMIXL_PCITAG(0,2,3)
-#define RMIXLP_OHCI2_PCITAG _RMIXL_PCITAG(0,2,4)
-#define RMIXLP_OHCI3_PCITAG _RMIXL_PCITAG(0,2,5)
-
#define RMIXLP_USB_CTL0 _RMIXL_OFFSET(0x41)
#define RMIXLP_USB_BYTE_SWAP_DIS _RMIXL_OFFSET(0x49)
#define RMIXLP_USB_PHY0 _RMIXL_OFFSET(0x4A)
@@ -1446,10 +1429,48 @@
#define RMIXLP_USB_PHY0_PHYDETVBUS __BIT(1)
#define RMIXLP_USB_PHY0_USBPHYRESET __BIT(0)
+#define RMIXLP_SBC_PCITAG _RMIXL_PCITAG(0,0,0)
+#define RMIXLP_ICI1_PCITAG _RMIXL_PCITAG(0,0,1)
+#define RMIXLP_ICI2_PCITAG _RMIXL_PCITAG(0,0,2)
+#define RMIXLP_ICI3_PCITAG _RMIXL_PCITAG(0,0,3)
+#define RMIXLP_PIC_PCITAG _RMIXL_PCITAG(0,0,4)
+
+#define RMIXLP_PCIPORT0_PCITAG _RMIXL_PCITAG(0,0,0)
+#define RMIXLP_PCIPORT1_PCITAG _RMIXL_PCITAG(0,1,0)
+#define RMIXLP_PCIPORT2_PCITAG _RMIXL_PCITAG(0,2,0)
+#define RMIXLP_PCIPORT3_PCITAG _RMIXL_PCITAG(0,3,0)
+
+#define RMIXLP_EHCI0_PCITAG _RMIXL_PCITAG(0,2,0)
+#define RMIXLP_OHCI0_PCITAG _RMIXL_PCITAG(0,2,1)
+#define RMIXLP_OHCI1_PCITAG _RMIXL_PCITAG(0,2,2)
+#define RMIXLP_EHCI1_PCITAG _RMIXL_PCITAG(0,2,3)
+#define RMIXLP_OHCI2_PCITAG _RMIXL_PCITAG(0,2,4)
+#define RMIXLP_OHCI3_PCITAG _RMIXL_PCITAG(0,2,5)
+
#define RMIXLP_NAE_PCITAG _RMIXL_PCITAG(0,3,0)
#define RMIXLP_POE_PCITAG _RMIXL_PCITAG(0,3,1)
+#define RMIXLP_AHCI_PCITAG _RMIXL_PCITAG(0,3,2)
+
#define RMIXLP_FMN_PCITAG _RMIXL_PCITAG(0,4,0)
+#define RMIXLP_DMA_PCITAG _RMIXL_PCITAG(0,5,0)
+#define RMIXLP_SAE_PCITAG _RMIXL_PCITAG(0,5,1)
+#define RMIXLP_PKE_PCITAG _RMIXL_PCITAG(0,5,2)
+#define RMIXLP_SRIO_PCITAG _RMIXL_PCITAG(0,5,3)
+#define RMIXLP_RXE_PCITAG _RMIXL_PCITAG(0,5,4)
+
+#define RMIXLP_UART1_PCITAG _RMIXL_PCITAG(0,6,0)
+#define RMIXLP_UART2_PCITAG _RMIXL_PCITAG(0,6,1)
+#define RMIXLP_I2C1_PCITAG _RMIXL_PCITAG(0,6,2)
+#define RMIXLP_I2C2_PCITAG _RMIXL_PCITAG(0,6,3)
+#define RMIXLP_GPIO_PCITAG _RMIXL_PCITAG(0,6,4)
+#define RMIXLP_SM_PCITAG _RMIXL_PCITAG(0,6,5)
+#define RMIXLP_JTAG_PCITAG _RMIXL_PCITAG(0,6,6)
+
+#define RMIXLP_NOR_PCITAG _RMIXL_PCITAG(0,7,0)
+#define RMIXLP_NAND_PCITAG _RMIXL_PCITAG(0,7,1)
+#define RMIXLP_SPI_PCITAG _RMIXL_PCITAG(0,7,2)
+#define RMIXLP_MMC_PCITAG _RMIXL_PCITAG(0,7,3)
/*
* PCI PCIe control (contains the IRT info)
*/
@@ -1465,7 +1486,6 @@
/*
* XLP System Management Registers
*/
-#define RMIXLP_SM_PCITAG _RMIXL_PCITAG(0, 6, 5)
#define RMIXLP_SM_CHIP_RESET _RMIXL_OFFSET(0x40)
#define RMIXLP_SM_POWER_ON_RESET_CFG _RMIXL_OFFSET(0x41)
#define RMIXLP_SM_EFUSE_DEVICE_CFG_STATUS0 _RMIXL_OFFSET(0x42)
@@ -1488,7 +1508,6 @@
#define RMIXLP_SM_POWER_ON_RESET_CFG_NORSP __BIT(4)
#define RMIXLP_SM_POWER_ON_RESET_CFG_BD __BITS(3,0)
-#define RMIXLP_NOR_PCITAG _RMIXL_PCITAG(0,7,0)
#define RMIXLP_NOR_NCS 8
#define RMIXLP_NOR_CS_BASEADDRESSn(n) _RMIXL_OFFSET(0x40+(n))
#define RMIXLP_NOR_CS_BASELIMITn(n) _RMIXL_OFFSET(0x48+(n))
@@ -1636,11 +1655,9 @@
// RDY/BSY Status. 1: NOR device is ready.
#define RMIXLP_NOR_STATUS_RDYBSY __BIT(0)
-#define RMIXLP_NAND_PCITAG _RMIXL_PCITAG(0,7,1)
#define RMIXLP_NAND_RDYBSY_SEL _RMIXL_OFFSET(0x81)
-#define RMIXLP_SPI_PCITAG _RMIXL_PCITAG(0,7,2)
#define RMIXLP_SPI_CS_CONFIG(n) _RMIXL_OFFSET(0x40+0x10*(n))
#define RMIXLP_SPI_CS_FDIV(n) _RMIXL_OFFSET(0x41+0x10*(n))
@@ -1700,7 +1717,6 @@
#define RMIXLP_SPI_GPIO_PINS __BITS(28,22)
-#define RMIXLP_MMC_PCITAG _RMIXL_PCITAG(0,7,3)
#define RMIXLP_MMC_SLOTSIZE _RMIXL_OFFSET(0x40)
#define RMIXLP_MMC_SLOT0 _RMIXL_OFFSET(0x40)
