Module Name: src
Committed By: bsh
Date: Sun Apr 15 10:16:37 UTC 2012
Modified Files:
src/sys/arch/arm/imx: imx51_iomuxreg.h
src/sys/arch/evbarm/netwalker: netwalker_usb.c
Log Message:
delete many definitions like MUX_PIN_foo.
use MUX_PIN(foo) instead.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/imx/imx51_iomuxreg.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbarm/netwalker/netwalker_usb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/imx/imx51_iomuxreg.h
diff -u src/sys/arch/arm/imx/imx51_iomuxreg.h:1.1 src/sys/arch/arm/imx/imx51_iomuxreg.h:1.2
--- src/sys/arch/arm/imx/imx51_iomuxreg.h:1.1 Sat Nov 13 07:11:02 2010
+++ src/sys/arch/arm/imx/imx51_iomuxreg.h Sun Apr 15 10:16:37 2012
@@ -658,996 +658,25 @@
/* MUX & PAD Control */
-#define MUX_PIN_AUD3_BB_CK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK, \
- IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK)
-#define MUX_PIN_AUD3_BB_FS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS, \
- IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS)
-#define MUX_PIN_AUD3_BB_RXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD, \
- IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD)
-#define MUX_PIN_AUD3_BB_TXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD, \
- IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD)
-#define MUX_PIN_BOOT_MODE0 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0)
-#define MUX_PIN_BOOT_MODE1 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1)
-#define MUX_PIN_CKIL \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CKIL)
-#define MUX_PIN_CLK_SS \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CLK_SS)
-#define MUX_PIN_CSI1_D10 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D10, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D10)
-#define MUX_PIN_CSI1_D11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D11, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D11)
-#define MUX_PIN_CSI1_D12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D12, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D12)
-#define MUX_PIN_CSI1_D13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D13, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D13)
-#define MUX_PIN_CSI1_D14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D14, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D14)
-#define MUX_PIN_CSI1_D15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D15, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D15)
-#define MUX_PIN_CSI1_D16 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D16, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D16)
-#define MUX_PIN_CSI1_D17 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D17, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D17)
-#define MUX_PIN_CSI1_D18 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D18, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D18)
-#define MUX_PIN_CSI1_D19 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D19, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D19)
-#define MUX_PIN_CSI1_D8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D8, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D8)
-#define MUX_PIN_CSI1_D9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D9, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D9)
-#define MUX_PIN_CSI1_HSYNC \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC)
-#define MUX_PIN_CSI1_MCLK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK)
-#define MUX_PIN_CSI1_PIXCLK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK)
-#define MUX_PIN_CSI1_VSYNC \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC)
-#define MUX_PIN_CSI2_D12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D12, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D12)
-#define MUX_PIN_CSI2_D13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D13, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D13)
-#define MUX_PIN_CSI2_D14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D14, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D14)
-#define MUX_PIN_CSI2_D15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D15, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D15)
-#define MUX_PIN_CSI2_D16 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D16, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D16)
-#define MUX_PIN_CSI2_D17 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D17, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D17)
-#define MUX_PIN_CSI2_D18 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D18, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D18)
-#define MUX_PIN_CSI2_D19 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D19, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D19)
-#define MUX_PIN_CSI2_HSYNC \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC)
-#define MUX_PIN_CSI2_PIXCLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK)
-#define MUX_PIN_CSI2_VSYNC \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC)
-#define MUX_PIN_CSPI1_MISO \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO)
-#define MUX_PIN_CSPI1_MOSI \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI)
-#define MUX_PIN_CSPI1_RDY \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY)
-#define MUX_PIN_CSPI1_SCLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK)
-#define MUX_PIN_CSPI1_SS0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0)
-#define MUX_PIN_CSPI1_SS1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1)
-#define MUX_PIN_DI1_D0_CS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS)
-#define MUX_PIN_DI1_D1_CS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS)
-#define MUX_PIN_DI1_DISP_CLK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK)
-#define MUX_PIN_DI1_PIN11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11)
-#define MUX_PIN_DI1_PIN12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12)
-#define MUX_PIN_DI1_PIN13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13)
-#define MUX_PIN_DI1_PIN15 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15)
-#define MUX_PIN_DI1_PIN2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2)
-#define MUX_PIN_DI1_PIN3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3)
-#define MUX_PIN_DI2_DISP_CLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK, \
- IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK)
-#define MUX_PIN_DI2_PIN2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2, \
- IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2)
-#define MUX_PIN_DI2_PIN3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3, \
- IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3)
-#define MUX_PIN_DI2_PIN4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4, \
- IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4)
-#define MUX_PIN_DISP1_DAT0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0)
-#define MUX_PIN_DISP1_DAT1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1)
-#define MUX_PIN_DISP1_DAT10 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10)
-#define MUX_PIN_DISP1_DAT11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11)
-#define MUX_PIN_DISP1_DAT12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12)
-#define MUX_PIN_DISP1_DAT13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13)
-#define MUX_PIN_DISP1_DAT14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14)
-#define MUX_PIN_DISP1_DAT15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15)
-#define MUX_PIN_DISP1_DAT16 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16)
-#define MUX_PIN_DISP1_DAT17 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17)
-#define MUX_PIN_DISP1_DAT18 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18)
-#define MUX_PIN_DISP1_DAT19 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19)
-#define MUX_PIN_DISP1_DAT2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2)
-#define MUX_PIN_DISP1_DAT20 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20)
-#define MUX_PIN_DISP1_DAT21 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21)
-#define MUX_PIN_DISP1_DAT22 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22)
-#define MUX_PIN_DISP1_DAT23 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23)
-#define MUX_PIN_DISP1_DAT3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3)
-#define MUX_PIN_DISP1_DAT4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4)
-#define MUX_PIN_DISP1_DAT5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5)
-#define MUX_PIN_DISP1_DAT6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6)
-#define MUX_PIN_DISP1_DAT7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7)
-#define MUX_PIN_DISP1_DAT8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8)
-#define MUX_PIN_DISP1_DAT9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9)
-#define MUX_PIN_DISP2_DAT0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0)
-#define MUX_PIN_DISP2_DAT1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1)
-#define MUX_PIN_DISP2_DAT10 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10)
-#define MUX_PIN_DISP2_DAT11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11)
-#define MUX_PIN_DISP2_DAT12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12)
-#define MUX_PIN_DISP2_DAT13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13)
-#define MUX_PIN_DISP2_DAT14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14)
-#define MUX_PIN_DISP2_DAT15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15)
-#define MUX_PIN_DISP2_DAT2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2)
-#define MUX_PIN_DISP2_DAT3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3)
-#define MUX_PIN_DISP2_DAT4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4)
-#define MUX_PIN_DISP2_DAT5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5)
-#define MUX_PIN_DISP2_DAT6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6)
-#define MUX_PIN_DISP2_DAT7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7)
-#define MUX_PIN_DISP2_DAT8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8)
-#define MUX_PIN_DISP2_DAT9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9)
-#define MUX_PIN_DISPB2_SER_CLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK, \
- IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK)
-#define MUX_PIN_DISPB2_SER_DIN \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN, \
- IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN)
-#define MUX_PIN_DISPB2_SER_DIO \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO, \
- IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO)
-#define MUX_PIN_DISPB2_SER_RS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS, \
- IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS)
-#define MUX_PIN_DI_GP1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, \
- IOMUXC_SW_PAD_CTL_PAD_DI_GP1)
-#define MUX_PIN_DI_GP2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, \
- IOMUXC_SW_PAD_CTL_PAD_DI_GP2)
-#define MUX_PIN_DI_GP3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP3, \
- IOMUXC_SW_PAD_CTL_PAD_DI_GP3)
-#define MUX_PIN_DI_GP4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP4, \
- IOMUXC_SW_PAD_CTL_PAD_DI_GP4)
-#define MUX_PIN_DRAM_CAS \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS)
-#define MUX_PIN_DRAM_CS0 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0)
-#define MUX_PIN_DRAM_CS1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1, \
- IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1)
-#define MUX_PIN_DRAM_DQM0 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0)
-#define MUX_PIN_DRAM_DQM1 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1)
-#define MUX_PIN_DRAM_DQM2 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2)
-#define MUX_PIN_DRAM_DQM3 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3)
-#define MUX_PIN_DRAM_RAS \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS)
-#define MUX_PIN_DRAM_SDCKE0 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0)
-#define MUX_PIN_DRAM_SDCKE1 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1)
-#define MUX_PIN_DRAM_SDCLK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK)
-#define MUX_PIN_DRAM_SDQS0 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0)
-#define MUX_PIN_DRAM_SDQS1 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1)
-#define MUX_PIN_DRAM_SDQS2 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2)
-#define MUX_PIN_DRAM_SDQS3 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3)
-#define MUX_PIN_DRAM_SDWE \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE)
-#define MUX_PIN_EIM_A16 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A16, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A16)
-#define MUX_PIN_EIM_A17 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A17, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A17)
-#define MUX_PIN_EIM_A18 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A18, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A18)
-#define MUX_PIN_EIM_A19 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A19, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A19)
-#define MUX_PIN_EIM_A20 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A20, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A20)
-#define MUX_PIN_EIM_A21 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A21, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A21)
-#define MUX_PIN_EIM_A22 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A22, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A22)
-#define MUX_PIN_EIM_A23 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A23, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A23)
-#define MUX_PIN_EIM_A24 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A24, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A24)
-#define MUX_PIN_EIM_A25 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A25, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A25)
-#define MUX_PIN_EIM_A26 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A26, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A26)
-#define MUX_PIN_EIM_A27 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A27, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_A27)
-#define MUX_PIN_EIM_BCLK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK)
-#define MUX_PIN_EIM_CRE \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CRE, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_CRE)
-#define MUX_PIN_EIM_CS0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_CS0)
-#define MUX_PIN_EIM_CS1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS1, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_CS1)
-#define MUX_PIN_EIM_CS2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS2, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_CS2)
-#define MUX_PIN_EIM_CS3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS3, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_CS3)
-#define MUX_PIN_EIM_CS4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS4, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_CS4)
-#define MUX_PIN_EIM_CS5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS5, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_CS5)
-#define MUX_PIN_EIM_D16 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D16, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D16)
-#define MUX_PIN_EIM_D17 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D17, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D17)
-#define MUX_PIN_EIM_D18 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D18, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D18)
-#define MUX_PIN_EIM_D19 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D19, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D19)
-#define MUX_PIN_EIM_D20 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D20, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D20)
-#define MUX_PIN_EIM_D21 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D21, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D21)
-#define MUX_PIN_EIM_D22 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D22, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D22)
-#define MUX_PIN_EIM_D23 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D23, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D23)
-#define MUX_PIN_EIM_D24 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D24, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D24)
-#define MUX_PIN_EIM_D25 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D25, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D25)
-#define MUX_PIN_EIM_D26 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D26, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D26)
-#define MUX_PIN_EIM_D27 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D27, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D27)
-#define MUX_PIN_EIM_D28 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D28, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D28)
-#define MUX_PIN_EIM_D29 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D29, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D29)
-#define MUX_PIN_EIM_D30 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D30, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D30)
-#define MUX_PIN_EIM_D31 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D31, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_D31)
-#define MUX_PIN_EIM_DA0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA0, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA1, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA10 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA10, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA11, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA12, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA13, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA14, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA15, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA2, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA3, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA4, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA5, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA6, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA7, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA8, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA9, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DTACK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK)
-#define MUX_PIN_EIM_EB0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB0, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_EB0)
-#define MUX_PIN_EIM_EB1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB1, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_EB1)
-#define MUX_PIN_EIM_EB2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_EB2)
-#define MUX_PIN_EIM_EB3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_EB3)
-#define MUX_PIN_EIM_LBA \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_LBA)
-#define MUX_PIN_EIM_OE \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_OE, \
- IOMUXC_SW_PAD_CTL_PAD_EIM_OE)
-#define MUX_PIN_EIM_RW \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_RW)
-#define MUX_PIN_EIM_SDBA2 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2)
-#define MUX_PIN_EIM_SDODT0 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0)
-#define MUX_PIN_EIM_SDODT1 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1)
-#define MUX_PIN_EIM_WAIT \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT)
-#define MUX_PIN_GPIO1_0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_0, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_0)
-#define MUX_PIN_GPIO1_1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_1, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_1)
-#define MUX_PIN_GPIO1_2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_2, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_2)
-#define MUX_PIN_GPIO1_3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_3, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_3)
-#define MUX_PIN_GPIO1_4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_4, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_4)
-#define MUX_PIN_GPIO1_5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_5, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_5)
-#define MUX_PIN_GPIO1_6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_6, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_6)
-#define MUX_PIN_GPIO1_7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_7, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_7)
-#define MUX_PIN_GPIO1_8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_8, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_8)
-#define MUX_PIN_GPIO1_9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_9, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO1_9)
-#define MUX_PIN_GPIO_NAND \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND, \
- IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND)
-#define MUX_PIN_I2C1_CLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK, \
- IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK)
-#define MUX_PIN_I2C1_DAT \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT, \
- IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT)
-#define MUX_PIN_JTAG_DE_B \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B, \
- IOMUX_PAD_NONE)
-#define MUX_PIN_JTAG_MOD \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD)
-#define MUX_PIN_JTAG_TCK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK)
-#define MUX_PIN_JTAG_TDI \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI)
-#define MUX_PIN_JTAG_TMS \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS)
-#define MUX_PIN_JTAG_TRSTB \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB)
-#define MUX_PIN_KEY_COL0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL0, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_COL0)
-#define MUX_PIN_KEY_COL1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL1, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_COL1)
-#define MUX_PIN_KEY_COL2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL2, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_COL2)
-#define MUX_PIN_KEY_COL3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL3, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_COL3)
-#define MUX_PIN_KEY_COL4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL4, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_COL4)
-#define MUX_PIN_KEY_COL5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL5, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_COL5)
-#define MUX_PIN_KEY_ROW0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0)
-#define MUX_PIN_KEY_ROW1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1)
-#define MUX_PIN_KEY_ROW2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2)
-#define MUX_PIN_KEY_ROW3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3, \
- IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3)
-#define MUX_PIN_NANDF_ALE \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE)
-#define MUX_PIN_NANDF_CLE \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE)
-#define MUX_PIN_NANDF_CS0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0)
-#define MUX_PIN_NANDF_CS1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1)
-#define MUX_PIN_NANDF_CS2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2)
-#define MUX_PIN_NANDF_CS3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3)
-#define MUX_PIN_NANDF_CS4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4)
-#define MUX_PIN_NANDF_CS5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5)
-#define MUX_PIN_NANDF_CS6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6)
-#define MUX_PIN_NANDF_CS7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7)
-#define MUX_PIN_NANDF_D0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D0, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D0)
-#define MUX_PIN_NANDF_D1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D1, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D1)
-#define MUX_PIN_NANDF_D10 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D10, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D10)
-#define MUX_PIN_NANDF_D11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D11, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D11)
-#define MUX_PIN_NANDF_D12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D12, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D12)
-#define MUX_PIN_NANDF_D13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D13, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D13)
-#define MUX_PIN_NANDF_D14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D14, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D14)
-#define MUX_PIN_NANDF_D15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D15, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D15)
-#define MUX_PIN_NANDF_D2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D2, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D2)
-#define MUX_PIN_NANDF_D3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D3, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D3)
-#define MUX_PIN_NANDF_D4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D4, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D4)
-#define MUX_PIN_NANDF_D5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D5, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D5)
-#define MUX_PIN_NANDF_D6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D6, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D6)
-#define MUX_PIN_NANDF_D7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D7, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D7)
-#define MUX_PIN_NANDF_D8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D8, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D8)
-#define MUX_PIN_NANDF_D9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D9, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_D9)
-#define MUX_PIN_NANDF_RB0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0)
-#define MUX_PIN_NANDF_RB1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1)
-#define MUX_PIN_NANDF_RB2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2)
-#define MUX_PIN_NANDF_RB3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3)
-#define MUX_PIN_NANDF_RDY_INT \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT)
-#define MUX_PIN_NANDF_RE_B \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B)
-#define MUX_PIN_NANDF_WE_B \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B)
-#define MUX_PIN_NANDF_WP_B \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B, \
- IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B)
-#define MUX_PIN_OWIRE_LINE \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE, \
- IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE)
-#define MUX_PIN_PMIC_INT_REQ \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ, \
- IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ)
-#define MUX_PIN_PMIC_ON_REQ \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ)
-#define MUX_PIN_PMIC_RDY \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY)
-#define MUX_PIN_PMIC_STBY_REQ \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ)
-#define MUX_PIN_POR_B \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_POR_B)
-#define MUX_PIN_RESET_IN_B \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B)
-#define MUX_PIN_SD1_CLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_CLK, \
- IOMUXC_SW_PAD_CTL_PAD_SD1_CLK)
-#define MUX_PIN_SD1_CMD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_CMD, \
- IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)
-#define MUX_PIN_SD1_DATA0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0, \
- IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0)
-#define MUX_PIN_SD1_DATA1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1, \
- IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1)
-#define MUX_PIN_SD1_DATA2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2, \
- IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2)
-#define MUX_PIN_SD1_DATA3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3, \
- IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3)
-#define MUX_PIN_SD2_CLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_CLK, \
- IOMUXC_SW_PAD_CTL_PAD_SD2_CLK)
-#define MUX_PIN_SD2_CMD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_CMD, \
- IOMUXC_SW_PAD_CTL_PAD_SD2_CMD)
-#define MUX_PIN_SD2_DATA0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0, \
- IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0)
-#define MUX_PIN_SD2_DATA1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1, \
- IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1)
-#define MUX_PIN_SD2_DATA2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2, \
- IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2)
-#define MUX_PIN_SD2_DATA3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3, \
- IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3)
-#define MUX_PIN_UART1_CTS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_CTS, \
- IOMUXC_SW_PAD_CTL_PAD_UART1_CTS)
-#define MUX_PIN_UART1_RTS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_RTS, \
- IOMUXC_SW_PAD_CTL_PAD_UART1_RTS)
-#define MUX_PIN_UART1_RXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_RXD, \
- IOMUXC_SW_PAD_CTL_PAD_UART1_RXD)
-#define MUX_PIN_UART1_TXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_TXD, \
- IOMUXC_SW_PAD_CTL_PAD_UART1_TXD)
-#define MUX_PIN_UART2_RXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART2_RXD, \
- IOMUXC_SW_PAD_CTL_PAD_UART2_RXD)
-#define MUX_PIN_UART2_TXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART2_TXD, \
- IOMUXC_SW_PAD_CTL_PAD_UART2_TXD)
-#define MUX_PIN_UART3_RXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART3_RXD, \
- IOMUXC_SW_PAD_CTL_PAD_UART3_RXD)
-#define MUX_PIN_UART3_TXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART3_TXD, \
- IOMUXC_SW_PAD_CTL_PAD_UART3_TXD)
-#define MUX_PIN_USBH1_CLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK)
-#define MUX_PIN_USBH1_DATA0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0)
-#define MUX_PIN_USBH1_DATA1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1)
-#define MUX_PIN_USBH1_DATA2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2)
-#define MUX_PIN_USBH1_DATA3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3)
-#define MUX_PIN_USBH1_DATA4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4)
-#define MUX_PIN_USBH1_DATA5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5)
-#define MUX_PIN_USBH1_DATA6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6)
-#define MUX_PIN_USBH1_DATA7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7)
-#define MUX_PIN_USBH1_DIR \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR)
-#define MUX_PIN_USBH1_NXT \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT)
-#define MUX_PIN_USBH1_STP \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_STP, \
- IOMUXC_SW_PAD_CTL_PAD_USBH1_STP)
+#define MUX_PIN(name) \
+ IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \
+ IOMUXC_SW_PAD_CTL_PAD_##name)
+
+#define MUX_PIN_MUX(name) \
+ IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, IOMUX_PAD_NONE)
+
+#define MUX_PIN_PAD(name) \
+ IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_##name)
+
+#define MUX_PIN_GRP(name) \
+ IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_GRP_##name)
+
+#define MUX_PIN_PATH(name) \
+ IOMUX_PIN(IOMUXC_##name##_SELECT_INPUT, IOMUX_MUX_NONE)
/* INPUT Control */
-#define MUX_IN_AUDMUX_P4_INPUT_DA_AMX \
- IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P4_INPUT_DB_AMX \
- IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX \
- IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX \
- IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_DA_AMX \
- IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_DB_AMX \
- IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX \
- IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX \
- IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX \
- IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX \
- IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_DA_AMX \
- IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_DB_AMX \
- IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX \
- IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX \
- IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX \
- IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX \
- IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT
-#define MUX_IN_CCM_IPP_DI0_CLK \
- IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT
-#define MUX_IN_CCM_IPP_DI1_CLK \
- IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT
-#define MUX_IN_CCM_PLL1_BYPASS_CLK \
- IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT
-#define MUX_IN_CCM_PLL2_BYPASS_CLK \
- IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_CSPI_CLK_IN \
- IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_MISO \
- IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_MOSI \
- IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_SS1_B \
- IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_SS2_B \
- IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_SS3_B \
- IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT
-#define MUX_IN_DPLLIP1_L1T_TOG_EN \
- IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT
-#define MUX_IN_ECSPI2_IPP_IND_SS_B_1 \
- IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT
-#define MUX_IN_ECSPI2_IPP_IND_SS_B_3 \
- IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT
-#define MUX_IN_EMI_IPP_IND_RDY_INT \
- IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT
-#define MUX_IN_ESDHC3_IPP_DAT0_IN \
- IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT
-#define MUX_IN_ESDHC3_IPP_DAT1_IN \
- IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT
-#define MUX_IN_ESDHC3_IPP_DAT2_IN \
- IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT
-#define MUX_IN_ESDHC3_IPP_DAT3_IN \
- IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT
-#define MUX_IN_FEC_FEC_COL \
- IOMUXC_FEC_FEC_COL_SELECT_INPUT
-#define MUX_IN_FEC_FEC_CRS \
- IOMUXC_FEC_FEC_CRS_SELECT_INPUT
-#define MUX_IN_FEC_FEC_MDI \
- IOMUXC_FEC_FEC_MDI_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RDATA_0 \
- IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RDATA_1 \
- IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RDATA_2 \
- IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RDATA_3 \
- IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RX_CLK \
- IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RX_DV \
- IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RX_ER \
- IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT
-#define MUX_IN_FEC_FEC_TX_CLK \
- IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_1 \
- IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_2 \
- IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_3 \
- IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_4 \
- IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_5 \
- IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_6 \
- IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_7 \
- IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_8 \
- IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_12 \
- IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT
-#define MUX_IN_HSC_MIPI_MIX_PAR0_VSYNC \
- IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT
-#define MUX_IN_HSC_MIPI_MIX_PAR1_DI_WAIT \
- IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT
-#define MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG \
- IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT
-#define MUX_IN_I2C1_IPP_SCL_IN \
- IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT
-#define MUX_IN_I2C1_IPP_SDA_IN \
- IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT
-#define MUX_IN_I2C2_IPP_SCL_IN \
- IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT
-#define MUX_IN_I2C2_IPP_SDA_IN \
- IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT
-#define MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D \
- IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT
-#define MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D \
- IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_COL_6 \
- IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_COL_7 \
- IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_ROW_4 \
- IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_ROW_5 \
- IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_ROW_6 \
- IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_ROW_7 \
- IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT
-#define MUX_IN_UART1_IPP_UART_RTS_B \
- IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT
-#define MUX_IN_UART1_IPP_UART_RXD_MUX \
- IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
-#define MUX_IN_UART2_IPP_UART_RTS_B \
- IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT
-#define MUX_IN_UART2_IPP_UART_RXD_MUX \
- IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
-#define MUX_IN_UART3_IPP_UART_RTS_B \
- IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
-#define MUX_IN_UART3_IPP_UART_RXD_MUX \
- IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_CLK \
- IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_0 \
- IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_1 \
- IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_2 \
- IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_3 \
- IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_4 \
- IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_5 \
- IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_6 \
- IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_7 \
- IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DIR \
- IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_NXT \
- IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_STP \
- IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT
+#define MUX_SELECT(name) (name##_SELECT_INPUT)
#endif /* _IMX51_IOMUXREG_H */
Index: src/sys/arch/evbarm/netwalker/netwalker_usb.c
diff -u src/sys/arch/evbarm/netwalker/netwalker_usb.c:1.1 src/sys/arch/evbarm/netwalker/netwalker_usb.c:1.2
--- src/sys/arch/evbarm/netwalker/netwalker_usb.c:1.1 Thu Dec 9 04:40:22 2010
+++ src/sys/arch/evbarm/netwalker/netwalker_usb.c Sun Apr 15 10:16:37 2012
@@ -25,7 +25,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: netwalker_usb.c,v 1.1 2010/12/09 04:40:22 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netwalker_usb.c,v 1.2 2012/04/15 10:16:37 bsh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -144,7 +144,7 @@ init_h1(struct imxehci_softc *sc)
uint32_t reg;
/* output HIGH to USBH1_STP */
- gpio_data_write(GPIO_NO(1,27), 1);
+ gpio_data_write(GPIO_NO(1, 27), 1);
gpio_set_direction(GPIO_NO(1, 27), GPIO_DIR_OUT);
iomux_mux_config(iomux_usb1_config);
@@ -173,14 +173,13 @@ init_h1(struct imxehci_softc *sc)
bus_space_write_4(usbc->sc_iot, usbc->sc_ioh,
USBOH3_USBCTRL, reg);
- iomux_set_function(MUX_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+ iomux_set_function(MUX_PIN(USBH1_STP), IOMUX_CONFIG_ALT0);
/* HUB RESET release */
gpio_data_write(GPIO_NO(1, 7), 1);
gpio_set_direction(GPIO_NO(1, 7), GPIO_DIR_OUT);
-
/* Drive 26M_OSC_EN line high 3_1 */
gpio_data_write(GPIO_NO(3, 1), 1);
gpio_set_direction(GPIO_NO(3, 1), GPIO_DIR_OUT);
@@ -193,7 +192,7 @@ init_h1(struct imxehci_softc *sc)
delay(10 * 1000);
gpio_data_write(GPIO_NO(2, 5), 1);
gpio_set_direction(GPIO_NO(2, 5), GPIO_DIR_OUT);
- iomux_set_function(MUX_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
+ iomux_set_function(MUX_PIN(EIM_D21), IOMUX_CONFIG_ALT1);
delay(5 * 1000);
}
@@ -206,7 +205,7 @@ const struct iomux_conf iomux_usb1_confi
{
/* Initially setup this pin for GPIO, and change to
* USBH1_STP later */
- .pin = MUX_PIN_USBH1_STP,
+ .pin = MUX_PIN(USBH1_STP),
.mux = IOMUX_CONFIG_ALT2,
.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
PAD_CTL_KEEPER | PAD_CTL_HYS)
@@ -214,14 +213,14 @@ const struct iomux_conf iomux_usb1_confi
{
/* Clock */
- .pin = MUX_PIN_USBH1_CLK,
+ .pin = MUX_PIN(USBH1_CLK),
.mux = IOMUX_CONFIG_ALT0,
- .pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
+ .pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
PAD_CTL_KEEPER | PAD_CTL_HYS)
},
{
/* DIR */
- .pin = MUX_PIN_USBH1_DIR,
+ .pin = MUX_PIN(USBH1_DIR),
.mux = IOMUX_CONFIG_ALT0,
.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
PAD_CTL_KEEPER | PAD_CTL_HYS)
@@ -229,7 +228,7 @@ const struct iomux_conf iomux_usb1_confi
{
/* NXT */
- .pin = MUX_PIN_USBH1_NXT,
+ .pin = MUX_PIN(USBH1_NXT),
.mux = IOMUX_CONFIG_ALT0,
.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
PAD_CTL_KEEPER | PAD_CTL_HYS)
@@ -238,7 +237,7 @@ const struct iomux_conf iomux_usb1_confi
#define USBH1_DATA_CONFIG(n) \
{ \
/* DATA n */ \
- .pin = __CONCAT(MUX_PIN_USBH1_DATA,n), \
+ .pin = MUX_PIN(USBH1_DATA##n), \
.mux = IOMUX_CONFIG_ALT0, \
.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH | \
PAD_CTL_KEEPER | PAD_CTL_PUS_100K_PU | \
@@ -257,21 +256,21 @@ const struct iomux_conf iomux_usb1_confi
{
/* USB_CLK_EN_B GPIO2[1]*/
- .pin = MUX_PIN_EIM_D17,
+ .pin = MUX_PIN(EIM_D17),
.mux = IOMUX_CONFIG_ALT1,
.pad = (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE),
},
{
/* USB PHY RESETB */
- .pin = MUX_PIN_EIM_D21,
+ .pin = MUX_PIN(EIM_D21),
.mux = IOMUX_CONFIG_ALT1,
.pad = (PAD_CTL_DSE_HIGH | PAD_CTL_KEEPER |
PAD_CTL_PUS_100K_PU | PAD_CTL_SRE)
},
{
/* USB HUB RESET */
- .pin = MUX_PIN_GPIO1_7,
+ .pin = MUX_PIN(GPIO1_7),
.mux = IOMUX_CONFIG_ALT0,
.pad = (PAD_CTL_DSE_HIGH | PAD_CTL_SRE),
},
