Module Name: src
Committed By: bsh
Date: Tue Apr 17 09:33:31 UTC 2012
Modified Files:
src/sys/arch/arm/imx: imx51_axi.c imx51_clock.c imxclock.c
imxclockvar.h
src/sys/arch/evbarm/conf: NETWALKER
Added Files:
src/sys/arch/arm/imx: imx51_ccm.c imx51_ccmreg.h imx51_ccmvar.h
imx51_dpllreg.h
Log Message:
driver for i.MX51 Clock Controller Module.
from Kenichi Hashimoto.
Currently used only to get peripheral clock frequencies.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/imx/imx51_axi.c \
src/sys/arch/arm/imx/imx51_clock.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/imx/imx51_ccm.c \
src/sys/arch/arm/imx/imx51_ccmreg.h src/sys/arch/arm/imx/imx51_ccmvar.h \
src/sys/arch/arm/imx/imx51_dpllreg.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/imx/imxclock.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/imx/imxclockvar.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbarm/conf/NETWALKER
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/imx/imx51_axi.c
diff -u src/sys/arch/arm/imx/imx51_axi.c:1.2 src/sys/arch/arm/imx/imx51_axi.c:1.3
--- src/sys/arch/arm/imx/imx51_axi.c:1.2 Tue Nov 30 13:05:27 2010
+++ src/sys/arch/arm/imx/imx51_axi.c Tue Apr 17 09:33:31 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_axi.c,v 1.2 2010/11/30 13:05:27 bsh Exp $ */
+/* $NetBSD: imx51_axi.c,v 1.3 2012/04/17 09:33:31 bsh Exp $ */
/*-
* Copyright (c) 2010 SHIMIZU Ryo <r...@nerv.org>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_axi.c,v 1.2 2010/11/30 13:05:27 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_axi.c,v 1.3 2012/04/17 09:33:31 bsh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -38,6 +38,7 @@ __KERNEL_RCSID(0, "$NetBSD: imx51_axi.c,
#include <arm/imx/imx51reg.h>
#include <arm/imx/imx51var.h>
+#include "bus_dma_generic.h"
#include "locators.h"
struct axi_softc {
@@ -102,6 +103,7 @@ axi_critical_search(device_t parent, str
if ((strcmp(cf->cf_name, "tzic") != 0) &&
(strcmp(cf->cf_name, "imxuart") != 0) &&
+ (strcmp(cf->cf_name, "imxccm") != 0) &&
(strcmp(cf->cf_name, "imxgpio") != 0))
return 0;
Index: src/sys/arch/arm/imx/imx51_clock.c
diff -u src/sys/arch/arm/imx/imx51_clock.c:1.2 src/sys/arch/arm/imx/imx51_clock.c:1.3
--- src/sys/arch/arm/imx/imx51_clock.c:1.2 Fri Jul 1 20:27:50 2011
+++ src/sys/arch/arm/imx/imx51_clock.c Tue Apr 17 09:33:31 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_clock.c,v 1.2 2011/07/01 20:27:50 dyoung Exp $ */
+/* $NetBSD: imx51_clock.c,v 1.3 2012/04/17 09:33:31 bsh Exp $ */
/*
* Copyright (c) 2009 Genetec corp. All rights reserved.
* Written by Hashimoto Kenichi for Genetec corp.
@@ -25,7 +25,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_clock.c,v 1.2 2011/07/01 20:27:50 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_clock.c,v 1.3 2012/04/17 09:33:31 bsh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -48,7 +48,7 @@ __KERNEL_RCSID(0, "$NetBSD: imx51_clock.
#include <arm/imx/imx51reg.h>
#include <arm/imx/imx51var.h>
#include <arm/imx/imxepitreg.h>
-//#include <arm/imx/imx51_ccmvar.h> notyet
+#include <arm/imx/imx51_ccmvar.h>
#include <arm/imx/imxclockvar.h>
#include "imxccm.h" /* if CCM driver is configured into the kernel */
@@ -90,8 +90,6 @@ imxclock_attach(device_t parent, device_
sc->sc_iot = aa->aa_iot;
sc->sc_intr = aa->aa_irq;
- KASSERT((sc->sc_intr == IRQ_EPIT1) || (sc->sc_intr == IRQ_EPIT2));
-
switch ( aa->aa_addr ) {
case EPIT1_BASE:
epit1_sc = sc;
@@ -106,6 +104,8 @@ imxclock_attach(device_t parent, device_
if (bus_space_map(aa->aa_iot, aa->aa_addr, aa->aa_size, 0, &sc->sc_ioh))
panic("%s: Cannot map registers", device_xname(self));
+
+ sc->sc_clksrc = EPITCR_CLKSRC_IPG;
}
int
@@ -113,11 +113,7 @@ imxclock_get_timerfreq(struct imxclock_s
{
unsigned int ipg_freq;
#if NIMXCCM > 0
- struct imx51_clocks clk;
-
- imx51_get_clocks(&clk);
-
- ipg_freq = clk.ipg_clk;
+ ipg_freq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
#else
#ifndef IMX51_IPGCLK_FREQ
#error IMX51_IPGCLK_FREQ need to be defined.
Index: src/sys/arch/arm/imx/imxclock.c
diff -u src/sys/arch/arm/imx/imxclock.c:1.4 src/sys/arch/arm/imx/imxclock.c:1.5
--- src/sys/arch/arm/imx/imxclock.c:1.4 Fri Jul 1 20:27:50 2011
+++ src/sys/arch/arm/imx/imxclock.c Tue Apr 17 09:33:31 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: imxclock.c,v 1.4 2011/07/01 20:27:50 dyoung Exp $ */
+/* $NetBSD: imxclock.c,v 1.5 2012/04/17 09:33:31 bsh Exp $ */
/*
* Copyright (c) 2009, 2010 Genetec corp. All rights reserved.
* Written by Hashimoto Kenichi for Genetec corp.
@@ -70,7 +70,7 @@ void
cpu_initclocks(void)
{
uint32_t reg;
- int freq;
+ u_int freq;
if (!epit1_sc) {
panic("%s: driver has not been initialized!", __FUNCTION__);
@@ -80,6 +80,9 @@ cpu_initclocks(void)
imx_epit_timecounter.tc_frequency = freq;
tc_init(&imx_epit_timecounter);
+ aprint_verbose_dev(epit1_sc->sc_dev,
+ "timer clock frequency %d\n", freq);
+
epit1_sc->sc_reload_value = freq / hz - 1;
/* stop all timers */
@@ -92,11 +95,13 @@ cpu_initclocks(void)
epit1_sc->sc_reload_value);
bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCMPR, 0);
- reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD;
- bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, reg);
- reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_CLKSRC_HIGH |
- EPITCR_WAITEN | EPITCR_DOZEN | EPITCR_STOPEN;
- bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, reg);
+ reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD | epit1_sc->sc_clksrc;
+ bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
+ EPIT_EPITCR, reg);
+ reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_WAITEN | EPITCR_DOZEN |
+ EPITCR_STOPEN;
+ bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
+ EPIT_EPITCR, reg);
epit1_sc->sc_ih = intr_establish(epit1_sc->sc_intr, IPL_CLOCK,
IST_LEVEL, imxclock_intr, epit1_sc);
Index: src/sys/arch/arm/imx/imxclockvar.h
diff -u src/sys/arch/arm/imx/imxclockvar.h:1.1 src/sys/arch/arm/imx/imxclockvar.h:1.2
--- src/sys/arch/arm/imx/imxclockvar.h:1.1 Sat Nov 13 06:51:37 2010
+++ src/sys/arch/arm/imx/imxclockvar.h Tue Apr 17 09:33:31 2012
@@ -9,6 +9,8 @@ struct imxclock_softc {
int sc_reload_value;
+ uint32_t sc_clksrc;
+
void *sc_ih; /* interrupt handler */
};
Index: src/sys/arch/evbarm/conf/NETWALKER
diff -u src/sys/arch/evbarm/conf/NETWALKER:1.9 src/sys/arch/evbarm/conf/NETWALKER:1.10
--- src/sys/arch/evbarm/conf/NETWALKER:1.9 Tue Apr 17 07:43:21 2012
+++ src/sys/arch/evbarm/conf/NETWALKER Tue Apr 17 09:33:31 2012
@@ -1,4 +1,4 @@
-# $NetBSD: NETWALKER,v 1.9 2012/04/17 07:43:21 bsh Exp $
+# $NetBSD: NETWALKER,v 1.10 2012/04/17 09:33:31 bsh Exp $
#
# NETWALKER -- http://www.sharp.co.jp/netwalker/
#
@@ -177,6 +177,10 @@ imxuart0 at axi? addr 0x73fbc000 irq 31
#imxuart2 at axi? addr 0x7000c000 irq 33
options IMXUARTCONSOLE
+# Clock Control
+imxccm0 at axi? addr 0x73fd4000
+options IMX51_CKIL_FREQ=32768
+
# Enhanced Periodic Interrupt Timer
imxclock0 at axi? addr 0x73fac000 size 0x4000 irq 40
imxclock1 at axi? addr 0x73fb0000 size 0x4000 irq 41
Added files:
Index: src/sys/arch/arm/imx/imx51_ccm.c
diff -u /dev/null src/sys/arch/arm/imx/imx51_ccm.c:1.1
--- /dev/null Tue Apr 17 09:33:31 2012
+++ src/sys/arch/arm/imx/imx51_ccm.c Tue Apr 17 09:33:31 2012
@@ -0,0 +1,425 @@
+/* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Clock Controller Module (CCM)
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $");
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/param.h>
+
+#include <machine/cpu.h>
+
+#include <arm/imx/imx51_ccmvar.h>
+#include <arm/imx/imx51_ccmreg.h>
+#include <arm/imx/imx51_dpllreg.h>
+
+#include <arm/imx/imx51var.h>
+#include <arm/imx/imx51reg.h>
+
+#include "opt_imx51clk.h"
+#include "locators.h"
+
+//#define IMXCCMDEBUG
+
+#ifndef IMX51_OSC_FREQ
+#define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
+#endif
+
+struct imxccm_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+
+ struct {
+ bus_space_handle_t pll_ioh;
+ u_int pll_freq;
+ } sc_pll[IMX51_N_DPLLS];
+};
+
+struct imxccm_softc *ccm_softc;
+
+static uint64_t imx51_get_pll_freq(u_int);
+
+static int imxccm_match(device_t, cfdata_t, void *);
+static void imxccm_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(imxccm, sizeof(struct imxccm_softc),
+ imxccm_match, imxccm_attach, NULL, NULL);
+
+static int
+imxccm_match(device_t parent, cfdata_t cfdata, void *aux)
+{
+ struct axi_attach_args *aa = aux;
+
+ if (aa->aa_addr == CCMC_BASE)
+ return 1;
+
+ return 0;
+}
+
+static void
+imxccm_attach(device_t parent, device_t self, void *aux)
+{
+ struct axi_attach_args *aa = aux;
+ bus_space_tag_t iot = aa->aa_iot;
+ int i;
+
+ ccm_softc = device_private(self);
+ ccm_softc->sc_dev = self;
+ ccm_softc->sc_iot = iot;
+
+ if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0,
+ &ccm_softc->sc_ioh)) {
+ aprint_error(": can't map\n");
+ return;
+ }
+
+ for (i=1; i <= IMX51_N_DPLLS; ++i) {
+ if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0,
+ &ccm_softc->sc_pll[i-1].pll_ioh)) {
+ aprint_error(": can't map\n");
+ return;
+ }
+ }
+
+ aprint_normal(": Clock control module\n");
+ aprint_naive("\n");
+
+ imx51_get_pll_freq(1);
+ imx51_get_pll_freq(2);
+ imx51_get_pll_freq(3);
+
+
+ aprint_verbose_dev(self, "CPU clock=%d, UART clock=%d\n",
+ imx51_get_clock(IMX51CLK_ARM_ROOT),
+ imx51_get_clock(IMX51CLK_UART_CLK_ROOT));
+ aprint_verbose_dev(self,
+ "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n",
+ imx51_get_clock(IMX51CLK_MAIN_BUS_CLK),
+ imx51_get_clock(IMX51CLK_AHB_CLK_ROOT),
+ imx51_get_clock(IMX51CLK_IPG_CLK_ROOT),
+ imx51_get_clock(IMX51CLK_PERCLK_ROOT));
+}
+
+
+u_int
+imx51_get_clock(enum imx51_clock clk)
+{
+ bus_space_tag_t iot = ccm_softc->sc_iot;
+ bus_space_handle_t ioh = ccm_softc->sc_ioh;
+
+ u_int freq;
+ u_int sel;
+ uint32_t cacrr; /* ARM clock root register */
+ uint32_t ccsr;
+ uint32_t cscdr1;
+ uint32_t cscmr1;
+ uint32_t cbcdr;
+ uint32_t cbcmr;
+ uint32_t cdcr;
+
+ switch (clk) {
+ case IMX51CLK_PLL1:
+ case IMX51CLK_PLL2:
+ case IMX51CLK_PLL3:
+ return ccm_softc->sc_pll[clk-IMX51CLK_PLL1].pll_freq;
+ case IMX51CLK_PLL1SW:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0)
+ return ccm_softc->sc_pll[1-1].pll_freq;
+ /* step clock */
+ /* FALLTHROUGH */
+ case IMX51CLK_PLL1STEP:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) {
+ case 0:
+ return imx51_get_clock(IMX51CLK_LP_APM);
+ case 1:
+ return 0; /* XXX PLL bypass clock */
+ case 2:
+ return ccm_softc->sc_pll[2-1].pll_freq /
+ (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >>
+ CCSR_PLL2_DIV_PODF_SHIFT));
+ case 3:
+ return ccm_softc->sc_pll[3-1].pll_freq /
+ (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >>
+ CCSR_PLL3_DIV_PODF_SHIFT));
+ }
+ /*NOTREACHED*/
+ case IMX51CLK_PLL2SW:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0)
+ return imx51_get_clock(IMX51CLK_PLL2);
+ return 0; /* XXX PLL2 bypass clk */
+ case IMX51CLK_PLL3SW:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0)
+ return imx51_get_clock(IMX51CLK_PLL3);
+ return 0; /* XXX PLL3 bypass clk */
+
+ case IMX51CLK_LP_APM:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ return (ccsr & CCSR_LP_APM) ?
+ imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ;
+
+ case IMX51CLK_ARM_ROOT:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW);
+ cacrr = bus_space_read_4(iot, ioh, CCMC_CACRR);
+ return freq / (cacrr + 1);
+
+ /* ... */
+ case IMX51CLK_MAIN_BUS_CLK_SRC:
+ cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+ if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0)
+ freq = imx51_get_clock(IMX51CLK_PLL2SW);
+ else {
+ freq = 0;
+ cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
+ switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >>
+ CBCMR_PERIPH_APM_SEL_SHIFT) {
+ case 0:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW);
+ break;
+ case 1:
+ freq = imx51_get_clock(IMX51CLK_PLL3SW);
+ break;
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ case 3:
+ /* XXX: error */
+ break;
+ }
+ }
+ return freq;
+ case IMX51CLK_MAIN_BUS_CLK:
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+ cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR);
+ return freq / (cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >>
+ CDCR_PERIPH_CLK_DVFS_PODF_SHIFT;
+ case IMX51CLK_AHB_CLK_ROOT:
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
+ cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+ return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >>
+ CBCDR_AHB_PODF_SHIFT));
+ case IMX51CLK_IPG_CLK_ROOT:
+ freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
+ cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+ return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >>
+ CBCDR_IPG_PODF_SHIFT));
+
+ case IMX51CLK_PERCLK_ROOT:
+ cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
+ if (cbcmr & CBCMR_PERCLK_IPG_SEL)
+ return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
+ if (cbcmr & CBCMR_PERCLK_LP_APM_SEL)
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ else
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+ cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+
+#ifdef IMXCCMDEBUG
+ printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
+#endif
+
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >>
+ CBCDR_PERCLK_PRED1_SHIFT);
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >>
+ CBCDR_PERCLK_PRED2_SHIFT);
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >>
+ CBCDR_PERCLK_PODF_SHIFT);
+ return freq;
+ case IMX51CLK_UART_CLK_ROOT:
+ cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
+ cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
+
+#ifdef IMXCCMDEBUG
+ printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1);
+#endif
+
+ sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >>
+ CSCMR1_UART_CLK_SEL_SHIFT;
+
+ freq = 0; /* shut up GCC */
+ switch (sel) {
+ case 0:
+ case 1:
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
+ break;
+ case 3:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ }
+
+ return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >>
+ CSCDR1_UART_CLK_PRED_SHIFT)) /
+ (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >>
+ CSCDR1_UART_CLK_PODF_SHIFT));
+ case IMX51CLK_IPU_HSP_CLK_ROOT:
+ freq = 0;
+ cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
+ switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >>
+ CBCMR_IPU_HSP_CLK_SEL_SHIFT) {
+ case 0:
+ freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK);
+ break;
+ case 1:
+ freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK);
+ break;
+ case 2:
+ freq = imx51_get_clock(
+ IMX51CLK_EMI_SLOW_CLK_ROOT);
+ break;
+ case 3:
+ freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
+ break;
+ }
+ return freq;
+ default:
+ aprint_error_dev(ccm_softc->sc_dev,
+ "clock %d: not supported yet\n", clk);
+ return 0;
+ }
+}
+
+
+static uint64_t
+imx51_get_pll_freq(u_int pll_no)
+{
+ uint32_t dp_ctrl;
+ uint32_t dp_op;
+ uint32_t dp_mfd;
+ uint32_t dp_mfn;
+ uint32_t mfi;
+ int32_t mfn;
+ uint32_t mfd;
+ uint32_t pdf;
+ uint32_t ccr;
+ uint64_t freq = 0;
+ u_int ref = 0;
+ bus_space_tag_t iot = ccm_softc->sc_iot;
+ bus_space_handle_t ioh = ccm_softc->sc_pll[pll_no-1].pll_ioh;
+
+ KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS);
+
+ dp_ctrl = bus_space_read_4(iot, ioh, DPLL_DP_CTL);
+
+ if (dp_ctrl & DP_CTL_HFSM) {
+ dp_op = bus_space_read_4(iot, ioh, DPLL_DP_HFS_OP);
+ dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFD);
+ dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFN);
+ } else {
+ dp_op = bus_space_read_4(iot, ioh, DPLL_DP_OP);
+ dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_MFD);
+ dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_MFN);
+ }
+
+ pdf = dp_op & DP_OP_PDF_MASK;
+ mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT);
+ mfd = dp_mfd;
+ if (dp_mfn & __BIT(26))
+ /* 27bit signed value */
+ mfn = (int32_t)(__BITS(31,27) | dp_mfn);
+ else
+ mfn = dp_mfn;
+
+ switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) {
+ case DP_CTL_REF_CLK_SEL_COSC:
+ /* Internal Oscillator */
+ ref = IMX51_OSC_FREQ;
+ break;
+ case DP_CTL_REF_CLK_SEL_FPM:
+ ccr = bus_space_read_4(iot, ccm_softc->sc_ioh, CCMC_CCR);
+ if (ccr & CCR_FPM_MULT)
+ ref = IMX51_CKIL_FREQ * 1024;
+ else
+ ref = IMX51_CKIL_FREQ * 512;
+ break;
+ default:
+ ref = 0;
+ }
+
+
+ if (dp_ctrl & DP_CTL_REF_CLK_DIV)
+ ref /= 2;
+
+#if 0
+ if (dp_ctrl & DP_CTL_DPDCK0_2_EN)
+ ref *= 2;
+
+ ref /= (pdf + 1);
+ freq = ref * mfn;
+ freq /= (mfd + 1);
+ freq = (ref * mfi) + freq;
+#endif
+
+ ref *= 4;
+ freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1);
+ freq /= pdf + 1;
+
+ if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN))
+ freq /= 2;
+
+
+#ifdef IMXCCMDEBUG
+ printf("dp_ctl: %08x ", dp_ctrl);
+ printf("pdf: %3d ", pdf);
+ printf("mfi: %3d ", mfi);
+ printf("mfd: %3d ", mfd);
+ printf("mfn: %3d ", mfn);
+ printf("pll: %lld\n", freq);
+#endif
+
+ ccm_softc->sc_pll[pll_no-1].pll_freq = freq;
+
+ return freq;
+}
+
+void
+imx51_clk_gating(int clk_src, int mode)
+{
+ bus_space_tag_t iot = ccm_softc->sc_iot;
+ bus_space_handle_t ioh = ccm_softc->sc_ioh;
+ uint32_t group = CCMR_CCGR_MODULE(clk_src);
+ uint32_t field = clk_src % CCMR_CCGR_NSOURCE;
+ uint32_t reg;
+ uint32_t bit;
+
+ bit = (mode << field * 2);
+ reg = bus_space_read_4(iot, ioh, CCMC_CCGR(group));
+ reg &= ~(0x03 << field * 2);
+ reg |= bit;
+ bus_space_write_4(iot, ioh, CCMC_CCGR(group), reg);
+}
Index: src/sys/arch/arm/imx/imx51_ccmreg.h
diff -u /dev/null src/sys/arch/arm/imx/imx51_ccmreg.h:1.1
--- /dev/null Tue Apr 17 09:33:31 2012
+++ src/sys/arch/arm/imx/imx51_ccmreg.h Tue Apr 17 09:33:31 2012
@@ -0,0 +1,199 @@
+/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _IMX51_CCMREG_H
+#define _IMX51_CCMREG_H
+
+#include <sys/cdefs.h>
+
+/* register offset address */
+
+#define CCMC_BASE 0x73fd4000
+#define CCMC_CCR 0x0000
+#define CCR_FPM_MULT __BIT(12)
+#define CCMC_CCDR 0x0004
+#define CCMC_CSR 0x0008
+#define CCMC_CCSR 0x000c
+#define CCSR_LP_APM __BIT(9)
+#define CCSR_STEP_SEL_SHIFT 7
+#define CCSR_STEP_SEL_MASK __BITS(8,CCSR_STEP_SEL_SHIFT)
+#define CCSR_PLL2_DIV_PODF_SHIFT 5
+#define CCSR_PLL2_DIV_PODF_MASK __BITS(6, CCSR_PLL2_DIV_PODF_SHIFT)
+#define CCSR_PLL3_DIV_PODF_SHIFT 3
+#define CCSR_PLL3_DIV_PODF_MASK __BITS(4, CCSR_PLL2_DIV_PODF_SHIFT)
+#define CCSR_PLL1_SW_CLK_SEL __BIT(2)
+#define CCSR_PLL2_SW_CLK_SEL __BIT(1)
+#define CCSR_PLL3_SW_CLK_SEL __BIT(0)
+#define CCMC_CACRR 0x0010
+#define CCMC_CBCDR 0x0014
+#define CBCDR_DDR_HIGH_FREQ_CLK_SEL __BIT(30)
+#define CBCDR_DDR_CLK_PODF_SHIFT 27
+#define CBCDR_DDR_CLK_PODF_MASK __BITS(29, CBCDR_DDR_CLK_PODF_SHIFT)
+#define CBCDR_EMI_CLK_SEL __BIT(26)
+#define CBCDR_PERIPH_CLK_SEL __BIT(25)
+#define CBCDR_EMI_SLOW_PODF_SHIFT 22
+#define CBCDR_EMI_SLOW_PODF_MASK __BITS(24, CBCDR_EMI_SLOW_PODF_SHIFT)
+#define CBCDR_AXI_B_PODF_SHIFT 19
+#define CBCDR_AXI_B_PODF_MASK __BITS(21, CBCDR_AXI_B_PODF_SHIFT)
+#define CBCDR_AXI_A_PODF_SHIFT 16
+#define CBCDR_AXI_A_PODF_MASK __BITS(28, CBCDR_AXI_A_PODF_SHIFT)
+#define CBCDR_NFC_PODF_SHIFT 13
+#define CBCDR_NFC_PODF_MASK __BITS(15, CBCDR_AXI_A_PODF_SHIFT)
+#define CBCDR_AHB_PODF_SHIFT 10
+#define CBCDR_AHB_PODF_MASK __BITS(12, CBCDR_AHB_PODF_SHIFT)
+#define CBCDR_IPG_PODF_SHIFT 8
+#define CBCDR_IPG_PODF_MASK __BITS(9, CBCDR_IPG_PODF_SHIFT)
+#define CBCDR_PERCLK_PRED1_SHIFT 6
+#define CBCDR_PERCLK_PRED1_MASK __BITS(7, CBCDR_PERCLK_PRED1_SHIFT)
+#define CBCDR_PERCLK_PRED2_SHIFT 3
+#define CBCDR_PERCLK_PRED2_MASK __BITS(5, CBCDR_PERCLK_PRED2_SHIFT)
+#define CBCDR_PERCLK_PODF_SHIFT 0
+#define CBCDR_PERCLK_PODF_MASK __BITS(2, CBCDR_PERCLK_PODF_SHIFT)
+#define CCMC_CBCMR 0x0018
+#define CBCMR_PERIPH_APM_SEL_SHIFT 12
+#define CBCMR_PERIPH_APM_SEL_MASK __BITS(13, CBCMR_PERIPH_APM_SEL_SHIFT)
+#define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6
+#define CBCMR_IPU_HSP_CLK_SEL_MASK __BITS(7, CBCMR_IPU_HSP_CLK_SEL_SHIFT)
+#define CBCMR_PERCLK_LP_APM_SEL __BIT(1)
+#define CBCMR_PERCLK_IPG_SEL __BIT(0)
+#define CCMC_CSCMR1 0x001c
+#define CSCMR1_UART_CLK_SEL_SHIFT 24
+#define CSCMR1_UART_CLK_SEL_MASK __BITS(25, CSCMR1_UART_CLK_SEL_SHIFT)
+#define CCMC_CSCMR2 0x0020
+#define CCMC_CSCDR1 0x0024
+#define CSCDR1_UART_CLK_PRED_SHIFT 3
+#define CSCDR1_UART_CLK_PRED_MASK __BITS(5, CSCDR1_UART_CLK_PRED_SHIFT)
+#define CSCDR1_UART_CLK_PODF_SHIFT 0
+#define CSCDR1_UART_CLK_PODF_MASK __BITS(2, CSCDR1_UART_CLK_PODF_SHIFT)
+#define CCMC_CS1CDR 0x0028
+#define CCMC_CS2CDR 0x002c
+#define CCMC_CDCDR 0x0030
+#define CCMC_CSCDR2 0x0038
+#define CCMC_CSCDR3 0x003c
+#define CCMC_CSCDR4 0x0040
+#define CCMC_CWDR 0x0044
+#define CCMC_CDHIPR 0x0048
+#define CCMC_CDCR 0x004c
+#define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0
+#define CDCR_PERIPH_CLK_DVFS_PODF_MASK \
+ __BITS(1,CDCR_PERIPH_CLK_DVFS_PODF_SHIFT)
+#define CCMC_CTOR 0x0050
+#define CCMC_CLPCR 0x0054
+#define CCMC_CISR 0x0058
+#define CCMC_CIMR 0x005c
+#define CCMC_CCOSR 0x0060
+#define CCMC_CGPR 0x0064
+#define CCMC_CCGR(n) (0x0068 + (n) * 4)
+#define CCMC_CMEOR 0x0084
+
+#define CCMC_SIZE 0x88
+
+/* CCGR Clock Gate Register */
+
+#define CCMR_CCGR_NSOURCE 16
+#define CCMR_CCGR_NGROUPS 7
+#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE)
+#define __CCGR_NUM(a, b) ((a) * 16 + (b))
+
+#define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0)
+#define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1)
+#define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2)
+#define CCGR_TZIC_CLK __CCGR_NUM(0, 3)
+#define CCGR_DAP_CLK __CCGR_NUM(0, 4)
+#define CCGR_TPIU_CLK __CCGR_NUM(0, 5)
+#define CCGR_CTI2_CLK __CCGR_NUM(0, 6)
+#define CCGR_CTI3_CLK __CCGR_NUM(0, 7)
+#define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8)
+#define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9)
+#define CCGR_ROMCP_CLK __CCGR_NUM(0, 10)
+#define CCGR_ROM_CLK __CCGR_NUM(0, 11)
+#define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12)
+#define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13)
+#define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14)
+#define CCGR_IIM_CLK __CCGR_NUM(0, 15)
+#define CCGR_TMAX1_CLK __CCGR_NUM(1, 0)
+#define CCGR_TMAX2_CLK __CCGR_NUM(1, 1)
+#define CCGR_TMAX3_CLK __CCGR_NUM(1, 2)
+#define CCGR_UART1_CLK __CCGR_NUM(1, 3)
+#define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4)
+#define CCGR_UART2_CLK __CCGR_NUM(1, 5)
+#define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6)
+#define CCGR_UART3_CLK __CCGR_NUM(1, 7)
+#define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8)
+#define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9)
+#define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10)
+#define CCGR_HSI2C_CLK __CCGR_NUM(1, 11)
+#define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12)
+#define CCGR_FIRI_CLK __CCGR_NUM(1, 13)
+#define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14)
+#define CCGR_SCC_CLK __CCGR_NUM(1, 15)
+#define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0)
+#define CCGR_EPIT1_CLK __CCGR_NUM(2, 1)
+#define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2)
+#define CCGR_EPIT2_CLK __CCGR_NUM(2, 3)
+#define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0)
+#define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1)
+#define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2)
+#define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3)
+#define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4)
+#define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5)
+#define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6)
+#define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7)
+#define CCGR_SSI1_CLK __CCGR_NUM(3, 8)
+#define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9)
+#define CCGR_SSI2_CLK __CCGR_NUM(3, 10)
+#define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11)
+#define CCGR_SSI3_CLK __CCGR_NUM(3, 12)
+#define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13)
+#define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14)
+#define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15)
+#define CCGR_PATA_CLK __CCGR_NUM(4, 0)
+#define CCGR_SIM_CLK __CCGR_NUM(4, 1)
+#define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2)
+#define CCGR_SAHARA_CLK __CCGR_NUM(4, 3)
+#define CCGR_RTIC_CLK __CCGR_NUM(4, 4)
+#define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5)
+#define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6)
+#define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7)
+#define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8)
+#define CCGR_CSPI_CLK __CCGR_NUM(4, 9)
+#define CCGR_SRTC_CLK __CCGR_NUM(4, 10)
+#define CCGR_SDMA_CLK __CCGR_NUM(4, 11)
+#define CCGR_SPBA_CLK __CCGR_NUM(5, 0)
+#define CCGR_GPU_CLK __CCGR_NUM(5, 1)
+#define CCGR_GARB_CLK __CCGR_NUM(5, 2)
+#define CCGR_VPU_CLK __CCGR_NUM(5, 3)
+#define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4)
+#define CCGR_IPU_CLK __CCGR_NUM(5, 5)
+#define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0)
+#define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1)
+#define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2)
+#define CCGR_GPU2D_CLK __CCGR_NUM(6, 3)
+#define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4)
+#define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5)
+
+#endif /* _IMX51_CCMREG_H */
+
Index: src/sys/arch/arm/imx/imx51_ccmvar.h
diff -u /dev/null src/sys/arch/arm/imx/imx51_ccmvar.h:1.1
--- /dev/null Tue Apr 17 09:33:31 2012
+++ src/sys/arch/arm/imx/imx51_ccmvar.h Tue Apr 17 09:33:31 2012
@@ -0,0 +1,78 @@
+/* $NetBSD: imx51_ccmvar.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_IMX_IMX51_CCMVAR_H_
+#define _ARM_IMX_IMX51_CCMVAR_H_
+
+enum imx51_clock {
+ IMX51CLK_FPM,
+ IMX51CLK_PLL1,
+ IMX51CLK_PLL2,
+ IMX51CLK_PLL3,
+ IMX51CLK_PLL1SW,
+ IMX51CLK_PLL2SW,
+ IMX51CLK_PLL3SW,
+ IMX51CLK_PLL1STEP,
+ IMX51CLK_LP_APM,
+ IMX51CLK_ARM_ROOT,
+ IMX51CLK_MAIN_BUS_CLK_SRC, /* XXX */
+ IMX51CLK_MAIN_BUS_CLK,
+ IMX51CLK_EMI_SLOW_CLK_ROOT,
+ IMX51CLK_ENFC_CLK_ROOT,
+ IMX51CLK_AHB_CLK_ROOT,
+ IMX51CLK_IPG_CLK_ROOT,
+ IMX51CLK_PERCLK_ROOT,
+ IMX51CLK_DDR_CLK_ROOT,
+ IMX51CLK_ARM_AXI_CLK_ROOT,
+ IMX51CLK_ARM_AXI_A_CLK,
+ IMX51CLK_ARM_AXI_B_CLK,
+ IMX51CLK_IPU_HSP_CLK_ROOT,
+ IMX51CLK_CKIL_SYNC_CLK_ROOT,
+ IMX51CLK_USBOH3_CLK_ROOT,
+ IMX51CLK_ESDHC1_CLK_ROOT,
+ IMX51CLK_ESDHC2_CLK_ROOT,
+ IMX51CLK_ESDHC3_CLK_ROOT,
+ IMX51CLK_UART_CLK_ROOT,
+ IMX51CLK_SSI1_CLK_ROOT,
+ IMX51CLK_SSI2_CLK_ROOT,
+ IMX51CLK_SSI_EXT1_CLK_ROOT,
+ IMX51CLK_SSI_EXT2_CLK_ROOT,
+ IMX51CLK_USB_PHY_CLK_ROOT,
+ IMX51CLK_TVE_216_54_CLK_ROOT,
+ IMX51CLK_DI_CLK_ROOT,
+ IMX51CLK_SPDIF0_CLK_ROOT,
+ IMX51CLK_SPDIF1_CLK_ROOT,
+ IMX51CLK_CSPI_CLK_ROOT,
+ IMX51CLK_WRCK_CLK_ROOT,
+ IMX51CLK_LPSR_CLK_ROOT,
+ IMX51CLK_PGC_CLK_ROOT
+};
+
+u_int imx51_get_clock(enum imx51_clock);
+void imx51_clk_gating(int, int);
+
+#endif /* _ARM_IMX_IMX51_CCMVAR_H_ */
Index: src/sys/arch/arm/imx/imx51_dpllreg.h
diff -u /dev/null src/sys/arch/arm/imx/imx51_dpllreg.h:1.1
--- /dev/null Tue Apr 17 09:33:31 2012
+++ src/sys/arch/arm/imx/imx51_dpllreg.h Tue Apr 17 09:33:31 2012
@@ -0,0 +1,62 @@
+/* $NetBSD: imx51_dpllreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _IMX51_DPLLREG_H
+#define _IMX51_DPLLREG_H
+
+#include <sys/cdefs.h>
+
+/* register offset address */
+
+#define IMX51_N_DPLLS 3 /* 1..3 */
+
+#define DPLL_BASE(n) (0x83F80000 + (0x4000 * ((n)-1)))
+#define DPLL_SIZE 0x100
+
+#define DPLL_DP_CTL 0x0000
+#define DP_CTL_HFSM __BIT(7)
+#define DP_CTL_REF_CLK_SEL_MASK __BITS(8,9)
+#define DP_CTL_REF_CLK_SEL_COSC (__BIT(9)|0)
+#define DP_CTL_REF_CLK_SEL_FPM (__BIT(9)|__BIT(8))
+#define DP_CTL_REF_CLK_DIV __BIT(10)
+#define DP_CTL_DPDCK0_2_EN __BIT(12)
+#define DPLL_DP_CONFIG 0x0004
+#define DPLL_DP_OP 0x0008
+#define DP_OP_PDF_SHIFT 0
+#define DP_OP_PDF_MASK (0xf << DP_OP_PDF_SHIFT)
+#define DP_OP_MFI_SHIFT 4
+#define DP_OP_MFI_MASK (0xf << DP_OP_MFI_SHIFT)
+#define DPLL_DP_MFD 0x000C
+#define DPLL_DP_MFN 0x0010
+#define DPLL_DP_MFNMINUS 0x0014
+#define DPLL_DP_MFNPLUS 0x0018
+#define DPLL_DP_HFS_OP 0x001C
+#define DPLL_DP_HFS_MFD 0x0020
+#define DPLL_DP_HFS_MFN 0x0024
+#define DPLL_DP_TOGC 0x0028
+#define DPLL_DP_DESTAT 0x002C
+
+#endif /* _IMX51_DPLLREG_H */
