Module Name: src
Committed By: matt
Date: Sun Jul 15 08:44:57 UTC 2012
Modified Files:
src/sys/arch/evbppc/conf: files.mpc85xx
src/sys/arch/evbppc/mpc85xx: machdep.c
src/sys/arch/powerpc/booke: e500_intr.c
src/sys/arch/powerpc/booke/dev: pq3etsec.c pq3gpio.c
src/sys/arch/powerpc/include/booke: e500reg.h openpicreg.h spr.h
Added Files:
src/sys/arch/evbppc/conf: INSTALL_TWRP1025 INSTALL_TWRP1025.MP TWRP1025
TWRP1025.MP
Log Message:
Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbppc/conf/INSTALL_TWRP1025 \
src/sys/arch/evbppc/conf/INSTALL_TWRP1025.MP \
src/sys/arch/evbppc/conf/TWRP1025 src/sys/arch/evbppc/conf/TWRP1025.MP
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbppc/conf/files.mpc85xx
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/evbppc/mpc85xx/machdep.c
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/powerpc/booke/e500_intr.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/powerpc/booke/dev/pq3etsec.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/powerpc/booke/dev/pq3gpio.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/powerpc/include/booke/e500reg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/powerpc/include/booke/openpicreg.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/powerpc/include/booke/spr.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbppc/conf/files.mpc85xx
diff -u src/sys/arch/evbppc/conf/files.mpc85xx:1.8 src/sys/arch/evbppc/conf/files.mpc85xx:1.9
--- src/sys/arch/evbppc/conf/files.mpc85xx:1.8 Mon Jul 9 17:36:55 2012
+++ src/sys/arch/evbppc/conf/files.mpc85xx Sun Jul 15 08:44:56 2012
@@ -1,9 +1,9 @@
-# $NetBSD: files.mpc85xx,v 1.8 2012/07/09 17:36:55 matt Exp $
+# $NetBSD: files.mpc85xx,v 1.9 2012/07/15 08:44:56 matt Exp $
#
# mpc85xx-specific configuration info
defflag opt_mpc85xx.h MPC8536 MPC8544 MPC8548 MPC8555 MPC8568 MPC8572
- P2020 CADMUS PIXIS E500_WDOG_STACK
+ P1025 P2020 CADMUS PIXIS E500_WDOG_STACK
defparam opt_mpc85xx.h SYS_CLK MEMSIZE
file arch/evbppc/mpc85xx/autoconf.c
Index: src/sys/arch/evbppc/mpc85xx/machdep.c
diff -u src/sys/arch/evbppc/mpc85xx/machdep.c:1.24 src/sys/arch/evbppc/mpc85xx/machdep.c:1.25
--- src/sys/arch/evbppc/mpc85xx/machdep.c:1.24 Sat Jul 7 08:06:51 2012
+++ src/sys/arch/evbppc/mpc85xx/machdep.c Sun Jul 15 08:44:56 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.24 2012/07/07 08:06:51 skrll Exp $ */
+/* $NetBSD: machdep.c,v 1.25 2012/07/15 08:44:56 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -205,12 +205,15 @@ static struct consdev e500_earlycons = {
*/
static const struct cpunode_locators mpc8548_cpunode_locs[] = {
{ "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */
- { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
-#if defined(MPC8572) || defined(P2020)
+ { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1025v1 >> 16 } },
+#if defined(MPC8572) || defined(P2020) || defined(P1025)
{ "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */
- { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
+ { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1025v1 >> 16 } },
{ "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */
- { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
+ { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1025v1 >> 16 } },
#endif
{ "wdog" }, /* not a real device */
{ "duart", DUART1_BASE, 2*DUART_SIZE, 0,
@@ -219,12 +222,14 @@ static const struct cpunode_locators mpc
{ "tsec", ETSEC1_BASE, ETSEC_SIZE, 1,
3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR },
1 + ilog2(DEVDISR_TSEC1) },
-#if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020)
+#if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \
+ || defined(P2020) || defined(P1025)
{ "tsec", ETSEC2_BASE, ETSEC_SIZE, 2,
3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR },
1 + ilog2(DEVDISR_TSEC2),
{ SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16,
- SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
+ SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1025v1 >> 16 } },
#endif
#if defined(MPC8544) || defined(MPC8536)
{ "tsec", ETSEC3_BASE, ETSEC_SIZE, 2,
@@ -232,12 +237,12 @@ static const struct cpunode_locators mpc
1 + ilog2(DEVDISR_TSEC3),
{ SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } },
#endif
-#if defined(MPC8548) || defined(MPC8572) || defined(P2020)
+#if defined(MPC8548) || defined(MPC8572) || defined(P1025) || defined(P2020)
{ "tsec", ETSEC3_BASE, ETSEC_SIZE, 3,
3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR },
1 + ilog2(DEVDISR_TSEC3),
{ SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16,
- SVR_P2020v2 >> 16 } },
+ SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 } },
#endif
#if defined(MPC8548) || defined(MPC8572)
{ "tsec", ETSEC4_BASE, ETSEC_SIZE, 4,
@@ -308,25 +313,29 @@ static const struct cpunode_locators mpc
1 + ilog2(DEVDISR_PCI2),
{ SVR_MPC8548v1 >> 16 }, },
#endif
-#if defined(MPC8572) || defined(P2020)
+#if defined(MPC8572) || defined(P1025) || defined(P2020)
{ "pcie", PCIE1_BASE, PCI_SIZE, 1,
1, { ISOURCE_PCIEX },
1 + ilog2(DEVDISR_PCIE),
- { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
+ { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1025v1 >> 16 } },
{ "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2,
1, { ISOURCE_PCIEX2 },
1 + ilog2(DEVDISR_PCIE2),
- { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
+ { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1025v1 >> 16 } },
{ "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3,
1, { ISOURCE_PCIEX3_MPC8572 },
1 + ilog2(DEVDISR_PCIE3),
- { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } },
+ { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1025v1 >> 16 } },
#endif
-#if defined(MPC8536) || defined(P2020)
+#if defined(MPC8536) || defined(P1025) || defined(P2020)
{ "ehci", USB1_BASE, USB_SIZE, 1,
1, { ISOURCE_USB1 },
1 + ilog2(DEVDISR_USB1),
- { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } },
+ { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16,
+ SVR_P1025v1 >> 16 } },
#endif
#ifdef MPC8536
{ "ehci", USB2_BASE, USB_SIZE, 2,
@@ -354,15 +363,15 @@ static const struct cpunode_locators mpc
1 + ilog2(DEVDISR_ESDHC_12),
{ SVR_MPC8536v1 >> 16 }, },
#endif
-#if defined(P2020)
+#if defined(P1025) || defined(P2020)
{ "spi", SPI_BASE, SPI_SIZE, 0,
1, { ISOURCE_SPI },
1 + ilog2(DEVDISR_SPI_28),
- { SVR_P2020v2 >> 16 }, },
+ { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, },
{ "sdhc", ESDHC_BASE, ESDHC_SIZE, 0,
1, { ISOURCE_ESDHC },
1 + ilog2(DEVDISR_ESDHC_10),
- { SVR_P2020v2 >> 16 }, },
+ { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, },
#endif
//{ "sec", RNG_BASE, RNG_SIZE, 0, 0, },
{ NULL }
@@ -611,6 +620,7 @@ getsvr(void)
case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16;
case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16;
case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16;
+ case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16;
default: return svr;
}
}
@@ -634,6 +644,8 @@ socname(uint32_t svr)
case SVR_MPC8572v1 >> 8: return "MPC8572";
case SVR_P2020v2 >> 8: return "P2020";
case SVR_P2010v2 >> 8: return "P2010";
+ case SVR_P1016v1 >> 8: return "P1016";
+ case SVR_P1025v1 >> 8: return "P1025";
default:
panic("%s: unknown SVR %#x", __func__, svr);
}
@@ -1364,10 +1376,13 @@ cpu_startup(void)
IST_LEVEL, 0, 1, 2, 3);
break;
#endif
-#if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020)
+#if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \
+ || defined(P1025) || defined(P2020)
case SVR_MPC8536v1 >> 16:
case SVR_MPC8544v1 >> 16:
case SVR_MPC8572v1 >> 16:
+ case SVR_P1016v1 >> 16:
+ case SVR_P1025v1 >> 16:
case SVR_P2010v2 >> 16:
case SVR_P2020v2 >> 16:
mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL,
Index: src/sys/arch/powerpc/booke/e500_intr.c
diff -u src/sys/arch/powerpc/booke/e500_intr.c:1.18 src/sys/arch/powerpc/booke/e500_intr.c:1.19
--- src/sys/arch/powerpc/booke/e500_intr.c:1.18 Mon Jul 9 11:40:19 2012
+++ src/sys/arch/powerpc/booke/e500_intr.c Sun Jul 15 08:44:56 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: e500_intr.c,v 1.18 2012/07/09 11:40:19 matt Exp $ */
+/* $NetBSD: e500_intr.c,v 1.19 2012/07/15 08:44:56 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,7 +39,7 @@
#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.18 2012/07/09 11:40:19 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.19 2012/07/15 08:44:56 matt Exp $");
#include <sys/param.h>
#include <sys/proc.h>
@@ -319,6 +319,30 @@ const struct e500_intr_name mpc8572_onch
INTR_INFO_DECL(mpc8572, MPC8572);
#endif
+
+#ifdef P1025
+#define p1025_external_intr_names default_external_intr_names
+const struct e500_intr_name p1025_onchip_intr_names[] = {
+ { ISOURCE_PCIEX3_MPC8572, "pcie3" },
+ { ISOURCE_ETSEC1_G1_TX, "etsec1-g1-tx" },
+ { ISOURCE_ETSEC1_G1_RX, "etsec1-g1-rx" },
+ { ISOURCE_ETSEC1_G1_ERR, "etsec1-g1-error" },
+ { ISOURCE_ETSEC2_G1_TX, "etsec2-g1-tx" },
+ { ISOURCE_ETSEC2_G1_RX, "etsec2-g1-rx" },
+ { ISOURCE_ETSEC2_G1_ERR, "etsec2-g1-error" },
+ { ISOURCE_ETSEC3_G1_TX, "etsec3-g1-tx" },
+ { ISOURCE_ETSEC3_G1_RX, "etsec3-g1-rx" },
+ { ISOURCE_ETSEC3_G1_ERR, "etsec3-g1-error" },
+ { ISOURCE_DMA2_CHAN1, "dma2-chan1" },
+ { ISOURCE_DMA2_CHAN2, "dma2-chan2" },
+ { ISOURCE_DMA2_CHAN3, "dma2-chan3" },
+ { ISOURCE_DMA2_CHAN4, "dma2-chan4" },
+ { 0, "" },
+};
+
+INTR_INFO_DECL(p1025, P1025);
+#endif
+
#ifdef P2020
#define p20x0_external_intr_names default_external_intr_names
const struct e500_intr_name p20x0_onchip_intr_names[] = {
@@ -1013,6 +1037,12 @@ e500_intr_init(void)
*ii = mpc8572_intr_info;
break;
#endif
+#ifdef P1025
+ case SVR_P1016v1 >> 16:
+ case SVR_P1025v1 >> 16:
+ *ii = p1025_intr_info;
+ break;
+#endif
#ifdef P2020
case SVR_P2010v2 >> 16:
case SVR_P2020v2 >> 16:
Index: src/sys/arch/powerpc/booke/dev/pq3etsec.c
diff -u src/sys/arch/powerpc/booke/dev/pq3etsec.c:1.13 src/sys/arch/powerpc/booke/dev/pq3etsec.c:1.14
--- src/sys/arch/powerpc/booke/dev/pq3etsec.c:1.13 Mon May 7 23:04:22 2012
+++ src/sys/arch/powerpc/booke/dev/pq3etsec.c Sun Jul 15 08:44:56 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: pq3etsec.c,v 1.13 2012/05/07 23:04:22 matt Exp $ */
+/* $NetBSD: pq3etsec.c,v 1.14 2012/07/15 08:44:56 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -38,7 +38,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.13 2012/05/07 23:04:22 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.14 2012/07/15 08:44:56 matt Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -693,8 +693,6 @@ pq3etsec_ifinit(struct ifnet *ifp)
struct pq3etsec_softc * const sc = ifp->if_softc;
int error = 0;
- KASSERT(!cpu_softintr_p());
-
sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES);
if (ifp->if_mtu > ETHERMTU_JUMBO)
return error;
@@ -1134,7 +1132,7 @@ pq3etsec_mapcache_destroy(
for (u_int i = 0; i < dmc->dmc_maxmaps; i++) {
bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]);
}
- kmem_free(dmc, dmc_size);
+ kmem_intr_free(dmc, dmc_size);
}
static int
@@ -1147,7 +1145,8 @@ pq3etsec_mapcache_create(
{
const size_t dmc_size =
offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]);
- struct pq3etsec_mapcache * const dmc = kmem_zalloc(dmc_size, KM_SLEEP);
+ struct pq3etsec_mapcache * const dmc =
+ kmem_intr_zalloc(dmc_size, KM_NOSLEEP);
dmc->dmc_maxmaps = maxmaps;
dmc->dmc_nmaps = maxmaps;
@@ -1167,7 +1166,7 @@ pq3etsec_mapcache_create(
bus_dmamap_destroy(sc->sc_dmat,
dmc->dmc_maps[i]);
}
- kmem_free(dmc, dmc_size);
+ kmem_intr_free(dmc, dmc_size);
return error;
}
KASSERT(dmc->dmc_maps[i] != NULL);
Index: src/sys/arch/powerpc/booke/dev/pq3gpio.c
diff -u src/sys/arch/powerpc/booke/dev/pq3gpio.c:1.7 src/sys/arch/powerpc/booke/dev/pq3gpio.c:1.8
--- src/sys/arch/powerpc/booke/dev/pq3gpio.c:1.7 Sat May 19 00:11:46 2012
+++ src/sys/arch/powerpc/booke/dev/pq3gpio.c Sun Jul 15 08:44:56 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: pq3gpio.c,v 1.7 2012/05/19 00:11:46 matt Exp $ */
+/* $NetBSD: pq3gpio.c,v 1.8 2012/07/15 08:44:56 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -41,7 +41,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.7 2012/05/19 00:11:46 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.8 2012/07/15 08:44:56 matt Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -109,6 +109,58 @@ pq3gpio_null_pin_ctl(void *v, int num, i
}
#endif
+#if defined(P1025)
+/*
+ * P1025 has controllable input/output pins
+ */
+static void
+pq3gpio_pin_ctl(void *v, int num, int ctl)
+{
+ struct pq3gpio_group * const gc = v;
+ const size_t shift = gc->gc_pins[num].pin_num ^ 31;
+
+ uint64_t old_dir =
+ ((uint64_t)bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR1) << 32)
+ | (bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR2) << 0);
+
+ uint32_t dir = 0;
+ switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
+ case GPIO_PIN_INPUT|GPIO_PIN_OUTPUT: dir = CPDIR_INOUT; break;
+ case GPIO_PIN_OUTPUT: dir = CPDIR_OUT; break;
+ case GPIO_PIN_INPUT: dir = CPDIR_INOUT; break;
+ case 0: dir = CPDIR_DIS; break;
+ }
+
+ uint64_t new_dir = (old_dir & (3ULL << (2 * shift)))
+ | ((uint64_t)dir << (2 * shift));
+
+ if ((uint32_t)old_dir != (uint32_t)new_dir)
+ bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR2,
+ (uint32_t)new_dir);
+ new_dir >>= 32;
+ old_dir >>= 32;
+ if ((uint32_t)old_dir != (uint32_t)new_dir)
+ bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR1,
+ (uint32_t)new_dir);
+
+ /*
+ * Now handle opendrain
+ */
+ uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPODR);
+ uint32_t new_odr = old_odr;
+ uint32_t odr_mask = 1UL << shift;
+
+ if (ctl & GPIO_PIN_OPENDRAIN) {
+ new_odr |= odr_mask;
+ } else {
+ new_odr &= ~odr_mask;
+ }
+
+ if (old_odr != new_odr)
+ bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPODR, new_odr);
+}
+#endif
+
#if defined(MPC8536) || defined(P2020)
/*
* MPC8536 / P20x0 have controllable input/output pins
@@ -327,6 +379,55 @@ pq3gpio_mpc8548_attach(device_t self, bu
}
#endif /* MPC8548 */
+#ifdef P1025
+static void
+pq3gpio_p1025_attach(device_t self, bus_space_tag_t bst,
+ bus_space_handle_t bsh, u_int svr)
+{
+ static const uint32_t gpio2pmuxcr_map[][4] = {
+ { 0, __BIT(12), 0, PMUXCR_SDHC_WP },
+ { __BIT(15), __BIT(8), 0, PMUXCR_USB1 },
+ { __BITS(14,4)|__BIT(16)|__BITS(27,17)|__BIT(30),
+ __BIT(1)|__BITS(3,2), 0, PMUXCR_QE0 },
+ { __BITS(3,1), 0, 0, PMUXCR_QE3 },
+ { 0, __BITS(17,14), 0, PMUXCR_QE8 },
+ { __BIT(29), __BITS(19,18), 0, PMUXCR_QE9 },
+ { 0, __BITS(22,21), 0, PMUXCR_QE10 },
+ { 0, __BITS(28,23), 0, PMUXCR_QE11 },
+ { 0, __BIT(20), 0, PMUXCR_QE12 },
+ };
+
+ uint32_t pinmask[3] = {
+ 0xffffffff, 0xffffffff, 0xffffffff
+ }; /* assume all bits are valid */
+ const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR);
+ for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) {
+ if (pmuxcr & gpio2pmuxcr_map[i][3]) {
+ pinmask[0] &= ~gpio2pmuxcr_map[i][0];
+ pinmask[1] &= ~gpio2pmuxcr_map[i][1];
+ pinmask[2] &= ~gpio2pmuxcr_map[i][2];
+ }
+ }
+
+ /*
+ * Create GPIO pin groups
+ */
+ for (size_t i = 0; i < 3; i++) {
+ if (pinmask[i]) {
+ bus_space_handle_t bsh2;
+ aprint_normal_dev(self,
+ "gpio[%c]: %zu input/output/opendrain pins\n",
+ "abc"[i], popcount32(pinmask[i]));
+ bus_space_subregion(bst, bsh, CPBASE(i), 0x20, &bsh2);
+ pq3gpio_group_create(self, bst, bsh2, CPDAT,
+ pinmask[0],
+ GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN,
+ pq3gpio_pin_ctl);
+ }
+ }
+}
+#endif /* P1025 */
+
#ifdef P2020
static void
pq3gpio_p20x0_attach(device_t self, bus_space_tag_t bst,
@@ -386,6 +487,10 @@ static const struct pq3gpio_svr_info {
{ SVR_MPC8536v1 >> 16, pq3gpio_mpc8536_attach,
GPIO_BASE, GPIO_SIZE },
#endif
+#ifdef P1025
+ { SVR_P1025v1 >> 16, pq3gpio_p1025_attach,
+ GLOBAL_BASE, GLOBAL_SIZE },
+#endif
#ifdef P2020
{ SVR_P2020v2 >> 16, pq3gpio_p20x0_attach,
GPIO_BASE, GPIO_SIZE },
Index: src/sys/arch/powerpc/include/booke/e500reg.h
diff -u src/sys/arch/powerpc/include/booke/e500reg.h:1.10 src/sys/arch/powerpc/include/booke/e500reg.h:1.11
--- src/sys/arch/powerpc/include/booke/e500reg.h:1.10 Tue Aug 2 00:23:34 2011
+++ src/sys/arch/powerpc/include/booke/e500reg.h Sun Jul 15 08:44:56 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: e500reg.h,v 1.10 2011/08/02 00:23:34 matt Exp $ */
+/* $NetBSD: e500reg.h,v 1.11 2012/07/15 08:44:56 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -458,9 +458,20 @@
#define PMUXCR_USB1 __PPCBIT(5)
#define PMUXCR_TSEC3_TS __PPCBIT(5)
#define PMUXCR_USB2 __PPCBIT(6)
-#define PMUXCR_USB __PPCBIT(6)
+#define PMUXCR_USB_PCTL __PPCBITS(6,5)
+#define PMUXCR_USB __PPCBIT(6)
+#define PMUXCR_TSEC1 __PPCBIT(14)
#define PMUXCR_DMA0 __PPCBIT(14)
#define PMUXCR_DMA2 __PPCBIT(15)
+#define PMUXCR_QE0 __PPCBIT(16)
+#define PMUXCR_QE1 __PPCBIT(17)
+#define PMUXCR_QE2 __PPCBIT(18)
+#define PMUXCR_QE3 __PPCBIT(19)
+#define PMUXCR_QE8 __PPCBIT(24)
+#define PMUXCR_QE9 __PPCBIT(25)
+#define PMUXCR_QE10 __PPCBIT(26)
+#define PMUXCR_QE11 __PPCBIT(27)
+#define PMUXCR_QE12 __PPCBIT(28)
#define PMUXCR_DMA1 __PPCBIT(30)
#define PMUXCR_DMA3 __PPCBIT(31)
@@ -518,6 +529,25 @@
#define PVR 0x0A0 /* Processor version register */
#define SVR 0x0A4 /* System version register */
+/* Control Pin Registers (GPIO) for P1025 */
+#define CPBASE(n) (0x100+0x20*(n)) /* Control Pin (GPIO) base */
+#define CPODR 0x0000 /* Open Drain */
+#define CPDAT 0x0004 /* Output Data */
+#define CPDIR1 0x0008 /* Direction1 */
+#define CPDIR2 0x000c /* Direction2 */
+#define CPPAR1 0x0010 /* Pin Assignment1 */
+#define CPPAR2 0x0014 /* Pin Assignment2 */
+
+#define CPDIR_DIS 0
+#define CPDIR_OUT 1
+#define CPDIR_IN 2
+#define CPDIR_INOUT 3
+
+#define CPPAR_FUNC0 0
+#define CPPAR_FUNC1 1
+#define CPPAR_FUNC2 2
+#define CPPAR_FUNC3 3
+
/* Status Registers */
#define RSTCR 0x0B0 /* Reset control register */
#define HRESET_REQ __PPCBIT(30) /* hardware reset request */
Index: src/sys/arch/powerpc/include/booke/openpicreg.h
diff -u src/sys/arch/powerpc/include/booke/openpicreg.h:1.5 src/sys/arch/powerpc/include/booke/openpicreg.h:1.6
--- src/sys/arch/powerpc/include/booke/openpicreg.h:1.5 Tue Aug 2 00:22:02 2011
+++ src/sys/arch/powerpc/include/booke/openpicreg.h Sun Jul 15 08:44:57 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: openpicreg.h,v 1.5 2011/08/02 00:22:02 matt Exp $ */
+/* $NetBSD: openpicreg.h,v 1.6 2012/07/15 08:44:57 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -275,6 +275,30 @@
+ MPC8572_TIMERSOURCES \
+ MPC8572_MISOURCES))
+#define P1025_EXTERNALSOURCES 6
+#define P1025_ONCHIPSOURCES 64
+#define P1025_ONCHIPBITMAP { 0xbd1fffff, 0x01789c18 }
+#define P1025_IPISOURCES 4
+#define P1025_TIMERSOURCES 4
+#define P1025_MISOURCES 4
+#define P1025_MSIGROUPSOURCES 8
+#define P1025_NCPUS 2
+#define P1025_SOURCES /* 102 */ \
+ (P1025_EXTERNALSOURCES \
+ + P1025_ONCHIPSOURCES \
+ + P1025_MSIGROUPSOURCES \
+ + P1025_NCPUS*(P1025_IPISOURCES \
+ + P1025_TIMERSOURCES \
+ + P1025_MISOURCES))
+#define P1016_NCPUS 1
+#define P1016_SOURCES \
+ (P1025_EXTERNALSOURCES \
+ + P1025_ONCHIPSOURCES \
+ + P1025_MSIGROUPSOURCES \
+ + P1016_NCPUS*(P1025_IPISOURCES \
+ + P1025_TIMERSOURCES \
+ + P1025_MISOURCES))
+
#define P20x0_EXTERNALSOURCES 12
#define P20x0_ONCHIPSOURCES 64
#define P20x0_ONCHIPBITMAP { 0xbd1ff7ff, 0xf17005e7 }
@@ -311,31 +335,38 @@
#define IRQ_SPURIOUS 0xffff
#define ISOURCE_L2 0
+#define ISOURCE_ERROR 0
#define ISOURCE_ECM 1
+#define ISOURCE_ETSEC1_G1_TX 1 /* P1025 */
#define ISOURCE_DDR 2
+#define ISOURCE_ETSEC1_G1_RX 2 /* P1025 */
#define ISOURCE_LBC 3
#define ISOURCE_DMA_CHAN1 4
#define ISOURCE_DMA_CHAN2 5
#define ISOURCE_DMA_CHAN3 6
#define ISOURCE_DMA_CHAN4 7
-#define ISOURCE_PCIEX3_MPC8572 8 /* MPC8572/P20x0 */
+#define ISOURCE_PCIEX3_MPC8572 8 /* MPC8572/P20x0/P1025 */
#define ISOURCE_PCI1 8 /* MPC8548/MPC8544/MPC8536/MPC8555 */
+#define ISOURCE_ETSEC1_G1_ERR 8 /* P1025 */
#define ISOURCE_PCI2 9 /* MPC8548 */
#define ISOURCE_PCIEX2 9 /* MPC8544/MPC8572/MPC8536/P20x0 */
+#define ISOURCE_ETSEC3_G1_TX 9 /* P1025 */
#define ISOURCE_PCIEX 10
+#define ISOURCE_ETSEC3_G1_RX 10 /* P1025 */
#define ISOURCE_PCIEX3 11 /* MPC8544/MPC8536 */
-#define ISOURCE_USB1 12 /* MPC8536/P20x0 */
+#define ISOURCE_ETSEC3_G1_ERR 11 /* P1025 */
+#define ISOURCE_USB1 12 /* MPC8536/P20x0/P1025 */
#define ISOURCE_ETSEC1_TX 13
#define ISOURCE_ETSEC1_RX 14
#define ISOURCE_ETSEC3_TX 15
#define ISOURCE_ETSEC3_RX 16
#define ISOURCE_ETSEC3_ERR 17
#define ISOURCE_ETSEC1_ERR 18
-#define ISOURCE_ETSEC2_TX 19 /* !MPC8544/!MPC8536 */
-#define ISOURCE_ETSEC2_RX 20 /* !MPC8544/!MPC8536 */
-#define ISOURCE_ETSEC4_TX 21 /* !MPC8544/!MPC8536/!P20x0 */
-#define ISOURCE_ETSEC4_RX 22 /* !MPC8544/!MPC8536/!P20x0 */
-#define ISOURCE_ETSEC4_ERR 23 /* !MPC8544/!MPC8536/!P20x0 */
+#define ISOURCE_ETSEC2_TX 19 /* !MPC8544/!MPC8536/!P1025 */
+#define ISOURCE_ETSEC2_RX 20 /* !MPC8544/!MPC8536/!P1025 */
+#define ISOURCE_ETSEC4_TX 21 /* !MPC8544/!MPC8536/!P20x0/!P1025 */
+#define ISOURCE_ETSEC4_RX 22 /* !MPC8544/!MPC8536/!P20x0/!P1025 */
+#define ISOURCE_ETSEC4_ERR 23 /* !MPC8544/!MPC8536/!P20x0/!P1025 */
#define ISOURCE_ETSEC2_ERR 24 /* !MPC8544/!MPC8536 */
#define ISOURCE_FEC 25 /* MPC8572 */
#define ISOURCE_SATA2 25 /* MPC8536 */
@@ -347,34 +378,35 @@
#define ISOURCE_QEB_LOW 30 /* MPC8568 */
#define ISOURCE_USB2 30 /* MPC8536 */
#define ISOURCE_GPIO 31 /* MPC8572/!MPC8548 */
-#define ISOURCE_QEB_PORT 31 /* MPC8568 */
-#define ISOURCE_SRIO_EWPU 32 /* !MPC8548&!P20x0 */
-#define ISOURCE_SRIO_ODBELL 33 /* !MPC8548&!P20x0 */
-#define ISOURCE_SRIO_IDBELL 34 /* !MPC8548&!P20x0 */
-#define ISOURCE_35 35
-#define ISOURCE_36 36
-#define ISOURCE_SRIO_OMU1 37 /* !MPC8548&!P20x0 */
-#define ISOURCE_SRIO_IMU1 38 /* !MPC8548&!P20x0 */
-#define ISOURCE_SRIO_OMU2 39 /* !MPC8548&!P20x0 */
-#define ISOURCE_SRIO_IMU2 40 /* !MPC8548&!P20x0 */
+#define ISOURCE_QEB_PORT 31 /* MPC8568/P1025 */
+#define ISOURCE_SRIO_EWPU 32 /* !MPC8548&!P20x0&!P1025 */
+#define ISOURCE_SRIO_ODBELL 33 /* !MPC8548&!P20x0&!P1025 */
+#define ISOURCE_SRIO_IDBELL 34 /* !MPC8548&!P20x0&!P1025 */
+#define ISOURCE_ETSEC2_G1_TX 35 /* P1025 */
+#define ISOURCE_ETSEC2_G1_RX 36 /* P1025 */
+#define ISOURCE_SRIO_OMU1 37 /* !MPC8548&!P20x0&!P1025 */
+#define ISOURCE_SRIO_IMU1 38 /* !MPC8548&!P20x0&!P1025 */
+#define ISOURCE_SRIO_OMU2 39 /* !MPC8548&!P20x0&!P1025 */
+#define ISOURCE_SRIO_IMU2 40 /* !MPC8548&!P20x0&!P1025 */
#define ISOURCE_PME_GENERAL 41 /* MPC8572 */
-#define ISOURCE_SECURITY2 42 /* MPC8572|MPC8536|P20x0 */
-#define ISOURCE_SPI 43 /* MPC8536|P20x0 */
+#define ISOURCE_SECURITY2 42 /* MPC8572|MPC8536|P20x0|P1025 */
+#define ISOURCE_SPI 43 /* MPC8536|P20x0|P1025 */
#define ISOURCE_QEB_IECC 43 /* MPC8568 */
#define ISOURCE_USB3 44 /* MPC8536 */
-#define ISOURCE_QEB_MUECC 44 /* MPC8568 */
+#define ISOURCE_QEB_MUECC 44 /* MPC8568|P1025 */
#define ISOURCE_TLU1 45 /* MPC8568/MPC8572 */
#define ISOURCE_46 46
-#define ISOURCE_QEB_HIGH 47 /* MPC8548 */
+#define ISOURCE_QEB_HIGH 47 /* MPC8548|P1025 */
#define ISOURCE_PME_CHAN1 48 /* MPC8572 */
#define ISOURCE_PME_CHAN2 49 /* MPC8572 */
#define ISOURCE_PME_CHAN3 50 /* MPC8572 */
#define ISOURCE_PME_CHAN4 51 /* MPC8572 */
-#define ISOURCE_ETSEC1_PTP 52 /* MPC8572|MPC8536|P20x0 */
-#define ISOURCE_ETSEC2_PTP 53 /* MPC8572|P20x0 */
-#define ISOURCE_ETSEC3_PTP 54 /* MPC8572|MPC8536|P20x0 */
+#define ISOURCE_ETSEC2_G1_ERR 51 /* P1025 */
+#define ISOURCE_ETSEC1_PTP 52 /* MPC8572|MPC8536|P20x0|P1025 */
+#define ISOURCE_ETSEC2_PTP 53 /* MPC8572|P20x0|P1025 */
+#define ISOURCE_ETSEC3_PTP 54 /* MPC8572|MPC8536|P20x0|P1025 */
#define ISOURCE_ETSEC4_PTP 55 /* MPC8572 */
-#define ISOURCE_ESDHC 56 /* MPC8536|P20x0 */
+#define ISOURCE_ESDHC 56 /* MPC8536|P20x0|P1025 */
#define ISOURCE_57 57
#define ISOURCE_SATA1 58 /* MPC8536 */
#define ISOURCE_TLU2 59 /* MPC8572 */
Index: src/sys/arch/powerpc/include/booke/spr.h
diff -u src/sys/arch/powerpc/include/booke/spr.h:1.8 src/sys/arch/powerpc/include/booke/spr.h:1.9
--- src/sys/arch/powerpc/include/booke/spr.h:1.8 Mon Jul 9 17:58:34 2012
+++ src/sys/arch/powerpc/include/booke/spr.h Sun Jul 15 08:44:57 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: spr.h,v 1.8 2012/07/09 17:58:34 matt Exp $ */
+/* $NetBSD: spr.h,v 1.9 2012/07/15 08:44:57 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -68,9 +68,11 @@
#define SVR_P1011v2 0x80e50020
#define SVR_P1012v2 0x80e50120
#define SVR_P1013v2 0x80e70020
+#define SVR_P1016v1 0x80e50310
#define SVR_P1020v2 0x80e40020
#define SVR_P1021v2 0x80e40120
#define SVR_P1022v2 0x80e60020
+#define SVR_P1025v1 0x80e40310
#define SVR_SECURITY_P(svr) (((svr) & 0x00080000) != 0)
Added files:
Index: src/sys/arch/evbppc/conf/INSTALL_TWRP1025
diff -u /dev/null src/sys/arch/evbppc/conf/INSTALL_TWRP1025:1.1
--- /dev/null Sun Jul 15 08:44:57 2012
+++ src/sys/arch/evbppc/conf/INSTALL_TWRP1025 Sun Jul 15 08:44:56 2012
@@ -0,0 +1,10 @@
+# $NetBSD: INSTALL_TWRP1025,v 1.1 2012/07/15 08:44:56 matt Exp $
+
+include "arch/evbppc/conf/TWRP1025"
+
+#ident "INSTALL_P2020RDB-$Revision: 1.1 $"
+
+include "arch/evbppc/conf/INSTALL.inc"
+
+no config netbsd-sd0a
+no config nfsnetbsd
Index: src/sys/arch/evbppc/conf/INSTALL_TWRP1025.MP
diff -u /dev/null src/sys/arch/evbppc/conf/INSTALL_TWRP1025.MP:1.1
--- /dev/null Sun Jul 15 08:44:57 2012
+++ src/sys/arch/evbppc/conf/INSTALL_TWRP1025.MP Sun Jul 15 08:44:56 2012
@@ -0,0 +1,9 @@
+# $NetBSD: INSTALL_TWRP1025.MP,v 1.1 2012/07/15 08:44:56 matt Exp $
+
+include "arch/evbppc/conf/TWRP1205.MP"
+
+#ident "INSTALL_TWRP1205.MP-$Revision: 1.1 $"
+
+include "arch/evbppc/conf/INSTALL.inc"
+
+no config nfsnetbsd
Index: src/sys/arch/evbppc/conf/TWRP1025
diff -u /dev/null src/sys/arch/evbppc/conf/TWRP1025:1.1
--- /dev/null Sun Jul 15 08:44:57 2012
+++ src/sys/arch/evbppc/conf/TWRP1025 Sun Jul 15 08:44:56 2012
@@ -0,0 +1,224 @@
+# $NetBSD: TWRP1025,v 1.1 2012/07/15 08:44:56 matt Exp $
+#
+# TWRP1025 -- everything that's currently supported
+#
+
+include "arch/evbppc/conf/std.mpc85xx"
+
+options INCLUDE_CONFIG_FILE # embed config file in kernel binary
+
+ident "TWRP1025-$Revision: 1.1 $"
+
+maxusers 32
+
+makeoptions NEED_BINARY="yes"
+makeoptions NEED_UBOOTIMAGE="yes"
+
+#options UVMHIST
+#options UVMHIST_PRINT
+
+options P1025
+options SYS_CLK=66666667
+#options HZ=1000
+
+#options SDHC_DEBUG
+
+#options INSECURE # disable kernel security levels
+#options NTP # NTP phase/frequency locked loop
+options KTRACE # system call tracing via ktrace(1)
+
+options SYSVMSG # System V message queues
+options SYSVSEM # System V semaphores
+options SYSVSHM # System V shared memory
+
+options USERCONF # userconf(4) support
+#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
+#options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
+
+# Diagnostic/debugging support options
+options DIAGNOSTIC # cheap kernel consistency checks
+options DEBUG # expensive debugging checks/support
+#options SYSCALL_DEBUG # syscall debugging
+options DDB # in-kernel debugger
+options DDB_HISTORY_SIZE=512 # enable history editing in DDB
+options TRAP_PANICWAIT
+options SYMTAB_SPACE=410000 # size for embedded symbol table
+
+makeoptions DEBUG="-g" # compile full symbol table
+
+# Compatibility options
+#options COMPAT_09 # NetBSD 0.9,
+#options COMPAT_10 # NetBSD 1.0,
+#options COMPAT_11 # NetBSD 1.1,
+#options COMPAT_12 # NetBSD 1.2,
+options COMPAT_13 # NetBSD 1.3,
+options COMPAT_14 # NetBSD 1.4,
+options COMPAT_15 # NetBSD 1.5,
+options COMPAT_16 # NetBSD 1.6,
+options COMPAT_20 # NetBSD 2.0,
+options COMPAT_30 # NetBSD 3.0,
+options COMPAT_40 # NetBSD 4.0,
+options COMPAT_50 # NetBSD 5.0 compatibility.
+options COMPAT_43 # and 4.3BSD
+#options COMPAT_386BSD_MBRPART # recognize old partition ID
+#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
+options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
+
+# File systems
+file-system FFS # UFS
+file-system EXT2FS # second extended file system (linux)
+file-system LFS # log-structured file system
+file-system MFS # memory file system
+file-system NFS # Network File System client
+file-system CD9660 # ISO 9660 + Rock Ridge file system
+file-system MSDOSFS # MS-DOS file system
+#file-system FDESC # /dev/fd
+file-system TMPFS # efficient memory file system
+file-system KERNFS # /kern
+file-system NULLFS # loopback file system
+#file-system OVERLAY # overlay file system
+#file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs)
+file-system PROCFS # /proc
+#file-system UMAPFS # NULLFS + uid and gid remapping
+#file-system UNION # union file system
+file-system PTYFS # /dev/pts/N support
+
+# File system options
+options QUOTA # legacy UFS quotas
+options QUOTA2 # new, in-filesystem UFS quotas
+options FFS_EI # FFS Endian Independent support
+options WAPBL # File system journaling support
+options NFSSERVER # Network File System server
+#options FFS_NO_SNAPSHOT # No FFS snapshot support
+options EXT2FS_SYSTEM_FLAGS # makes ext2fs file flags (append and
+ # immutable) behave as system flags.
+
+options NFS_BOOT_DHCP # Support DHCP NFS root
+
+# Networking options
+#options GATEWAY # packet forwarding
+options INET # IP + ICMP + TCP + UDP
+options INET_CSUM_COUNTERS
+options TCP_CSUM_COUNTERS
+options UDP_CSUM_COUNTERS
+#options INET6 # IPV6
+#options IPSEC # IP security
+#options IPSEC_ESP # IP security (encryption part; define w/IPSEC)
+#options IPSEC_NAT_T # IPsec NAT traversal (NAT-T)
+#options IPSEC_DEBUG # debug for IP security
+#options MROUTING # IP multicast routing
+#options PIM # Protocol Independent Multicast
+#options DIRECTED_BROADCAST # allow broadcasts through routers
+#options ISO,TPIP # OSI
+#options EON # OSI tunneling over IP
+#options NETATALK # AppleTalk networking protocols
+#options PPP_BSDCOMP # BSD-Compress compression support for PPP
+#options PPP_DEFLATE # Deflate compression support for PPP
+#options PPP_FILTER # Active filter support for PPP (requires bpf)
+#options PFIL_HOOKS # pfil(9) packet filter hooks
+#options IPFILTER_LOG # ipmon(8) log support
+#options IPFILTER_LOOKUP # ippool(8) support
+#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
+
+# These options enable verbose messages for several subsystems.
+# Warning, these may compile large string tables into the kernel!
+options PCIVERBOSE # verbose PCI device autoconfig messages
+options MIIVERBOSE # verbose PHY autoconfig messages
+#options PCI_CONFIG_DUMP # verbosely dump PCI config space
+options SCSIVERBOSE # human readable SCSI error messages
+#options PCI_NETBSD_CONFIGURE # Do not rely on BIOS/whatever to configure PCI devices
+#options PCI_CONFIGURE_VERBOSE # Show PCI config information
+
+# wscons options
+#options WSEMUL_SUN # sun terminal emulation
+#options WSEMUL_VT100 # VT100 / VT220 emulation
+
+# Kernel root file system and dump configuration.
+config netbsd root on ? type ?
+config netbsd-sd0a root on sd0a type ffs
+config nfsnetbsd root on tsec0 type nfs
+
+#
+# Device configuration
+#
+
+mainbus0 at root # Processor Local Bus
+
+cpunode* at mainbus? node ?
+gpio* at gpiobus?
+
+cpu* at cpunode?
+
+obio0 at cpunode? # On-chip Peripheral Bus
+#nandfcm* at obio0 cs ? # nand flash
+#nand* at nandfcm?
+#flash* at nand?
+
+# NOR Flash
+#options NOR_VERBOSE
+cfi0 at obio0 cs 0
+nor* at cfi?
+flash* at nor? offset 0 size 0x1000000
+
+e500wdog* at cpunode? # Watchdog timer
+
+ddrc* at cpunode?
+duart* at cpunode?
+com* at duart? port ?
+options CONSADDR="DUART1_BASE"
+
+tsec0 at cpunode? flags 0x002 # Enhanced 3-Speed Ethernet Controller
+tsec1 at cpunode? flags 0x103 # Enhanced 3-Speed Ethernet Controller
+ukphy* at mii?
+#options ETSEC_EVENT_COUNTERS
+
+diic* at cpunode? # i2c bus
+iic* at diic?
+#dsrtc* at iic1 addr 0x68 flags 1339 # RTC DS1339
+
+pq3pcie* at cpunode? # PCI-Express controller
+pci* at pq3pcie?
+
+ppb* at pci? dev ? function ? # PCI-PCI bridges
+pci* at ppb?
+
+ahcisata* at pci? dev ? function ?
+atabus* at ahcisata? channel ?
+wd* at atabus? drive ?
+
+ehci* at cpunode? # usb
+usb* at ehci?
+uhub* at usb?
+uhub* at uhub? port ?
+umass* at uhub? port ?
+scsibus* at umass? channel ?
+sd* at scsibus? target ? lun ?
+
+sdhc* at cpunode? # sdmmc
+sdmmc* at sdhc? # SD/MMC bus
+ld* at sdmmc?
+
+#siisata* at pci? dev ? function ?
+#atabus* at siisata? channel ?
+#jmide* at pci? dev ? function ? # JMicron PCI-e PATA/SATA controllers
+#ahcisata* at jmide?
+#atabus* at ahcisata? channel ?
+
+#viaide* at pci? dev ? function ?
+#atabus* at viaide? channel ?
+#wd* at atabus? drive ?
+#rtk* at pci? dev ? function ?
+#wm* at pci? dev ? function ? # Intel Ethernet
+
+#inphy* at mii? phy ? # Intel 82555 PHYs
+#iophy* at mii? phy ? # Intel 82553 PHYs
+#makphy* at mii? phy ? # Marvell PHYs
+#ukphy* at mii? phy ? # generic unknown PHYs
+
+pseudo-device loop # network loopback
+pseudo-device bpfilter # packet filter
+pseudo-device clockctl # user control of clock subsystem
+pseudo-device ksyms # /dev/ksyms
+pseudo-device pty # pseudo-terminals
+pseudo-device kttcp # kernel ttcp
+pseudo-device vlan # 802.1Q VLANs
Index: src/sys/arch/evbppc/conf/TWRP1025.MP
diff -u /dev/null src/sys/arch/evbppc/conf/TWRP1025.MP:1.1
--- /dev/null Sun Jul 15 08:44:57 2012
+++ src/sys/arch/evbppc/conf/TWRP1025.MP Sun Jul 15 08:44:56 2012
@@ -0,0 +1,9 @@
+# $NetBSD: TWRP1025.MP,v 1.1 2012/07/15 08:44:56 matt Exp $
+#
+# TWRP1025 kernel, plus multiprocessor support.
+
+include "arch/evbppc/conf/TWRP1025"
+
+options MULTIPROCESSOR
+# this option may cause trouble under very high interrupt load
+#options OPENPIC_DISTRIBUTE # let all CPUs serve interrupts
