Module Name: src
Committed By: matt
Date: Tue Jul 17 01:36:14 UTC 2012
Modified Files:
src/sys/arch/evbppc/conf: TWRP1025
src/sys/arch/evbppc/mpc85xx: machdep.c
src/sys/arch/powerpc/booke/dev: pq3etsec.c
src/sys/arch/powerpc/include/booke: e500reg.h etsecreg.h
Log Message:
The ETSEC on the P1025 has been moved/split so the MDIO stayed in the same
place but each ETSEC has been split into two virtual halves (G0 and G1) and
each one has a new different base address.
For some reason, tsec1 connects to phy 2 and tsec2 connects to phy 1.
Adjust config file to match
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbppc/conf/TWRP1025
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/evbppc/mpc85xx/machdep.c
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/powerpc/booke/dev/pq3etsec.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/powerpc/include/booke/e500reg.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/powerpc/include/booke/etsecreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbppc/conf/TWRP1025
diff -u src/sys/arch/evbppc/conf/TWRP1025:1.1 src/sys/arch/evbppc/conf/TWRP1025:1.2
--- src/sys/arch/evbppc/conf/TWRP1025:1.1 Sun Jul 15 08:44:56 2012
+++ src/sys/arch/evbppc/conf/TWRP1025 Tue Jul 17 01:36:12 2012
@@ -1,4 +1,4 @@
-# $NetBSD: TWRP1025,v 1.1 2012/07/15 08:44:56 matt Exp $
+# $NetBSD: TWRP1025,v 1.2 2012/07/17 01:36:12 matt Exp $
#
# TWRP1025 -- everything that's currently supported
#
@@ -7,7 +7,7 @@ include "arch/evbppc/conf/std.mpc85xx"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-ident "TWRP1025-$Revision: 1.1 $"
+ident "TWRP1025-$Revision: 1.2 $"
maxusers 32
@@ -167,8 +167,8 @@ duart* at cpunode?
com* at duart? port ?
options CONSADDR="DUART1_BASE"
-tsec0 at cpunode? flags 0x002 # Enhanced 3-Speed Ethernet Controller
-tsec1 at cpunode? flags 0x103 # Enhanced 3-Speed Ethernet Controller
+tsec0 at cpunode? instance 1 flags 0x003 # Enhanced 3-Speed Ethernet Controller
+tsec1 at cpunode? instance 3 flags 0x102 # Enhanced 3-Speed Ethernet Controller
ukphy* at mii?
#options ETSEC_EVENT_COUNTERS
Index: src/sys/arch/evbppc/mpc85xx/machdep.c
diff -u src/sys/arch/evbppc/mpc85xx/machdep.c:1.25 src/sys/arch/evbppc/mpc85xx/machdep.c:1.26
--- src/sys/arch/evbppc/mpc85xx/machdep.c:1.25 Sun Jul 15 08:44:56 2012
+++ src/sys/arch/evbppc/mpc85xx/machdep.c Tue Jul 17 01:36:12 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.25 2012/07/15 08:44:56 matt Exp $ */
+/* $NetBSD: machdep.c,v 1.26 2012/07/17 01:36:12 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -221,9 +221,23 @@ static const struct cpunode_locators mpc
1 + ilog2(DEVDISR_DUART) },
{ "tsec", ETSEC1_BASE, ETSEC_SIZE, 1,
3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR },
- 1 + ilog2(DEVDISR_TSEC1) },
+ 1 + ilog2(DEVDISR_TSEC1),
+ { 0xffff, SVR_P1025v1 >> 16 } },
+#if defined(P1025)
+ { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1,
+ 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR },
+ 1 + ilog2(DEVDISR_TSEC1),
+ { SVR_P1025v1 >> 16 } },
+#if 0
+ { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1,
+ 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX,
+ ISOURCE_ETSEC1_G1_ERR },
+ 1 + ilog2(DEVDISR_TSEC1),
+ { SVR_P1025v1 >> 16 } },
+#endif
+#endif
#if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \
- || defined(P2020) || defined(P1025)
+ || defined(P2020)
{ "tsec", ETSEC2_BASE, ETSEC_SIZE, 2,
3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR },
1 + ilog2(DEVDISR_TSEC2),
@@ -231,18 +245,44 @@ static const struct cpunode_locators mpc
SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16,
SVR_P1025v1 >> 16 } },
#endif
+#if defined(P1025)
+ { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2,
+ 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR },
+ 1 + ilog2(DEVDISR_TSEC2),
+ { SVR_P1025v1 >> 16 } },
+#if 0
+ { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5,
+ 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX,
+ ISOURCE_ETSEC2_G1_ERR },
+ 1 + ilog2(DEVDISR_TSEC2),
+ { SVR_P1025v1 >> 16 } },
+#endif
+#endif
#if defined(MPC8544) || defined(MPC8536)
{ "tsec", ETSEC3_BASE, ETSEC_SIZE, 2,
3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR },
1 + ilog2(DEVDISR_TSEC3),
{ SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } },
#endif
-#if defined(MPC8548) || defined(MPC8572) || defined(P1025) || defined(P2020)
+#if defined(MPC8548) || defined(MPC8572) || defined(P2020)
{ "tsec", ETSEC3_BASE, ETSEC_SIZE, 3,
3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR },
1 + ilog2(DEVDISR_TSEC3),
{ SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16,
- SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 } },
+ SVR_P2020v2 >> 16 } },
+#endif
+#if defined(P1025)
+ { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3,
+ 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR },
+ 1 + ilog2(DEVDISR_TSEC3),
+ { SVR_P1025v1 >> 16 } },
+#if 0
+ { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3,
+ 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX,
+ ISOURCE_ETSEC3_G1_ERR },
+ 1 + ilog2(DEVDISR_TSEC3),
+ { SVR_P1025v1 >> 16 } },
+#endif
#endif
#if defined(MPC8548) || defined(MPC8572)
{ "tsec", ETSEC4_BASE, ETSEC_SIZE, 4,
Index: src/sys/arch/powerpc/booke/dev/pq3etsec.c
diff -u src/sys/arch/powerpc/booke/dev/pq3etsec.c:1.14 src/sys/arch/powerpc/booke/dev/pq3etsec.c:1.15
--- src/sys/arch/powerpc/booke/dev/pq3etsec.c:1.14 Sun Jul 15 08:44:56 2012
+++ src/sys/arch/powerpc/booke/dev/pq3etsec.c Tue Jul 17 01:36:13 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: pq3etsec.c,v 1.14 2012/07/15 08:44:56 matt Exp $ */
+/* $NetBSD: pq3etsec.c,v 1.15 2012/07/17 01:36:13 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -35,10 +35,11 @@
*/
#include "opt_inet.h"
+#include "opt_mpc85xx.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.14 2012/07/15 08:44:56 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.15 2012/07/17 01:36:13 matt Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -170,6 +171,7 @@ struct pq3etsec_softc {
struct mii_data sc_mii;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
+ bus_space_handle_t sc_mdio_bsh;
bus_dma_tag_t sc_dmat;
int sc_phy_addr;
prop_dictionary_t sc_intrmap;
@@ -303,6 +305,18 @@ etsec_write(struct pq3etsec_softc *sc, b
bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data);
}
+static inline uint32_t
+etsec_mdio_read(struct pq3etsec_softc *sc, bus_size_t off)
+{
+ return bus_space_read_4(sc->sc_bst, sc->sc_mdio_bsh, off);
+}
+
+static inline void
+etsec_mdio_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data)
+{
+ bus_space_write_4(sc->sc_bst, sc->sc_mdio_bsh, off, data);
+}
+
static int
pq3etsec_mii_readreg(device_t self, int phy, int reg)
{
@@ -311,24 +325,24 @@ pq3etsec_mii_readreg(device_t self, int
// int s = splnet();
- etsec_write(sc, MIIMADD,
+ etsec_mdio_write(sc, MIIMADD,
__SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG));
etsec_write(sc, IEVENT, IEVENT_MMRD);
- etsec_write(sc, MIIMCOM, 0); /* clear any past bits */
- etsec_write(sc, MIIMCOM, MIIMCOM_READ);
+ etsec_mdio_write(sc, MIIMCOM, 0); /* clear any past bits */
+ etsec_mdio_write(sc, MIIMCOM, MIIMCOM_READ);
#if 0
sc->sc_imask |= IEVENT_MMRD;
etsec_write(sc, IMASK, sc->sc_imask);
#endif
- while (etsec_read(sc, MIIMIND) != 0) {
+ while (etsec_mdio_read(sc, MIIMIND) != 0) {
delay(1);
}
- int data = etsec_read(sc, MIIMSTAT);
+ int data = etsec_mdio_read(sc, MIIMSTAT);
if (miimcom == MIIMCOM_SCAN)
- etsec_write(sc, MIIMCOM, miimcom);
+ etsec_mdio_write(sc, MIIMCOM, miimcom);
#if 0
aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n",
@@ -343,7 +357,7 @@ static void
pq3etsec_mii_writereg(device_t self, int phy, int reg, int data)
{
struct pq3etsec_softc * const sc = device_private(self);
- uint32_t miimcom = etsec_read(sc, MIIMCOM);
+ uint32_t miimcom = etsec_mdio_read(sc, MIIMCOM);
#if 0
aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n",
@@ -352,10 +366,10 @@ pq3etsec_mii_writereg(device_t self, int
// int s = splnet();
etsec_write(sc, IEVENT, IEVENT_MMWR);
- etsec_write(sc, MIIMADD,
+ etsec_mdio_write(sc, MIIMADD,
__SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG));
- etsec_write(sc, MIIMCOM, 0); /* clear any past bits */
- etsec_write(sc, MIIMCON, data);
+ etsec_mdio_write(sc, MIIMCOM, 0); /* clear any past bits */
+ etsec_mdio_write(sc, MIIMCON, data);
#if 0
sc->sc_imask |= IEVENT_MMWR;
@@ -363,12 +377,12 @@ pq3etsec_mii_writereg(device_t self, int
#endif
int timo = 1000; /* 1ms */
- while ((etsec_read(sc, MIIMIND) & MIIMIND_BUSY) && --timo > 0) {
+ while ((etsec_mdio_read(sc, MIIMIND) & MIIMIND_BUSY) && --timo > 0) {
delay(1);
}
if (miimcom == MIIMCOM_SCAN)
- etsec_write(sc, MIIMCOM, miimcom);
+ etsec_mdio_write(sc, MIIMCOM, miimcom);
etsec_write(sc, IEVENT, IEVENT_MMWR);
// splx(s);
}
@@ -453,6 +467,50 @@ pq3etsec_mediachange(struct ifnet *ifp)
}
#endif
+
+static const struct {
+ bus_addr_t reg_base;
+ bus_addr_t mdio_base;
+} etsec_mdio_map[] = {
+ { ETSEC1_BASE, ETSEC1_BASE },
+ { ETSEC2_BASE, ETSEC2_BASE },
+ { ETSEC3_BASE, ETSEC3_BASE },
+ { ETSEC4_BASE, ETSEC4_BASE },
+#if defined(P1025)
+ { ETSEC1_G0_BASE, ETSEC1_BASE },
+ { ETSEC1_G1_BASE, ETSEC1_BASE },
+ { ETSEC2_G0_BASE, ETSEC2_BASE },
+ { ETSEC2_G1_BASE, ETSEC2_BASE },
+ { ETSEC3_G0_BASE, ETSEC3_BASE },
+ { ETSEC3_G1_BASE, ETSEC3_BASE },
+#endif
+};
+
+static bool
+pq3etsec_mdio_map(struct pq3etsec_softc *sc, bus_addr_t reg_base,
+ bus_addr_t *mdio_basep)
+{
+ *mdio_basep = 0;
+ for (size_t i = 0; i < __arraycount(etsec_mdio_map); i++) {
+ if (etsec_mdio_map[i].reg_base == reg_base) {
+ bus_addr_t mdio_base = etsec_mdio_map[i].mdio_base;
+ if (mdio_base == reg_base) {
+ sc->sc_mdio_bsh = sc->sc_bsh;
+ return true;
+ }
+ if (!bus_space_map(sc->sc_bst,
+ mdio_base,
+ ETSEC_SIZE, 0, &sc->sc_mdio_bsh)) {
+ return true;
+ }
+ *mdio_basep = mdio_base;
+ break;
+ }
+ }
+
+ return false;
+}
+
static void
pq3etsec_attach(device_t parent, device_t self, void *aux)
{
@@ -462,6 +520,7 @@ pq3etsec_attach(device_t parent, device_
struct cpunode_locators * const cnl = &cna->cna_locs;
cfdata_t cf = device_cfdata(self);
int error;
+ bus_addr_t mdio_base;
psc->sc_children |= cna->cna_childmask;
sc->sc_dev = self;
@@ -494,6 +553,12 @@ pq3etsec_attach(device_t parent, device_
return;
}
+ if (!pq3etsec_mdio_map(sc, cnl->cnl_addr, &mdio_base)) {
+ aprint_error(": error mapping mdio registers @ %#x\n",
+ mdio_base);
+ return;
+ }
+
/*
* Assume firmware has aready set the mac address and fetch it
* before we reinit it.
Index: src/sys/arch/powerpc/include/booke/e500reg.h
diff -u src/sys/arch/powerpc/include/booke/e500reg.h:1.11 src/sys/arch/powerpc/include/booke/e500reg.h:1.12
--- src/sys/arch/powerpc/include/booke/e500reg.h:1.11 Sun Jul 15 08:44:56 2012
+++ src/sys/arch/powerpc/include/booke/e500reg.h Tue Jul 17 01:36:13 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: e500reg.h,v 1.11 2012/07/15 08:44:56 matt Exp $ */
+/* $NetBSD: e500reg.h,v 1.12 2012/07/17 01:36:13 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -333,6 +333,12 @@
#define ETSEC2_BASE 0x25000
#define ETSEC3_BASE 0x26000
#define ETSEC4_BASE 0x27000
+#define ETSEC1_G0_BASE 0xB0000
+#define ETSEC2_G0_BASE 0xB1000
+#define ETSEC3_G0_BASE 0xB2000
+#define ETSEC1_G1_BASE 0xB4000
+#define ETSEC2_G1_BASE 0xB5000
+#define ETSEC3_G1_BASE 0xB6000
#define ETSEC_SIZE 0x01000
#define ESDHC_BASE 0x2e000
Index: src/sys/arch/powerpc/include/booke/etsecreg.h
diff -u src/sys/arch/powerpc/include/booke/etsecreg.h:1.4 src/sys/arch/powerpc/include/booke/etsecreg.h:1.5
--- src/sys/arch/powerpc/include/booke/etsecreg.h:1.4 Mon May 7 23:04:22 2012
+++ src/sys/arch/powerpc/include/booke/etsecreg.h Tue Jul 17 01:36:13 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: etsecreg.h,v 1.4 2012/05/07 23:04:22 matt Exp $ */
+/* $NetBSD: etsecreg.h,v 1.5 2012/07/17 01:36:13 matt Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -151,6 +151,7 @@ struct rxfcb {
#define IEVENT_PERR __PPCBIT(31) /* Receive parse error for TOE */
#define IMASK 0x014 /* Interrupt mask register */
#define EDIS 0x018 /* error disabled register */
+#define EMAPG 0x01c /* group eror mapping register */
#define ECNTRL 0x020 /* ethernet control register */
#define ECNTRL_FIFM __PPCBIT(16) /* FIFO mode enable */
#define ECNTRL_CLRCNT __PPCBIT(17) /* Clear all MIB counters */
