Module Name: src
Committed By: matt
Date: Thu Sep 6 02:05:46 UTC 2012
Modified Files:
src/sys/arch/arm/include: armreg.h
Log Message:
Add ttbr/ttbr1/ttbcr registers
To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.62 src/sys/arch/arm/include/armreg.h:1.63
--- src/sys/arch/arm/include/armreg.h:1.62 Fri Aug 31 12:01:15 2012
+++ src/sys/arch/arm/include/armreg.h Thu Sep 6 02:05:46 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.62 2012/08/31 12:01:15 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.63 2012/09/06 02:05:46 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -566,8 +566,12 @@ ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c
ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
/* c2 registers */
-ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
-ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
+ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
+ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
+ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
+ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
+ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
+ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
/* c9 registers */
ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
