Module Name: src
Committed By: matt
Date: Tue Feb 12 15:05:26 UTC 2013
Modified Files:
src/sys/arch/arm/include: vfpreg.h
Log Message:
More fully document FPEXC register
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/include/vfpreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/vfpreg.h
diff -u src/sys/arch/arm/include/vfpreg.h:1.7 src/sys/arch/arm/include/vfpreg.h:1.8
--- src/sys/arch/arm/include/vfpreg.h:1.7 Tue Feb 12 00:32:15 2013
+++ src/sys/arch/arm/include/vfpreg.h Tue Feb 12 15:05:26 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: vfpreg.h,v 1.7 2013/02/12 00:32:15 matt Exp $ */
+/* $NetBSD: vfpreg.h,v 1.8 2013/02/12 15:05:26 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -64,14 +64,20 @@
#define FPU_VFP_CORTEXA8 0x410330c0
#define FPU_VFP_CORTEXA9 0x41033090
-#define VFP_FPEXC_EX 0x80000000 /* Exception status bit */
+#define VFP_FPEXC_EX 0x80000000 /* EXception status bit */
#define VFP_FPEXC_EN 0x40000000 /* VFP Enable bit */
-#define VFP_FPEXC_FP2V 0x10000000 /* FPINST2 instruction valid */
-#define VFP_FPEXC_VECITR 0x00000700 /* Vector iteration count */
-#define VFP_FPEXC_INV 0x00000080 /* Input exception flag */
-#define VFP_FPEXC_UFC 0x00000008 /* Potential underflow flag */
-#define VFP_FPEXC_OFC 0x00000004 /* Potential overflow flag */
-#define VFP_FPEXC_IOC 0x00000001 /* Potential inv. op. flag */
+#define VFP_FPEXC_DEX 0x20000000 /* Defined sync EXception bit */
+#define VFP_FPEXC_FP2V 0x10000000 /* FPinst2 instruction Valid */
+#define VFP_FPEXC_VV 0x08000000 /* Vecitr Valid */
+#define VFP_FPEXC_TFV 0x04000000 /* Trapped Fault Valid */
+#define VFP_FPEXC_VECITR 0x00000700 /* VECtor ITeRation count */
+#define VFP_FPEXC_IDF 0x00000080 /* Input Denormal flag */
+#define VFP_FPEXC_IXF 0x00000010 /* Potential inexact flag */
+#define VFP_FPEXC_UFF 0x00000008 /* Potential underflow flag */
+#define VFP_FPEXC_OFF 0x00000004 /* Potential overflow flag */
+#define VFP_FPEXC_DZF 0x00000002 /* Potential DivByZero flag */
+#define VFP_FPEXC_IOF 0x00000001 /* Potential inv. op. flag */
+#define VFP_FPEXE_FSUM 0x000000ff /* all flag bits */
#define VFP_FPSCR_N 0x80000000 /* set if compare <= result */
#define VFP_FPSCR_Z 0x40000000 /* set if compare = result */
@@ -91,7 +97,7 @@
#define VFP_FPSCR_IXE 0x00001000 /* Inexact Exception Enable */
#define VFP_FPSCR_UFE 0x00000800 /* Underflow Exception Enable */
#define VFP_FPSCR_OFE 0x00000400 /* Overflow Exception Enable */
-#define VFP_FPSCR_DZE 0x00000200 /* Inexact Exception Enable */
+#define VFP_FPSCR_DZE 0x00000200 /* DivByZero Exception Enable */
#define VFP_FPSCR_IOE 0x00000100 /* Invalid Operation Cumulative Flag */
#define VFP_FPSCR_IDC 0x00000080 /* Input Subnormal Cumlative Flag */
#define VFP_FPSCR_CSUM 0x0000001f /* IXC|UFC|OFC|DZC|IOC */
