Module Name: src
Committed By: matt
Date: Thu Feb 28 18:33:01 UTC 2013
Modified Files:
src/sys/arch/arm/include: armreg.h
Log Message:
Add c16 c8 (tlb) inlines.
Add CPUID of Cortex-A7 r0
To generate a diff of this commit:
cvs rdiff -u -r1.73 -r1.74 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.73 src/sys/arch/arm/include/armreg.h:1.74
--- src/sys/arch/arm/include/armreg.h:1.73 Tue Feb 12 15:06:40 2013
+++ src/sys/arch/arm/include/armreg.h Thu Feb 28 18:33:01 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.73 2013/02/12 15:06:40 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.74 2013/02/28 18:33:01 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -205,6 +205,7 @@
#define CPU_ID_ARM1176JZS 0x410fb760
#define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000)
#define CPU_ID_CORTEXA5R0 0x410fc050
+#define CPU_ID_CORTEXA7R0 0x411fc070
#define CPU_ID_CORTEXA8R1 0x411fc080
#define CPU_ID_CORTEXA8R2 0x412fc080
#define CPU_ID_CORTEXA8R3 0x413fc080
@@ -657,6 +658,21 @@ ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c1
ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */
ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */
ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */
+/* cp15 c8 registers */
+ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */
+ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */
+ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */
+ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */
+ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */
+ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */
+ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */
+ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */
+ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */
+ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */
+ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */
+ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */
+ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */
+ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */
/* cp15 c9 registers */
ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
