Module Name: src
Committed By: matt
Date: Sun Jun 16 16:42:13 UTC 2013
Modified Files:
src/sys/arch/arm/omap: omap2_reg.h omap3_ehci.c
Log Message:
OMAP4 EHCI enhancements
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/omap/omap2_reg.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/omap/omap3_ehci.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/omap2_reg.h
diff -u src/sys/arch/arm/omap/omap2_reg.h:1.18 src/sys/arch/arm/omap/omap2_reg.h:1.19
--- src/sys/arch/arm/omap/omap2_reg.h:1.18 Tue Apr 30 05:37:51 2013
+++ src/sys/arch/arm/omap/omap2_reg.h Sun Jun 16 16:42:13 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.18 2013/04/30 05:37:51 matt Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.19 2013/06/16 16:42:13 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -87,6 +87,32 @@
#define OMAP4430_L4_ABE_BASE 0x49000000 /* Actually L3 */
#define OMAP4430_L4_ABE_SIZE 0x01000000 /* 16MB */
+#define OMAP4430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
+#define OMAP4430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
+
+#define OMAP4430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
+#define OMAP4430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
+
+/* OMAP5 processors */
+
+#define OMAP5430_L4_CORE_BASE 0x4A000000
+#define OMAP5430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
+
+#define OMAP5430_L4_WAKEUP_BASE 0x4AE00000
+#define OMAP5430_L4_WAKEUP_SIZE 0x00200000 /* 2M */
+
+#define OMAP5430_L4_PERIPHERAL_BASE 0x48000000
+#define OMAP5430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+
+#define OMAP5430_L4_ABE_BASE 0x49000000 /* Actually L3 */
+#define OMAP5430_L4_ABE_SIZE 0x01000000 /* 16MB */
+
+#define OMAP5430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
+#define OMAP5430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
+
+#define OMAP5430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
+#define OMAP5430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
+
/* TI Sitara AM335x (OMAP like) */
#define TI_AM335X_L4_WAKEUP_BASE 0x44C00000
@@ -98,8 +124,8 @@
#define TI_AM335X_L4_FAST_BASE 0x4A000000
#define TI_AM335X_L4_FAST_SIZE 0x01000000 /* 16MB */
-#define TI_AM335X_L4_EMIF_BASE 0x4C000000
-#define TI_AM335X_L4_EMIF_SIZE 0x01000000 /* 16MB */
+#define TI_AM335X_EMIF1_BASE 0x4C000000
+#define TI_AM335X_EMIF1_SIZE 0x00100000 /* 4KB pad to 1MB */
/* TI Sitara DM37xx (OMAP like) */
@@ -133,6 +159,9 @@
#ifdef OMAP_4430
#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000)
#endif
+#ifdef OMAP_5430
+#define OMAP2_CM_BASE (OMAP5430_L4_CORE_BASE + 0x04000)
+#endif
#ifdef TI_AM335X
#define OMAP2_CM_BASE (TI_AM335X_L4_WAKEUP_BASE + 0x200000)
#endif
@@ -346,6 +375,9 @@
#ifdef OMAP_4430
#define OMAP2_PRM_BASE (OMAP4430_L4_WAKEUP_BASE + 0x6000)
#endif
+#ifdef OMAP_5430
+#define OMAP2_PRM_BASE (OMAP5430_L4_WAKEUP_BASE + 0x6000)
+#endif
#ifdef TI_AM335X
#define OMAP2_PRM_BASE 0x48306000
#endif
@@ -670,6 +702,15 @@
#define GPIO5_BASE_4430 0x4805b000
#define GPIO6_BASE_4430 0x4805d000
+#define GPIO1_BASE_5430 0x4ae10000
+#define GPIO2_BASE_5430 0x48055000
+#define GPIO3_BASE_5430 0x48057000
+#define GPIO4_BASE_5430 0x48059000
+#define GPIO5_BASE_5430 0x4805b000
+#define GPIO6_BASE_5430 0x4805d000
+#define GPIO7_BASE_5430 0x48051000
+#define GPIO8_BASE_5430 0x48053000
+
#define GPIO0_BASE_TI_AM335X 0x44e07000
#define GPIO1_BASE_TI_AM335X 0x4804c000
#define GPIO2_BASE_TI_AM335X 0x481ac000
@@ -718,14 +759,11 @@
*/
#define OHCI1_BASE_2430 0x4805e000
-#define OHCI1_BASE_3430 0x48064400
-#define EHCI1_BASE_3430 0x48064800
+#define OHCI1_BASE_OMAP3 0x48064400
+#define EHCI1_BASE_OMAP3 0x48064800
-#define OHCI1_BASE_3530 0x48064400
-#define EHCI1_BASE_3530 0x48064800
-
-#define OHCI1_BASE_4430 0x4A064800
-#define EHCI1_BASE_4430 0x4A064C00
+#define OHCI1_BASE_OMAP4 0x4A064800
+#define EHCI1_BASE_OMAP4 0x4A064C00
/*
* SDRC
@@ -743,13 +781,13 @@
#define TI_AM335X_CTLMOD_BASE 0x44e10000
#define CTLMOD_CONTROL_STATUS 0x40
#define CTLMOD_CONTROL_STATUS_SYSBOOT1 __BITS(23,22)
-
-#define TI_AM335X_EMIF0_BASE 0x4c000000
-#define TI_AM335X_EMIF0_SIZE 0x00100000
+#endif
+#if defined(OMAP4) || defined(TI_AM335X)
#define EMIF_SDRAM_CONFIG 8
#define SDRAM_CONFIG_WIDTH __BITS(15,14)
#define SDRAM_CONFIG_RSIZE __BITS(9,7)
#define SDRAM_CONFIG_IBANK __BITS(6,4)
+#define SDRAM_CONFIG_EBANK __BIT(3)
#define SDRAM_CONFIG_PAGESIZE __BITS(2,0)
#endif
Index: src/sys/arch/arm/omap/omap3_ehci.c
diff -u src/sys/arch/arm/omap/omap3_ehci.c:1.6 src/sys/arch/arm/omap/omap3_ehci.c:1.7
--- src/sys/arch/arm/omap/omap3_ehci.c:1.6 Mon Dec 24 06:41:02 2012
+++ src/sys/arch/arm/omap/omap3_ehci.c Sun Jun 16 16:42:13 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_ehci.c,v 1.6 2012/12/24 06:41:02 kiyohara Exp $ */
+/* $NetBSD: omap3_ehci.c,v 1.7 2013/06/16 16:42:13 matt Exp $ */
/*-
* Copyright (c) 2010-2012 Jared D. McNeill <[email protected]>
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.6 2012/12/24 06:41:02 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.7 2013/06/16 16:42:13 matt Exp $");
#include "locators.h"
@@ -273,10 +273,18 @@ omap3_ehci_attach1(device_t self)
static int
omap3_ehci_match(device_t parent, cfdata_t match, void *opaque)
{
+#ifdef OMAP3
struct obio_attach_args *obio = opaque;
+#endif
- if (obio->obio_addr == EHCI1_BASE_3530)
+#if defined(OMAP3) && !defined(OMAP4)
+ if (obio->obio_addr == EHCI1_BASE_OMAP3)
+ return 1;
+#endif
+#ifdef OMAP4
+ if (obio->obio_addr == EHCI1_BASE_OMAP4)
return 1;
+#endif
return 0;
}
@@ -429,7 +437,6 @@ dpll5_init(struct omap3_ehci_softc *sc)
{
bus_space_tag_t iot = sc->sc.iot;
bus_space_handle_t ioh;
- uint32_t m, n, m2;
int err;
if (sc->sc_dpll5.m == 0 || sc->sc_dpll5.n == 0 || sc->sc_dpll5.m2 == 0)
@@ -440,27 +447,38 @@ dpll5_init(struct omap3_ehci_softc *sc)
panic("%s: cannot map CCR_CM_BASE at %#x, error %d\n",
__func__, CCR_CM_BASE, err);
-#if OMAP_MPU_TIMER_CLOCK_FREQ != 12000000
-#error FIXME
-#endif
+#if defined(OMAP_3530) || defined(OMAP_3540)
/* set the multiplier and divider values for the desired CLKOUT freq */
- m = sc->sc_dpll5.m;
- n = sc->sc_dpll5.n;
+ uint32_t m = sc->sc_dpll5.m;
+ uint32_t n = sc->sc_dpll5.n;
/* set the corresponding output dividers */
- m2 = sc->sc_dpll5.m2;
+ uint32_t m2 = sc->sc_dpll5.m2;
- /* 4.7.6.2 In the DPLL programming sequence, the DPLL_FREQSEL must be programmed
- * before the new Multiplier factor M and the Divider factor N are programmed so
- * that the new value is taken into account during current DPLL relock.
+ KASSERTMSG(479900000 <= 2 * m * (omap_sys_clk / ((n + 1) * m2)),
+ "m=%u n=%u m2=%u freq=%u",
+ m, n, m2, 2 * m * (omap_sys_clk / ((n + 1) * m2)));
+ KASSERTMSG(2 * m * (omap_sys_clk / ((n + 1) * m2)) <= 480100000,
+ "m=%u n=%u m2=%u freq=%u",
+ m, n, m2, 2 * m * (omap_sys_clk / ((n + 1) * m2)));
+
+ /* 4.7.6.2
+ * In the DPLL programming sequence, the DPLL_FREQSEL must be
+ * programmed before the new Multiplier factor M and the Divider
+ * factor N are programmed so that the new value is taken into
+ * account during current DPLL relock.
*/
bus_space_write_4(iot, ioh, CM_CLKEN2_PLL, (0x4 << 4) | 0x7);
bus_space_write_4(iot, ioh, CM_CLKSEL4_PLL, (m << 8) | n);
bus_space_write_4(iot, ioh, CM_CLKSEL5_PLL, m2);
- /* Put DPLL5 into low power stop mode when the 120MHz clock is not required (restarted automatically) */
+ /*
+ * Put DPLL5 into low power stop mode when the 120MHz clock
+ * is not required (restarted automatically)
+ */
bus_space_write_4(iot, ioh, CM_AUTOIDLE2_PLL, AUTO_PERIPH2_DPLL);
+#endif /* OMAP_3540 || OMAP_3530 */
bus_space_unmap(iot, ioh, CCR_CM_SIZE);
}
