Module Name: src
Committed By: msaitoh
Date: Wed Jul 17 15:22:43 UTC 2013
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry from the document
(Table 3-22 Encoding of CPUID Leaf 2 Descriptors, Intel 64 and IA-32
Architectures Software Developer's Manual Vol. 2A.)
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.13 src/sys/arch/x86/include/cacheinfo.h:1.14
--- src/sys/arch/x86/include/cacheinfo.h:1.13 Sun Dec 4 17:00:10 2011
+++ src/sys/arch/x86/include/cacheinfo.h Wed Jul 17 15:22:43 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.13 2011/12/04 17:00:10 chs Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.14 2013/07/17 15:22:43 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -234,7 +234,7 @@ __CI_TBL(CAI_ICACHE, 0x09, 4,
__CI_TBL(CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL), \
__CI_TBL(CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL), \
-__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 32, NULL), \
+__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x21, 8, 256 * 1024, 64, NULL), /* L2 (MLC) */ \
__CI_TBL(CAI_L2CACHE, 0x39, 4, 128 * 1024, 64, NULL), \
__CI_TBL(CAI_L2CACHE, 0x3a, 6, 192 * 1024, 64, NULL), \
@@ -299,7 +299,7 @@ __CI_TBL(CAI_L3CACHE, 0xe2, 16, 2 * 1
__CI_TBL(CAI_L3CACHE, 0xe3, 16, 4 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \
-__CI_TBL(CAI_L3CACHE, 0xeb, 24,24 * 1024 * 1024, 64, NULL), \
+__CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \
__CI_TBL(0, 0, 0, 0, 0, NULL) \
}
