Module Name: src
Committed By: joerg
Date: Mon Dec 2 18:36:11 UTC 2013
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_arm8.S cpufunc_asm_sa1.S
cpufunc_asm_sa11x0.S cpufunc_asm_xscale.S fiq_subr.S
src/sys/arch/arm/arm32: exception.S spl.S
src/sys/arch/arm/include/arm32: frame.h
src/sys/arch/arm/iomd: iomd_irq.S
src/sys/arch/arm/ofw: ofw_irq.S
src/sys/arch/arm/sa11x0: sa11x0_irq.S
src/sys/arch/evbarm/ixm1200: ixm1200_start.S
src/sys/arch/hpcarm/hpcarm: locore.S softintr.c spl.S
src/sys/arch/shark/isa: isa_irq.S
src/sys/arch/zaurus/stand/zbsdmod: zbsdmod.c
Log Message:
Don't use cpsr_all/spsr_all with mrs, it doesn't take a mask.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/arm/cpufunc_asm_arm8.S
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/arm/cpufunc_asm_sa1.S
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/arm/cpufunc_asm_sa11x0.S
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/arm/cpufunc_asm_xscale.S
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/fiq_subr.S
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/arm32/exception.S
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/arm32/spl.S
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/include/arm32/frame.h
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/iomd/iomd_irq.S
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/ofw/ofw_irq.S
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/sa11x0/sa11x0_irq.S
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbarm/ixm1200/ixm1200_start.S
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/hpcarm/hpcarm/locore.S \
src/sys/arch/hpcarm/hpcarm/softintr.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/hpcarm/hpcarm/spl.S
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/shark/isa/isa_irq.S
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/zaurus/stand/zbsdmod/zbsdmod.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_arm8.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm8.S:1.8 src/sys/arch/arm/arm/cpufunc_asm_arm8.S:1.9
--- src/sys/arch/arm/arm/cpufunc_asm_arm8.S:1.8 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/arm/cpufunc_asm_arm8.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm8.S,v 1.8 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm8.S,v 1.9 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1997 ARM Limited
@@ -65,7 +65,7 @@ ENTRY(arm8_clock_config)
* addresses that are about to change.
*/
ENTRY(arm8_setttb)
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
@@ -176,7 +176,7 @@ ENTRY(arm8_cache_purgeID)
mov r0, #0x00000000
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
@@ -248,7 +248,7 @@ ENTRY(arm8_cache_purgeID_E)
* mcr p15, 0, rd, c7, c11, 1
* mcr p15, 0, rd, c7, c7, 1
*/
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
mcr p15, 0, r0, c7, c11, 1 /* clean I+D single entry */
Index: src/sys/arch/arm/arm/cpufunc_asm_sa1.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_sa1.S:1.13 src/sys/arch/arm/arm/cpufunc_asm_sa1.S:1.14
--- src/sys/arch/arm/arm/cpufunc_asm_sa1.S:1.13 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/arm/cpufunc_asm_sa1.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_sa1.S,v 1.13 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: cpufunc_asm_sa1.S,v 1.14 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@@ -49,7 +49,7 @@
*/
ENTRY(sa1_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
#else
@@ -146,7 +146,7 @@ _C_LABEL(sa1_cache_clean_size):
#ifdef CACHE_CLEAN_BLOCK_INTR
#define SA1_CACHE_CLEAN_BLOCK \
- mrs r3, cpsr_all ; \
+ mrs r3, cpsr ; \
orr r0, r3, #(I32_bit | F32_bit) ; \
msr cpsr_all, r0
Index: src/sys/arch/arm/arm/cpufunc_asm_sa11x0.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_sa11x0.S:1.4 src/sys/arch/arm/arm/cpufunc_asm_sa11x0.S:1.5
--- src/sys/arch/arm/arm/cpufunc_asm_sa11x0.S:1.4 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/arm/cpufunc_asm_sa11x0.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_sa11x0.S,v 1.4 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: cpufunc_asm_sa11x0.S,v 1.5 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -79,7 +79,7 @@ ENTRY(sa11x0_cpu_sleep)
* re-enable clock switching before servicing interrupts.
*/
- mrs r3, cpsr_all /* 6 */
+ mrs r3, cpsr /* 6 */
orr r2, r3, #(I32_bit|F32_bit) /* 7 */
msr cpsr_all, r2 /* 8 */
Index: src/sys/arch/arm/arm/cpufunc_asm_xscale.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.21 src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.22
--- src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.21 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/arm/cpufunc_asm_xscale.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_xscale.S,v 1.21 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: cpufunc_asm_xscale.S,v 1.22 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -133,7 +133,7 @@ END(xscale_control)
*/
ENTRY(xscale_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r2, r3, #(I32_bit | F32_bit)
msr cpsr_all, r2
#else
@@ -273,7 +273,7 @@ _C_LABEL(xscale_minidata_clean_size):
#ifdef CACHE_CLEAN_BLOCK_INTR
#define XSCALE_CACHE_CLEAN_BLOCK \
- mrs r3, cpsr_all ; \
+ mrs r3, cpsr ; \
orr r0, r3, #(I32_bit | F32_bit) ; \
msr cpsr_all, r0
Index: src/sys/arch/arm/arm/fiq_subr.S
diff -u src/sys/arch/arm/arm/fiq_subr.S:1.5 src/sys/arch/arm/arm/fiq_subr.S:1.6
--- src/sys/arch/arm/arm/fiq_subr.S:1.5 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/arm/fiq_subr.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: fiq_subr.S,v 1.5 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: fiq_subr.S,v 1.6 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -57,7 +57,7 @@
cps #PSR_FIQ32_MODE
#else
#define SWITCH_TO_FIQ_MODE \
- mrs r2, cpsr_all ; \
+ mrs r2, cpsr ; \
mov r3, r2 ; \
bic r2, r2, #(PSR_MODE) ; \
orr r2, r2, #(PSR_FIQ32_MODE) ; \
Index: src/sys/arch/arm/arm32/exception.S
diff -u src/sys/arch/arm/arm32/exception.S:1.19 src/sys/arch/arm/arm32/exception.S:1.20
--- src/sys/arch/arm/arm32/exception.S:1.19 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/arm32/exception.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: exception.S,v 1.19 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: exception.S,v 1.20 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@@ -51,7 +51,7 @@
#include <arm/locore.h>
- RCSID("$NetBSD: exception.S,v 1.19 2013/08/18 06:28:18 matt Exp $")
+ RCSID("$NetBSD: exception.S,v 1.20 2013/12/02 18:36:10 joerg Exp $")
.text
.align 0
@@ -178,8 +178,8 @@ ASEND(data_abort_entry)
* it like a Data Abort.
*/
ASENTRY_NP(address_exception_entry)
- mrs r1, cpsr_all
- mrs r2, spsr_all
+ mrs r1, cpsr
+ mrs r2, spsr
mov r3, lr
adr r0, .Laddress_exception_msg
bl _C_LABEL(printf) /* XXX CLOBBERS LR!! */
Index: src/sys/arch/arm/arm32/spl.S
diff -u src/sys/arch/arm/arm32/spl.S:1.9 src/sys/arch/arm/arm32/spl.S:1.10
--- src/sys/arch/arm/arm32/spl.S:1.9 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/arm32/spl.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: spl.S,v 1.9 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: spl.S,v 1.10 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1996-1998 Mark Brinicombe.
@@ -43,7 +43,7 @@
#include <arm/locore.h>
#include <arm/arm32/psl.h>
- RCSID("$NetBSD: spl.S,v 1.9 2013/08/18 06:28:18 matt Exp $")
+ RCSID("$NetBSD: spl.S,v 1.10 2013/12/02 18:36:10 joerg Exp $")
.text
.align 0
@@ -61,7 +61,7 @@ ENTRY(raisespl)
stmfd sp!, {r0, r1, r4, lr} /* Preserve registers */
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r2, r4, #(I32_bit)
msr cpsr_c, r2
@@ -81,7 +81,7 @@ ENTRY(lowerspl)
stmfd sp!, {r0, r1, r4, lr} /* Preserve registers */
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r2, r4, #(I32_bit)
msr cpsr_c, r2
@@ -104,7 +104,7 @@ ENTRY(splx)
stmfd sp!, {r0, r1, r4, lr}
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r2, r4, #(I32_bit)
msr cpsr_c, r2
Index: src/sys/arch/arm/include/arm32/frame.h
diff -u src/sys/arch/arm/include/arm32/frame.h:1.36 src/sys/arch/arm/include/arm32/frame.h:1.37
--- src/sys/arch/arm/include/arm32/frame.h:1.36 Sun Aug 18 06:37:02 2013
+++ src/sys/arch/arm/include/arm32/frame.h Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: frame.h,v 1.36 2013/08/18 06:37:02 matt Exp $ */
+/* $NetBSD: frame.h,v 1.37 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@@ -351,7 +351,7 @@ LOCK_CAS_DEBUG_LOCALS
sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \
PUSHUSERREGS; /* Push the user mode registers */ \
mov r0, r0; /* NOP for previous instruction */ \
- mrs r0, spsr_all; /* Get the SPSR */ \
+ mrs r0, spsr; /* Get the SPSR */ \
str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */
/*
@@ -364,7 +364,7 @@ LOCK_CAS_DEBUG_LOCALS
str lr, [sp, #-4]!; /* save SVC32 lr */ \
str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \
str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \
- mrs r0, cpsr_all; /* Get the CPSR */ \
+ mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */
/*
@@ -378,7 +378,7 @@ LOCK_CAS_DEBUG_LOCALS
str ip, [sp, #TF_SVC_SP]; \
str lr, [sp, #TF_SVC_LR]; \
str lr, [sp, #TF_PC]; \
- mrs rX, cpsr_all; /* Get the CPSR */ \
+ mrs rX, cpsr; /* Get the CPSR */ \
str rX, [sp, #TF_SPSR] /* save in trapframe */
#define PUSHSWITCHFRAME1 \
@@ -394,13 +394,13 @@ LOCK_CAS_DEBUG_LOCALS
#define PUSHSWITCHFRAME2 \
strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \
strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \
- mrs r0, cpsr_all; /* Get the CPSR */ \
+ mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #TF_SPSR] /* save in trapframe */
#else
#define PUSHSWITCHFRAME2 \
add r0, sp, #TF_R8; /* get ptr to r8 and above */ \
stmia r0, {r8-r11}; /* save rest of registers */ \
- mrs r0, cpsr_all; /* Get the CPSR */ \
+ mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #TF_SPSR] /* save in trapframe */
#endif
@@ -469,7 +469,7 @@ LOCK_CAS_DEBUG_LOCALS
sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
PUSHUSERREGS; /* Push the user mode registers */ \
mov r0, r0; /* NOP for previous instruction */ \
- mrs r0, spsr_all; /* Get the SPSR */ \
+ mrs r0, spsr; /* Get the SPSR */ \
str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */
/*
Index: src/sys/arch/arm/iomd/iomd_irq.S
diff -u src/sys/arch/arm/iomd/iomd_irq.S:1.15 src/sys/arch/arm/iomd/iomd_irq.S:1.16
--- src/sys/arch/arm/iomd/iomd_irq.S:1.15 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/iomd/iomd_irq.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: iomd_irq.S,v 1.15 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: iomd_irq.S,v 1.16 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -208,7 +208,7 @@ Lfind_highest_ipl:
/* Update the IOMD irq masks */
bl _C_LABEL(irq_setmasks)
- mrs r0, cpsr_all /* Enable IRQ's */
+ mrs r0, cpsr /* Enable IRQ's */
bic r0, r0, #I32_bit
msr cpsr_all, r0
@@ -331,7 +331,7 @@ exitirq:
#endif
/* Kill IRQ's in preparation for exit */
- mrs r0, cpsr_all
+ mrs r0, cpsr
orr r0, r0, #(I32_bit)
msr cpsr_all, r0
@@ -354,7 +354,7 @@ Lcurrent_mask:
ENTRY(irq_setmasks)
/* Disable interrupts */
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r1, r3, #(I32_bit)
msr cpsr_all, r1
Index: src/sys/arch/arm/ofw/ofw_irq.S
diff -u src/sys/arch/arm/ofw/ofw_irq.S:1.14 src/sys/arch/arm/ofw/ofw_irq.S:1.15
--- src/sys/arch/arm/ofw/ofw_irq.S:1.14 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/ofw/ofw_irq.S Mon Dec 2 18:36:10 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: ofw_irq.S,v 1.14 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: ofw_irq.S,v 1.15 2013/12/02 18:36:10 joerg Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -248,7 +248,7 @@ Lfind_highest_ipl:
/* Update the irq masks */
bl _C_LABEL(irq_setmasks)
- mrs r0, cpsr_all /* Enable IRQ's */
+ mrs r0, cpsr /* Enable IRQ's */
bic r0, r0, #I32_bit
msr cpsr_all, r0
@@ -318,7 +318,7 @@ nextirq:
bl _C_LABEL(dosoftints) /* Handle the soft interrupts */
/* Kill IRQ's in preparation for exit */
- mrs r0, cpsr_all
+ mrs r0, cpsr
orr r0, r0, #(I32_bit)
msr cpsr_all, r0
@@ -446,7 +446,7 @@ _C_LABEL(dotickgrovelling):
str r1, [r0, #0] /* plug spsr */
/* Sneak into SVC mode to get sp and lr */
- mrs r3, cpsr_all
+ mrs r3, cpsr
bic r3, r3, #(PSR_MODE)
orr r3, r3, #(PSR_SVC32_MODE)
msr cpsr_all, r3
Index: src/sys/arch/arm/sa11x0/sa11x0_irq.S
diff -u src/sys/arch/arm/sa11x0/sa11x0_irq.S:1.17 src/sys/arch/arm/sa11x0/sa11x0_irq.S:1.18
--- src/sys/arch/arm/sa11x0/sa11x0_irq.S:1.17 Sun Aug 18 06:28:18 2013
+++ src/sys/arch/arm/sa11x0/sa11x0_irq.S Mon Dec 2 18:36:11 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: sa11x0_irq.S,v 1.17 2013/08/18 06:28:18 matt Exp $ */
+/* $NetBSD: sa11x0_irq.S,v 1.18 2013/12/02 18:36:11 joerg Exp $ */
/*
* Copyright (c) 1998 Mark Brinicombe.
@@ -150,7 +150,7 @@ Lfind_highest_ipl:
bl _C_LABEL(printf)
ldmia sp!, {r0,r1,r2}
#endif
- mrs r0, cpsr_all /* Enable IRQs */
+ mrs r0, cpsr /* Enable IRQs */
bic r0, r0, #I32_bit
msr cpsr_all, r0
@@ -234,7 +234,7 @@ nextirq:
#endif
/* Kill IRQ's in preparation for exit */
- mrs r0, cpsr_all
+ mrs r0, cpsr
orr r0, r0, #(I32_bit)
msr cpsr_all, r0
@@ -262,7 +262,7 @@ ENTRY(irq_setmasks)
stmfd sp!, {r0, r1, r4, lr} /* Preserve registers */
/* Disable interrupts */
- mrs r1, cpsr_all
+ mrs r1, cpsr
orr r3, r1, #(I32_bit)
msr cpsr_all, r3
Index: src/sys/arch/evbarm/ixm1200/ixm1200_start.S
diff -u src/sys/arch/evbarm/ixm1200/ixm1200_start.S:1.4 src/sys/arch/evbarm/ixm1200/ixm1200_start.S:1.5
--- src/sys/arch/evbarm/ixm1200/ixm1200_start.S:1.4 Mon Jan 31 06:28:04 2011
+++ src/sys/arch/evbarm/ixm1200/ixm1200_start.S Mon Dec 2 18:36:11 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: ixm1200_start.S,v 1.4 2011/01/31 06:28:04 matt Exp $ */
+/* $NetBSD: ixm1200_start.S,v 1.5 2013/12/02 18:36:11 joerg Exp $ */
/*
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -39,14 +39,14 @@
.section .start,"ax",%progbits
-RCSID("$NetBSD: ixm1200_start.S,v 1.4 2011/01/31 06:28:04 matt Exp $")
+RCSID("$NetBSD: ixm1200_start.S,v 1.5 2013/12/02 18:36:11 joerg Exp $")
.global _C_LABEL(ixm1200_start)
_C_LABEL(ixm1200_start):
/*
* Disable IRQ and FIQ
*/
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r1, r3, #(I32_bit | F32_bit)
msr cpsr_all, r1
Index: src/sys/arch/hpcarm/hpcarm/locore.S
diff -u src/sys/arch/hpcarm/hpcarm/locore.S:1.14 src/sys/arch/hpcarm/hpcarm/locore.S:1.15
--- src/sys/arch/hpcarm/hpcarm/locore.S:1.14 Mon Aug 26 15:31:44 2013
+++ src/sys/arch/hpcarm/hpcarm/locore.S Mon Dec 2 18:36:11 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.14 2013/08/26 15:31:44 matt Exp $ */
+/* $NetBSD: locore.S,v 1.15 2013/12/02 18:36:11 joerg Exp $ */
/*
* Copyright (C) 1994-1997 Mark Brinicombe
@@ -57,7 +57,7 @@ ENTRY_NP(kernel_text)
ASENTRY_NP(start)
/* Put the processer in SVC mode */
mov r5, sp
- mrs r4, cpsr_all
+ mrs r4, cpsr
bic r4, r4, #(PSR_MODE)
orr r4, r4, #(PSR_SVC32_MODE)
msr cpsr_all, r4
@@ -255,7 +255,7 @@ ENTRY(dumpsys)
stmfd sp!, {r0-r7, lr}
/* push the status bits onto the stack */
- mrs r0, cpsr_all
+ mrs r0, cpsr
stmfd sp!, {r0}
/* fill in dumppcb */
Index: src/sys/arch/hpcarm/hpcarm/softintr.c
diff -u src/sys/arch/hpcarm/hpcarm/softintr.c:1.14 src/sys/arch/hpcarm/hpcarm/softintr.c:1.15
--- src/sys/arch/hpcarm/hpcarm/softintr.c:1.14 Mon Apr 28 20:23:21 2008
+++ src/sys/arch/hpcarm/hpcarm/softintr.c Mon Dec 2 18:36:11 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: softintr.c,v 1.14 2008/04/28 20:23:21 martin Exp $ */
+/* $NetBSD: softintr.c,v 1.15 2013/12/02 18:36:11 joerg Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: softintr.c,v 1.14 2008/04/28 20:23:21 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: softintr.c,v 1.15 2013/12/02 18:36:11 joerg Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -115,7 +115,7 @@ softintr_schedule(void *cookie)
sh->sh_hlink = NULL;
#ifdef __GNUC__
- __asm volatile("mrs %0, cpsr_all\n orr r1, %0, %1\n msr cpsr_all, r1" :
+ __asm volatile("mrs %0, cpsr\n orr r1, %0, %1\n msr cpsr_a;;, r1" :
"=r" (saved_cpsr) : "i" (I32_bit) : "r1");
#else
saved_cpsr = SetCPSR(I32_bit, I32_bit);
@@ -156,7 +156,7 @@ softintr_dispatch(int s)
while (1) {
/* Protect list operation from interrupts */
#ifdef __GNUC__
- __asm volatile("mrs %0, cpsr_all\n orr r1, %0, %1\n"
+ __asm volatile("mrs %0, cpsr\n orr r1, %0, %1\n"
" msr cpsr_all, r1" : "=r" (saved_cpsr) :
"i" (I32_bit) : "r1");
#else
Index: src/sys/arch/hpcarm/hpcarm/spl.S
diff -u src/sys/arch/hpcarm/hpcarm/spl.S:1.6 src/sys/arch/hpcarm/hpcarm/spl.S:1.7
--- src/sys/arch/hpcarm/hpcarm/spl.S:1.6 Tue Jan 8 02:07:55 2008
+++ src/sys/arch/hpcarm/hpcarm/spl.S Mon Dec 2 18:36:11 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: spl.S,v 1.6 2008/01/08 02:07:55 matt Exp $ */
+/* $NetBSD: spl.S,v 1.7 2013/12/02 18:36:11 joerg Exp $ */
/*
* Copyright (c) 1996-1998 Mark Brinicombe.
@@ -52,7 +52,7 @@ Lcurrent_spl_level:
ENTRY(raisespl)
stmfd sp!, {r4}
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r1, r4, #(I32_bit)
msr cpsr_all, r1
@@ -75,7 +75,7 @@ raisespl_exit:
ENTRY(lowerspl)
stmfd sp!, {r4}
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r1, r4, #(I32_bit)
msr cpsr_all, r1
@@ -104,7 +104,7 @@ lowerspl_exit:
ENTRY(splx)
stmfd sp!, {r4}
/* Disable interrupts */
- mrs r4, cpsr_all
+ mrs r4, cpsr
orr r1, r4, #(I32_bit)
msr cpsr_all, r1
Index: src/sys/arch/shark/isa/isa_irq.S
diff -u src/sys/arch/shark/isa/isa_irq.S:1.15 src/sys/arch/shark/isa/isa_irq.S:1.16
--- src/sys/arch/shark/isa/isa_irq.S:1.15 Mon Aug 12 17:32:03 2013
+++ src/sys/arch/shark/isa/isa_irq.S Mon Dec 2 18:36:11 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: isa_irq.S,v 1.15 2013/08/12 17:32:03 matt Exp $ */
+/* $NetBSD: isa_irq.S,v 1.16 2013/12/02 18:36:11 joerg Exp $ */
/*
* Copyright 1997
@@ -206,7 +206,7 @@ ASENTRY_NP(irq_entry)
/* Update the IOMD irq masks */
bl _C_LABEL(irq_setmasks)
- mrs r0, cpsr_all /* Enable IRQ's */
+ mrs r0, cpsr /* Enable IRQ's */
bic r0, r0, #I32_bit
msr cpsr_all, r0
@@ -274,7 +274,7 @@ nextirq:
#endif
/* Kill IRQ's in preparation for exit */
- mrs r0, cpsr_all
+ mrs r0, cpsr
orr r0, r0, #(I32_bit)
msr cpsr_all, r0
@@ -304,7 +304,7 @@ AST_ALIGNMENT_FAULT_LOCALS
ENTRY(irq_setmasks)
/* Disable interrupts */
- mrs r3, cpsr_all
+ mrs r3, cpsr
orr r1, r3, #(I32_bit)
msr cpsr_all, r1
Index: src/sys/arch/zaurus/stand/zbsdmod/zbsdmod.c
diff -u src/sys/arch/zaurus/stand/zbsdmod/zbsdmod.c:1.8 src/sys/arch/zaurus/stand/zbsdmod/zbsdmod.c:1.9
--- src/sys/arch/zaurus/stand/zbsdmod/zbsdmod.c:1.8 Fri Dec 16 14:17:41 2011
+++ src/sys/arch/zaurus/stand/zbsdmod/zbsdmod.c Mon Dec 2 18:36:11 2013
@@ -1,4 +1,4 @@
-/* $NetBSD: zbsdmod.c,v 1.8 2011/12/16 14:17:41 nonaka Exp $ */
+/* $NetBSD: zbsdmod.c,v 1.9 2013/12/02 18:36:11 joerg Exp $ */
/* $OpenBSD: zbsdmod.c,v 1.7 2005/05/02 02:45:29 uwe Exp $ */
/*
@@ -152,7 +152,7 @@ elf32bsdboot(void)
esymp = (vaddr_t *)phdr[i].p_vaddr;
}
- __asm volatile ("mrs %0, cpsr_all" : "=r" (cpsr));
+ __asm volatile ("mrs %0, cpsr" : "=r" (cpsr));
cpsr |= 0xc0; /* set FI */
__asm volatile ("msr cpsr_all, %0" :: "r" (cpsr));
