Module Name: src
Committed By: hkenken
Date: Sat Mar 22 09:46:33 UTC 2014
Modified Files:
src/sys/arch/arm/imx: imx51_ccm.c imx51_ccmreg.h imx51_ccmvar.h
imx51_esdhc.c
Log Message:
Fix SDHC clocks.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/imx/imx51_ccm.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/imx/imx51_ccmreg.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/imx/imx51_ccmvar.h \
src/sys/arch/arm/imx/imx51_esdhc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/imx/imx51_ccm.c
diff -u src/sys/arch/arm/imx/imx51_ccm.c:1.4 src/sys/arch/arm/imx/imx51_ccm.c:1.5
--- src/sys/arch/arm/imx/imx51_ccm.c:1.4 Sat Mar 22 09:28:08 2014
+++ src/sys/arch/arm/imx/imx51_ccm.c Sat Mar 22 09:46:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccm.c,v 1.4 2014/03/22 09:28:08 hkenken Exp $ */
+/* $NetBSD: imx51_ccm.c,v 1.5 2014/03/22 09:46:33 hkenken Exp $ */
/*
* Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.4 2014/03/22 09:28:08 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.5 2014/03/22 09:46:33 hkenken Exp $");
#include <sys/types.h>
#include <sys/time.h>
@@ -294,6 +294,52 @@ imx51_get_clock(enum imx51_clock clk)
break;
}
return freq;
+ case IMX51CLK_ESDHC2_CLK_ROOT:
+ case IMX51CLK_ESDHC4_CLK_ROOT:
+ cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
+
+ sel = 0;
+ if (clk == IMX51CLK_ESDHC2_CLK_ROOT)
+ sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC2_CLK_SEL);
+ else if (clk == IMX51CLK_ESDHC4_CLK_ROOT)
+ sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC4_CLK_SEL);
+
+ if (sel == 0)
+ freq = imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT);
+ else
+ freq = imx51_get_clock(IMX51CLK_ESDHC3_CLK_ROOT);
+
+ return freq;
+ case IMX51CLK_ESDHC1_CLK_ROOT:
+ case IMX51CLK_ESDHC3_CLK_ROOT:
+
+ cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
+ cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
+
+ sel = 0;
+ if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
+ sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC1_CLK_SEL);
+ else if (clk == IMX51CLK_ESDHC3_CLK_ROOT)
+ sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC3_CLK_SEL);
+
+ switch (sel) {
+ case 0:
+ case 1:
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
+ break;
+ case 3:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ }
+
+ if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
+ freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PRED)) /
+ (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PODF));
+ else if (clk == IMX51CLK_ESDHC3_CLK_ROOT)
+ freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PRED)) /
+ (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PODF));
+ return freq;
case IMX51CLK_CSPI_CLK_ROOT:
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
cscdr2 = bus_space_read_4(iot, ioh, CCMC_CSCDR2);
Index: src/sys/arch/arm/imx/imx51_ccmreg.h
diff -u src/sys/arch/arm/imx/imx51_ccmreg.h:1.3 src/sys/arch/arm/imx/imx51_ccmreg.h:1.4
--- src/sys/arch/arm/imx/imx51_ccmreg.h:1.3 Sat Mar 22 09:28:08 2014
+++ src/sys/arch/arm/imx/imx51_ccmreg.h Sat Mar 22 09:46:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccmreg.h,v 1.3 2014/03/22 09:28:08 hkenken Exp $ */
+/* $NetBSD: imx51_ccmreg.h,v 1.4 2014/03/22 09:46:33 hkenken Exp $ */
/*
* Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -85,9 +85,17 @@
#define CCMC_CSCMR1 0x001c
#define CSCMR1_UART_CLK_SEL_SHIFT 24
#define CSCMR1_UART_CLK_SEL_MASK __BITS(25, CSCMR1_UART_CLK_SEL_SHIFT)
+#define CSCMR1_ESDHC1_CLK_SEL __BITS(22, 21)
+#define CSCMR1_ESDHC2_CLK_SEL __BIT(20)
+#define CSCMR1_ESDHC4_CLK_SEL __BIT(19)
+#define CSCMR1_ESDHC3_CLK_SEL __BITS(18, 16)
#define CSCMR1_CSPI_CLK_SEL __BITS(5, 4)
#define CCMC_CSCMR2 0x0020
#define CCMC_CSCDR1 0x0024
+#define CSCDR1_ESDHC3_CLK_PRED __BITS(24, 22)
+#define CSCDR1_ESDHC3_CLK_PODF __BITS(21, 19)
+#define CSCDR1_ESDHC1_CLK_PRED __BITS(18, 16)
+#define CSCDR1_ESDHC1_CLK_PODF __BITS(13, 11)
#define CSCDR1_UART_CLK_PRED_SHIFT 3
#define CSCDR1_UART_CLK_PRED_MASK __BITS(5, CSCDR1_UART_CLK_PRED_SHIFT)
#define CSCDR1_UART_CLK_PODF_SHIFT 0
Index: src/sys/arch/arm/imx/imx51_ccmvar.h
diff -u src/sys/arch/arm/imx/imx51_ccmvar.h:1.1 src/sys/arch/arm/imx/imx51_ccmvar.h:1.2
--- src/sys/arch/arm/imx/imx51_ccmvar.h:1.1 Tue Apr 17 09:33:31 2012
+++ src/sys/arch/arm/imx/imx51_ccmvar.h Sat Mar 22 09:46:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccmvar.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/* $NetBSD: imx51_ccmvar.h,v 1.2 2014/03/22 09:46:33 hkenken Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -56,6 +56,7 @@ enum imx51_clock {
IMX51CLK_ESDHC1_CLK_ROOT,
IMX51CLK_ESDHC2_CLK_ROOT,
IMX51CLK_ESDHC3_CLK_ROOT,
+ IMX51CLK_ESDHC4_CLK_ROOT,
IMX51CLK_UART_CLK_ROOT,
IMX51CLK_SSI1_CLK_ROOT,
IMX51CLK_SSI2_CLK_ROOT,
Index: src/sys/arch/arm/imx/imx51_esdhc.c
diff -u src/sys/arch/arm/imx/imx51_esdhc.c:1.1 src/sys/arch/arm/imx/imx51_esdhc.c:1.2
--- src/sys/arch/arm/imx/imx51_esdhc.c:1.1 Thu Apr 19 09:53:53 2012
+++ src/sys/arch/arm/imx/imx51_esdhc.c Sat Mar 22 09:46:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_esdhc.c,v 1.1 2012/04/19 09:53:53 bsh Exp $ */
+/* $NetBSD: imx51_esdhc.c,v 1.2 2014/03/22 09:46:33 hkenken Exp $ */
/*-
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
@@ -30,7 +30,9 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_esdhc.c,v 1.1 2012/04/19 09:53:53 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_esdhc.c,v 1.2 2014/03/22 09:46:33 hkenken Exp $");
+
+#include "opt_imx.h"
#include <sys/param.h>
#include <sys/device.h>
@@ -70,6 +72,8 @@ sdhc_match(device_t parent, cfdata_t cf,
switch (aa->aa_addr) {
case ESDHC1_BASE:
case ESDHC2_BASE:
+ case ESDHC3_BASE:
+ case ESDHC4_BASE:
return 1;
}
@@ -83,7 +87,7 @@ sdhc_attach(device_t parent, device_t se
struct axi_attach_args *aa = aux;
bus_space_tag_t iot = aa->aa_iot;
bus_space_handle_t ioh;
- u_int perclk;
+ u_int perclk = 0;
sc->sc_sdhc.sc_dev = self;
@@ -96,11 +100,22 @@ sdhc_attach(device_t parent, device_t se
aprint_normal(": SD/MMC host controller\n");
aprint_naive("\n");
-
-
sc->sc_sdhc.sc_host = sc->sc_hosts;
/* base clock frequency in kHz */
- perclk = imx51_get_clock(IMX51CLK_PERCLK_ROOT);
+ switch (aa->aa_addr) {
+ case ESDHC1_BASE:
+ perclk = imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT);
+ break;;
+ case ESDHC2_BASE:
+ perclk = imx51_get_clock(IMX51CLK_ESDHC2_CLK_ROOT);
+ break;;
+ case ESDHC3_BASE:
+ perclk = imx51_get_clock(IMX51CLK_ESDHC3_CLK_ROOT);
+ break;;
+ case ESDHC4_BASE:
+ perclk = imx51_get_clock(IMX51CLK_ESDHC4_CLK_ROOT);
+ break;;
+ }
sc->sc_sdhc.sc_clkbase = perclk / 1000;
sc->sc_sdhc.sc_flags |= SDHC_FLAG_HAVE_DVS |
SDHC_FLAG_NO_PWR0 |
