Module Name: src
Committed By: matt
Date: Sat Mar 29 23:32:41 UTC 2014
Modified Files:
src/sys/arch/arm/omap: omap2_reg.h omap3_ehci.c omap3_sdhc.c
omap3_uhhreg.h omap3_usbtllreg.h
Log Message:
OMAP4/OMAP5 changes.
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/omap/omap2_reg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/omap/omap3_ehci.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/omap/omap3_sdhc.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/omap/omap3_uhhreg.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/omap/omap3_usbtllreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/omap2_reg.h
diff -u src/sys/arch/arm/omap/omap2_reg.h:1.23 src/sys/arch/arm/omap/omap2_reg.h:1.24
--- src/sys/arch/arm/omap/omap2_reg.h:1.23 Thu Jun 20 05:27:31 2013
+++ src/sys/arch/arm/omap/omap2_reg.h Sat Mar 29 23:32:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.23 2013/06/20 05:27:31 matt Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.24 2014/03/29 23:32:41 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -363,6 +363,47 @@
#define TI_AM335X_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIVCHACK __BIT(5)
#define TI_AM335X_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIV __BITS(4,0)
+#define OMAP4_CM_L3INIT_CORE 0x5300 /* OMAP2_CM_BASE */
+#define OMAP5_CM_L3INIT_CORE 0x5600 /* OMAP2_CM_BASE */
+#define OMAP4_CM_L3INIT_HSMMC1_CLKCTRL 0x0008
+#define OMAP4_CM_L3INIT_HSMMC2_CLKCTRL 0x0030
+#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL_DIV2 __BIT(25)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL __BIT(24)
+#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_OPTFCLKEN_32KHZ_CLK __BIT(8)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE __BITS(1,0)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE_HW 2
+#define OMAP4_CM_L3INIT_HSI_CLKCTRL 0x0038
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL 0x0058
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P2 __BIT(25)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P1 __BIT(24)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_FUNC48M_CLK __BIT(15)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK __BIT(14)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P1_CLK __BIT(13)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK __BIT(12)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P1_CLK __BIT(11)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK __BIT(10)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK __BIT(9)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P1_CLK __BIT(8)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK __BIT(7)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK __BIT(6)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE_HW 2
+#define OMAP4_CM_L3INIT_USB_OTG_HS_CLKCTRL 0x0060
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_CLKSEL_60M __BIT(24)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_XCLK __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL 0x0068
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK __BIT(10)
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK __BIT(9)
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH0_CLK __BIT(8)
+#define OMAP5_CM_L3INIT_SATA_CLKCTRL 0x0088
+#define OMAP5_CM_L3INIT_SATA_CLKCTRL_OPTFCLKEN_REF_CLK __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL 0x00F0
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_REFCLK960M __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
+
/*
* Power Management registers base, offsets, and size
*/
@@ -763,8 +804,8 @@
#define OHCI1_BASE_OMAP3 0x48064400
#define EHCI1_BASE_OMAP3 0x48064800
-#define OHCI1_BASE_OMAP4 0x4A064800
-#define EHCI1_BASE_OMAP4 0x4A064C00
+#define OHCI1_BASE_OMAP4 0x4A064800 /* also OMAP5 */
+#define EHCI1_BASE_OMAP4 0x4A064C00 /* also OMAP5 */
/*
* SDRC
@@ -781,6 +822,7 @@
/*
* PL310 L2CC (44xx)
*/
+#define OMAP4_SCU_BASE 0x48240000
#define OMAP4_L2CC_BASE 0x48242000
#define OMAP4_L2CC_SIZE 0x00001000 /* 4KB */
@@ -788,6 +830,13 @@
#define AHCI1_BASE_OMAP5 0x4a140000
+/* These also apply to OMAP5 */
+#define OMAP4_WUGEN_BASE 0x48281000
+#define OMAP4_WKG_CONTROL_0 0x00000000
+#define OMAP4_WKG_CONTROL_1 0x00000400
+#define OMAP4_AUX_CORE_BOOT0 0x00000800
+#define OMAP4_AUX_CORE_BOOT1 0x00000804
+
#define OMAP5_PRM_FRAC_INCREMENTER_NUMERATOR 0x48243210
#define PRM_FRAC_INCR_NUM_ABE_LP_MODE __BITS(27,16)
#define PRM_FRAC_INCR_NUM_SYS_MODE __BITS(11,0)
Index: src/sys/arch/arm/omap/omap3_ehci.c
diff -u src/sys/arch/arm/omap/omap3_ehci.c:1.9 src/sys/arch/arm/omap/omap3_ehci.c:1.10
--- src/sys/arch/arm/omap/omap3_ehci.c:1.9 Tue Jun 18 15:23:18 2013
+++ src/sys/arch/arm/omap/omap3_ehci.c Sat Mar 29 23:32:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $ */
+/* $NetBSD: omap3_ehci.c,v 1.10 2014/03/29 23:32:41 matt Exp $ */
/*-
* Copyright (c) 2010-2012 Jared D. McNeill <[email protected]>
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.10 2014/03/29 23:32:41 matt Exp $");
#include "locators.h"
@@ -110,7 +110,7 @@ __KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c
/* USBTLL module */
#ifdef OMAP_3XXX
#define USBTLL_BASE 0x48062000
-#elif defined(OMAP4)
+#elif defined(OMAP4) || defined(OMAP5)
#define USBTLL_BASE 0x4a062000
#endif
#define USBTLL_SIZE 0x1000
@@ -118,7 +118,7 @@ __KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c
/* HS USB HOST module */
#ifdef OMAP_3XXX
#define UHH_BASE 0x48064000
-#elif defined(OMAP4)
+#elif defined(OMAP4) || defined(OMAP5)
#define UHH_BASE 0x4a064000
#endif
#define UHH_SIZE 0x1000
@@ -127,6 +127,57 @@ enum omap3_ehci_port_mode {
OMAP3_EHCI_PORT_MODE_NONE,
OMAP3_EHCI_PORT_MODE_PHY,
OMAP3_EHCI_PORT_MODE_TLL,
+ OMAP3_EHCI_PORT_MODE_HSIC,
+};
+
+static const uint32_t uhh_map[3][4] = {
+#if defined(OMAP4) || defined(OMAP5)
+ {
+ [OMAP3_EHCI_PORT_MODE_NONE] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P1_MODE),
+ [OMAP3_EHCI_PORT_MODE_PHY] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P1_MODE),
+ [OMAP3_EHCI_PORT_MODE_TLL] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P1_MODE),
+ [OMAP3_EHCI_PORT_MODE_HSIC] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P1_MODE),
+ }, {
+ [OMAP3_EHCI_PORT_MODE_NONE] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P2_MODE),
+ [OMAP3_EHCI_PORT_MODE_PHY] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P2_MODE),
+ [OMAP3_EHCI_PORT_MODE_TLL] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P2_MODE),
+ [OMAP3_EHCI_PORT_MODE_HSIC] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P2_MODE),
+ }, {
+ [OMAP3_EHCI_PORT_MODE_NONE] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P3_MODE),
+ [OMAP3_EHCI_PORT_MODE_PHY] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P3_MODE),
+ [OMAP3_EHCI_PORT_MODE_TLL] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P3_MODE),
+ [OMAP3_EHCI_PORT_MODE_HSIC] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P3_MODE),
+ }
+#else
+ {
+ [OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_PHY] = 0,
+ [OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
+ }, {
+ [OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_PHY] = 0,
+ [OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
+ }, {
+ [OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_PHY] = 0,
+ [OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
+ },
+#endif
};
struct omap3_ehci_softc {
@@ -155,6 +206,9 @@ struct omap3_ehci_softc {
static void omap3_dpll5_init(struct omap3_ehci_softc *);
static void omap3_usbhost_init(struct omap3_ehci_softc *, int);
#endif
+#if defined(OMAP4) || defined(OMAP5)
+static void omap4_usbhost_init(struct omap3_ehci_softc *, int);
+#endif
static void usbtll_reset(struct omap3_ehci_softc *);
static void usbtll_power(struct omap3_ehci_softc *, bool);
static void usbtll_init(struct omap3_ehci_softc *, int);
@@ -297,7 +351,7 @@ omap3_ehci_match(device_t parent, cfdata
if (obio->obio_addr == EHCI1_BASE_OMAP3)
return 1;
#endif
-#ifdef OMAP4
+#if defined(OMAP4) || defined(OMAP5)
if (obio->obio_addr == EHCI1_BASE_OMAP4)
return 1;
#endif
@@ -318,6 +372,14 @@ omap3_ehci_get_port_mode(prop_dictionary
} else if (strcmp(s, "tll") == 0) {
mode = OMAP3_EHCI_PORT_MODE_TLL;
#endif
+#if defined(OMAP4) || defined(OMAP5)
+ } else if (strcmp(s, "hsic") == 0) {
+ mode = OMAP3_EHCI_PORT_MODE_HSIC;
+#endif
+ } else if (strcmp(s, "none") == 0) {
+ mode = OMAP3_EHCI_PORT_MODE_NONE;
+ } else {
+ panic("%s: unknown port mode %s", __func__, s);
}
}
@@ -415,6 +477,9 @@ omap3_ehci_attach(device_t parent, devic
omap3_usbhost_init(sc, 1);
#endif /* OMAP_3XXX */
+#if defined(OMAP4) || defined(OMAP5)
+ omap4_usbhost_init(sc, 1);
+#endif
sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
@@ -587,6 +652,40 @@ omap3_usbhost_init(struct omap3_ehci_sof
}
#endif /* OMAP_3XXX */
+#if defined(OMAP4) || defined(OMAP5)
+static void
+omap4_usbhost_init(struct omap3_ehci_softc *sc, int enable)
+{
+ bus_space_tag_t iot = sc->sc.iot;
+ bus_space_handle_t ioh;
+ uint32_t val;
+ int err __diagused;
+#ifdef OMAP5
+ bus_size_t off = OMAP5_CM_L3INIT_CORE;
+#elif defined(OMAP4)
+ bus_size_t off = OMAP4_CM_L3INIT_CORE;
+#endif
+
+ err = bus_space_map(iot, OMAP2_CM_BASE + off, 0x100, 0, &ioh);
+ KASSERT(err == 0);
+
+ val = bus_space_read_4(iot, ioh, OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL);
+ val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK;
+ bus_space_write_4(iot, ioh, OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL, val);
+
+ val = bus_space_read_4(iot, ioh, OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL);
+ val |= OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK
+ | OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK;
+ bus_space_write_4(iot, ioh, OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL, val);
+
+ bus_space_unmap(iot, ioh, 0x100);
+}
+#endif /* OMAP4 || OMAP5 */
static void
usbtll_reset(struct omap3_ehci_softc *sc)
{
@@ -648,28 +747,48 @@ usbtll_init(struct omap3_ehci_softc *sc,
static void
uhh_power(struct omap3_ehci_softc *sc, bool on)
{
- uint32_t v;
int retry = 5000;
+
+ uint32_t v;
+ v = UHH_READ4(sc, UHH_REVISION);
+ const int vers = UHH_REVISION_MAJOR(v);
if (on) {
v = UHH_READ4(sc, UHH_SYSCONFIG);
- v &= ~(UHH_SYSCONFIG_SIDLEMODE_MASK|UHH_SYSCONFIG_MIDLEMODE_MASK);
- v |= UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY;
- v |= UHH_SYSCONFIG_CLOCKACTIVITY;
- v |= UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE;
- v |= UHH_SYSCONFIG_ENAWAKEUP;
- v &= ~UHH_SYSCONFIG_AUTOIDLE;
+ if (vers >= UHH_REVISION_VERS2) {
+ v &= ~UHH4_SYSCONFIG_STANDBYMODE;
+ v |= UHH4_SYSCONFIG_STANDBYMODE_SMARTSTANDBY;
+ v &= ~UHH4_SYSCONFIG_SIDLEMODE;
+ v |= UHH4_SYSCONFIG_SIDLEMODE_SMARTIDLE;
+ } else {
+ v &= ~UHH3_SYSCONFIG_MIDLEMODE_MASK;
+ v |= UHH3_SYSCONFIG_MIDLEMODE_SMARTSTANDBY;
+ v &= ~UHH3_SYSCONFIG_SIDLEMODE_MASK;
+ v |= UHH3_SYSCONFIG_SIDLEMODE_SMARTIDLE;
+ v |= UHH3_SYSCONFIG_CLOCKACTIVITY;
+ v |= UHH3_SYSCONFIG_ENAWAKEUP;
+ v &= ~UHH3_SYSCONFIG_AUTOIDLE;
+ }
UHH_WRITE4(sc, UHH_SYSCONFIG, v);
v = UHH_READ4(sc, UHH_SYSCONFIG);
} else {
v = UHH_READ4(sc, UHH_SYSCONFIG);
- v |= UHH_SYSCONFIG_SOFTRESET;
+ if (vers >= UHH_REVISION_VERS2) {
+ v |= UHH4_SYSCONFIG_SOFTRESET;
+ } else {
+ v |= UHH3_SYSCONFIG_SOFTRESET;
+ }
UHH_WRITE4(sc, UHH_SYSCONFIG, v);
do {
v = UHH_READ4(sc, UHH_SYSSTATUS);
- if (v & UHH_SYSSTATUS_RESETDONE_ALL)
- break;
+ if (vers >= UHH_REVISION_VERS2) {
+ if ((v & UHH4_SYSSTATUS_RESETDONE_ALL) == 0)
+ break;
+ } else {
+ if (v & UHH3_SYSSTATUS_RESETDONE_ALL)
+ break;
+ }
delay(10);
} while (retry-- > 0);
if (retry == 0)
@@ -699,18 +818,18 @@ uhh_portconfig(struct omap3_ehci_softc *
&& sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_NONE)
v &= ~UHH_HOSTCONFIG_P3_CONNECT_STATUS;
- v &= ~(UHH_HOSTCONFIG_P1_ULPI_BYPASS |UHH_HOSTCONFIG_P2_ULPI_BYPASS
- |UHH_HOSTCONFIG_P2_ULPI_BYPASS);
- if (sc->sc_portconfig[0].mode != OMAP3_EHCI_PORT_MODE_PHY)
- v |= UHH_HOSTCONFIG_P1_ULPI_BYPASS;
-
- if (sc->sc_nports > 1
- && sc->sc_portconfig[1].mode != OMAP3_EHCI_PORT_MODE_PHY)
- v |= UHH_HOSTCONFIG_P2_ULPI_BYPASS;
+ v &= ~(UHH_HOSTCONFIG_P1_ULPI_BYPASS|UHH_HOSTCONFIG_P2_ULPI_BYPASS
+ |UHH_HOSTCONFIG_P3_ULPI_BYPASS);
+ v &= ~(UHH_HOSTCONFIG_P1_MODE|UHH_HOSTCONFIG_P2_MODE
+ |UHH_HOSTCONFIG_P3_MODE);
- if (sc->sc_nports > 2
- && sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_PHY)
- v |= UHH_HOSTCONFIG_P3_ULPI_BYPASS;
+ v |= uhh_map[0][sc->sc_portconfig[0].mode];
+ if (sc->sc_nports > 1) {
+ v |= uhh_map[1][sc->sc_portconfig[1].mode];
+ if (sc->sc_nports > 2) {
+ v |= uhh_map[2][sc->sc_portconfig[2].mode];
+ }
+ }
UHH_WRITE4(sc, UHH_HOSTCONFIG, v);
}
Index: src/sys/arch/arm/omap/omap3_sdhc.c
diff -u src/sys/arch/arm/omap/omap3_sdhc.c:1.13 src/sys/arch/arm/omap/omap3_sdhc.c:1.14
--- src/sys/arch/arm/omap/omap3_sdhc.c:1.13 Mon Aug 5 21:55:47 2013
+++ src/sys/arch/arm/omap/omap3_sdhc.c Sat Mar 29 23:32:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_sdhc.c,v 1.13 2013/08/05 21:55:47 jmcneill Exp $ */
+/* $NetBSD: omap3_sdhc.c,v 1.14 2014/03/29 23:32:41 matt Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.13 2013/08/05 21:55:47 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.14 2014/03/29 23:32:41 matt Exp $");
#include "opt_omap.h"
@@ -119,7 +119,7 @@ obiosdhc_match(device_t parent, cfdata_t
|| oa->obio_addr == SDMMC2_BASE_3530
|| oa->obio_addr == SDMMC3_BASE_3530)
return 1;
-#elif defined(OMAP4)
+#elif defined(OMAP4) || defined(OMAP5)
if (oa->obio_addr == SDMMC1_BASE_4430
|| oa->obio_addr == SDMMC2_BASE_4430
|| oa->obio_addr == SDMMC3_BASE_4430
Index: src/sys/arch/arm/omap/omap3_uhhreg.h
diff -u src/sys/arch/arm/omap/omap3_uhhreg.h:1.2 src/sys/arch/arm/omap/omap3_uhhreg.h:1.3
--- src/sys/arch/arm/omap/omap3_uhhreg.h:1.2 Tue Jun 18 15:01:49 2013
+++ src/sys/arch/arm/omap/omap3_uhhreg.h Sat Mar 29 23:32:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_uhhreg.h,v 1.2 2013/06/18 15:01:49 matt Exp $ */
+/* $NetBSD: omap3_uhhreg.h,v 1.3 2014/03/29 23:32:41 matt Exp $ */
/*-
* Copyright (c) 2010 Jared D. McNeill <[email protected]>
@@ -29,33 +29,51 @@
#define _OMAP3_UHHREG_H
/* 32-bit */
-#define UHH_REVISION 0x00
-#define UHH_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
-#define UHH_REVISION_MINOR(x) ((x) & 0xf)
-
-#define UHH_SYSCONFIG 0x10
-#define UHH_SYSCONFIG_MIDLEMODE_MASK 0x00003000
-#define UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x00002000
-#define UHH_SYSCONFIG_CLOCKACTIVITY 0x00000100
-#define UHH_SYSCONFIG_SIDLEMODE_MASK 0x00000018
-#define UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE 0x00000008
-#define UHH_SYSCONFIG_ENAWAKEUP 0x00000004
-#define UHH_SYSCONFIG_SOFTRESET 0x00000002
-#define UHH_SYSCONFIG_AUTOIDLE 0x00000001
-
-#define UHH_SYSSTATUS 0x14
-#define UHH_SYSSTATUS_EHCI_RESETDONE 0x00000004
-#define UHH_SYSSTATUS_OHCI_RESETDONE 0x00000002
-#define UHH_SYSSTATUS_RESETDONE 0x00000001
-#define UHH_SYSSTATUS_RESETDONE_ALL \
+#define UHH_REVISION 0x00
+#define UHH_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
+#define UHH_REVISION_MINOR(x) ((x) & 0xf)
+#define UHH_REVISION_VERS2 2
+
+#define UHH_HWINFO 0x04
+#define UHH_HWINFO_SAR_CNTX_SIZE __BITS(9,0)
+
+#define UHH_SYSCONFIG 0x10
+#define UHH3_SYSCONFIG_MIDLEMODE_MASK 0x00003000
+#define UHH3_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x00002000
+#define UHH3_SYSCONFIG_CLOCKACTIVITY 0x00000100
+#define UHH3_SYSCONFIG_SIDLEMODE_MASK 0x00000018
+#define UHH3_SYSCONFIG_SIDLEMODE_SMARTIDLE 0x00000008
+#define UHH3_SYSCONFIG_ENAWAKEUP 0x00000004
+#define UHH3_SYSCONFIG_SOFTRESET 0x00000002
+#define UHH3_SYSCONFIG_AUTOIDLE 0x00000001
+
+#define UHH4_SYSCONFIG_STANDBYMODE __BITS(5,4)
+#define UHH4_SYSCONFIG_STANDBYMODE_SMARTSTANDBY __SHIFTIN(2,UHH4_SYSCONFIG_STANDBYMODE)
+#define UHH4_SYSCONFIG_SIDLEMODE __BITS(3,2)
+#define UHH4_SYSCONFIG_SIDLEMODE_SMARTIDLE __SHIFTIN(2,UHH4_SYSCONFIG_SIDLEMODE)
+#define UHH4_SYSCONFIG_SOFTRESET __BIT(0)
+
+#define UHH_SYSSTATUS 0x14
+#define UHH_SYSSTATUS_EHCI_RESETDONE 0x00000004
+#define UHH_SYSSTATUS_OHCI_RESETDONE 0x00000002
+#define UHH3_SYSSTATUS_RESETDONE 0x00000001
+#define UHH3_SYSSTATUS_RESETDONE_ALL \
(UHH_SYSSTATUS_EHCI_RESETDONE | \
UHH_SYSSTATUS_OHCI_RESETDONE | \
- UHH_SYSSTATUS_RESETDONE)
+ UHH3_SYSSTATUS_RESETDONE)
+#define UHH4_SYSSTATUS_RESETDONE_ALL \
+ (UHH_SYSSTATUS_EHCI_RESETDONE | \
+ UHH_SYSSTATUS_OHCI_RESETDONE)
-#define UHH_HOSTCONFIG 0x40
+#define UHH_HOSTCONFIG 0x40
#define UHH_HOSTCONFIG_APP_START_CLK __BIT(31)
+#define UHH_HOSTCONFIG_P3_MODE __BITS(21,20)
#define UHH_HOSTCONFIG_P2_MODE __BITS(19,18)
#define UHH_HOSTCONFIG_P1_MODE __BITS(17,16)
+#define UHH_HOSTCONFIG_PMODE_ULPI_PHY 0
+#define UHH_HOSTCONFIG_PMODE_UTMI 1
+#define UHH_HOSTCONFIG_PMODE__RSVD2 2
+#define UHH_HOSTCONFIG_PMODE_HSIC 3
#define UHH_HOSTCONFIG_P3_ULPI_BYPASS __BIT(12)
#define UHH_HOSTCONFIG_P2_ULPI_BYPASS __BIT(11)
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS __BIT(10)
@@ -77,4 +95,6 @@
#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE 0x00000040
#define UHH_DEBUG_CSR_EHCI_FLADJ 0x0000003f
+#define UHH_SAR_CNTX_BASE 0x100
+
#endif /* !_OMAP3_UHHREG_H */
Index: src/sys/arch/arm/omap/omap3_usbtllreg.h
diff -u src/sys/arch/arm/omap/omap3_usbtllreg.h:1.1 src/sys/arch/arm/omap/omap3_usbtllreg.h:1.2
--- src/sys/arch/arm/omap/omap3_usbtllreg.h:1.1 Wed Dec 12 00:33:45 2012
+++ src/sys/arch/arm/omap/omap3_usbtllreg.h Sat Mar 29 23:32:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_usbtllreg.h,v 1.1 2012/12/12 00:33:45 matt Exp $ */
+/* $NetBSD: omap3_usbtllreg.h,v 1.2 2014/03/29 23:32:41 matt Exp $ */
/*-
* Copyright (c) 2010 Jared D. McNeill <[email protected]>
@@ -33,6 +33,9 @@
#define USBTLL_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
#define USBTLL_REVISION_MINOR(x) ((x) & 0xf)
+#define USBTLL_HWINFO 0x04
+#define USBTLL_HWINFO_SAR_CNTX_SIZE __BITS(7,0)
+
#define USBTLL_SYSCONFIG 0x10
#define USBTLL_SYSCONFIG_CLOCKACTIVITY 0x00000100
#define USBTLL_SYSCONFIG_SIDLEMODE 0x00000018
@@ -81,6 +84,8 @@
#define USBTLL_CHANNEL_CONF_CHANMODE 0x00000006
#define USBTLL_CHANNEL_CONF_CHANEN 0x00000001
+#define USBTLL_SAR_CNTX(i) (0x400 + (0x04 * (i)))
+
/* 8-bit */
#define ULPI_VENDOR_ID_LO(i) (0x100 * (i) + 0)
#define ULPI_VENDOR_ID_HI(i) (0x100 * (i) + 1)
