Module Name: src
Committed By: matt
Date: Thu Apr 3 17:09:48 UTC 2014
Modified Files:
src/sys/arch/arm/omap: omap2_reg.h
Log Message:
Consistently use #define<tab>
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/omap/omap2_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/omap2_reg.h
diff -u src/sys/arch/arm/omap/omap2_reg.h:1.24 src/sys/arch/arm/omap/omap2_reg.h:1.25
--- src/sys/arch/arm/omap/omap2_reg.h:1.24 Sat Mar 29 23:32:41 2014
+++ src/sys/arch/arm/omap/omap2_reg.h Thu Apr 3 17:09:48 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.24 2014/03/29 23:32:41 matt Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.25 2014/04/03 17:09:48 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -30,7 +30,7 @@
*/
#ifndef _ARM_OMAP_OMAP2_REG_H_
-#define _ARM_OMAP_OMAP2_REG_H_
+#define _ARM_OMAP_OMAP2_REG_H_
#include "opt_omap.h"
@@ -41,132 +41,132 @@
/*
* L4 Interconnect WAKEUP address space
*/
-#define OMAP2430_L4_CORE_BASE 0x48000000
-#define OMAP2430_L4_CORE_SIZE (16 << 20) /* 16 MB */
+#define OMAP2430_L4_CORE_BASE 0x48000000
+#define OMAP2430_L4_CORE_SIZE (16 << 20) /* 16 MB */
-#define OMAP2430_L4_WAKEUP_BASE 0x49000000
-#define OMAP2430_L4_WAKEUP_SIZE (8 << 20) /* 8 MB */
+#define OMAP2430_L4_WAKEUP_BASE 0x49000000
+#define OMAP2430_L4_WAKEUP_SIZE (8 << 20) /* 8 MB */
-#define OMAP3430_L4_CORE_BASE 0x48000000
-#define OMAP3430_L4_CORE_SIZE 0x01000000 /* 16 MB */
+#define OMAP3430_L4_CORE_BASE 0x48000000
+#define OMAP3430_L4_CORE_SIZE 0x01000000 /* 16 MB */
-#define OMAP3530_L4_CORE_BASE 0x48000000
-#define OMAP3530_L4_CORE_SIZE 0x01000000 /* 16 MB */
+#define OMAP3530_L4_CORE_BASE 0x48000000
+#define OMAP3530_L4_CORE_SIZE 0x01000000 /* 16 MB */
/* OMAP3 processors */
-#define OMAP3430_L4_WAKEUP_BASE 0x48300000
-#define OMAP3430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
+#define OMAP3430_L4_WAKEUP_BASE 0x48300000
+#define OMAP3430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
-#define OMAP3430_L4_PERIPHERAL_BASE 0x49000000
-#define OMAP3430_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
+#define OMAP3430_L4_PERIPHERAL_BASE 0x49000000
+#define OMAP3430_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
-#define OMAP3430_L4_EMULATION_BASE 0x54000000
-#define OMAP3430_L4_EMULATION_SIZE 0x00800000 /* 8MB */
+#define OMAP3430_L4_EMULATION_BASE 0x54000000
+#define OMAP3430_L4_EMULATION_SIZE 0x00800000 /* 8MB */
-#define OMAP3530_L4_WAKEUP_BASE 0x48300000
-#define OMAP3530_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
+#define OMAP3530_L4_WAKEUP_BASE 0x48300000
+#define OMAP3530_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
-#define OMAP3530_L4_PERIPHERAL_BASE 0x49000000
-#define OMAP3530_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
+#define OMAP3530_L4_PERIPHERAL_BASE 0x49000000
+#define OMAP3530_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
-#define OMAP3530_L4_EMULATION_BASE 0x54000000
-#define OMAP3530_L4_EMULATION_SIZE 0x00800000 /* 8MB */
+#define OMAP3530_L4_EMULATION_BASE 0x54000000
+#define OMAP3530_L4_EMULATION_SIZE 0x00800000 /* 8MB */
/* OMAP4 processors */
-#define OMAP4430_L4_CORE_BASE 0x4A000000
-#define OMAP4430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
+#define OMAP4430_L4_CORE_BASE 0x4A000000
+#define OMAP4430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
-#define OMAP4430_L4_WAKEUP_BASE 0x4A300000
-#define OMAP4430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
+#define OMAP4430_L4_WAKEUP_BASE 0x4A300000
+#define OMAP4430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
-#define OMAP4430_L4_PERIPHERAL_BASE 0x48000000
-#define OMAP4430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+#define OMAP4430_L4_PERIPHERAL_BASE 0x48000000
+#define OMAP4430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
-#define OMAP4430_L4_ABE_BASE 0x49000000 /* Actually L3 */
-#define OMAP4430_L4_ABE_SIZE 0x01000000 /* 16MB */
+#define OMAP4430_L4_ABE_BASE 0x49000000 /* Actually L3 */
+#define OMAP4430_L4_ABE_SIZE 0x01000000 /* 16MB */
-#define OMAP4430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
-#define OMAP4430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP4430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
+#define OMAP4430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
-#define OMAP4430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
-#define OMAP4430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP4430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
+#define OMAP4430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
/* OMAP5 processors */
-#define OMAP5430_L4_CORE_BASE 0x4A000000
-#define OMAP5430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
+#define OMAP5430_L4_CORE_BASE 0x4A000000
+#define OMAP5430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
-#define OMAP5430_L4_WAKEUP_BASE 0x4AE00000
-#define OMAP5430_L4_WAKEUP_SIZE 0x00200000 /* 2M */
+#define OMAP5430_L4_WAKEUP_BASE 0x4AE00000
+#define OMAP5430_L4_WAKEUP_SIZE 0x00200000 /* 2M */
-#define OMAP5430_L4_PERIPHERAL_BASE 0x48000000
-#define OMAP5430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+#define OMAP5430_L4_PERIPHERAL_BASE 0x48000000
+#define OMAP5430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
-#define OMAP5430_L4_ABE_BASE 0x49000000 /* Actually L3 */
-#define OMAP5430_L4_ABE_SIZE 0x01000000 /* 16MB */
+#define OMAP5430_L4_ABE_BASE 0x49000000 /* Actually L3 */
+#define OMAP5430_L4_ABE_SIZE 0x01000000 /* 16MB */
-#define OMAP5430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
-#define OMAP5430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP5430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
+#define OMAP5430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
-#define OMAP5430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
-#define OMAP5430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP5430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
+#define OMAP5430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
/* TI Sitara AM335x (OMAP like) */
-#define TI_AM335X_L4_WAKEUP_BASE 0x44C00000
-#define TI_AM335X_L4_WAKEUP_SIZE 0x00400000 /* 4MB */
+#define TI_AM335X_L4_WAKEUP_BASE 0x44C00000
+#define TI_AM335X_L4_WAKEUP_SIZE 0x00400000 /* 4MB */
-#define TI_AM335X_L4_PERIPHERAL_BASE 0x48000000
-#define TI_AM335X_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+#define TI_AM335X_L4_PERIPHERAL_BASE 0x48000000
+#define TI_AM335X_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
-#define TI_AM335X_L4_FAST_BASE 0x4A000000
-#define TI_AM335X_L4_FAST_SIZE 0x01000000 /* 16MB */
+#define TI_AM335X_L4_FAST_BASE 0x4A000000
+#define TI_AM335X_L4_FAST_SIZE 0x01000000 /* 16MB */
-#define TI_AM335X_EMIF1_BASE 0x4C000000
-#define TI_AM335X_EMIF1_SIZE 0x00100000 /* 4KB pad to 1MB */
+#define TI_AM335X_EMIF1_BASE 0x4C000000
+#define TI_AM335X_EMIF1_SIZE 0x00100000 /* 4KB pad to 1MB */
/* TI Sitara DM37xx (OMAP like) */
-#define TI_DM37XX_L4_CORE_BASE 0x48000000
-#define TI_DM37XX_L4_CORE_SIZE 0x01000000 /* 16MB */
+#define TI_DM37XX_L4_CORE_BASE 0x48000000
+#define TI_DM37XX_L4_CORE_SIZE 0x01000000 /* 16MB */
-#define TI_DM37XX_L4_WAKEUP_BASE 0x48300000
-#define TI_DM37XX_L4_WAKEUP_SIZE 0x00010000 /* 64KB */
+#define TI_DM37XX_L4_WAKEUP_BASE 0x48300000
+#define TI_DM37XX_L4_WAKEUP_SIZE 0x00010000 /* 64KB */
-#define TI_DM37XX_L4_PERIPHERAL_BASE 0x49000000
-#define TI_DM37XX_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+#define TI_DM37XX_L4_PERIPHERAL_BASE 0x49000000
+#define TI_DM37XX_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
-#define TI_DM37XX_L4_EMULATION_BASE 0x54000000
-#define TI_DM37XX_L4_EMULATION_SIZE 0x00800000 /* 8MB */
+#define TI_DM37XX_L4_EMULATION_BASE 0x54000000
+#define TI_DM37XX_L4_EMULATION_SIZE 0x00800000 /* 8MB */
/*
* Clock Management registers base, offsets, and size
*/
#ifdef OMAP_2430
-#define OMAP2_CM_BASE 0x49006000
+#define OMAP2_CM_BASE 0x49006000
#endif
#ifdef OMAP_2420
-#define OMAP2_CM_BASE 0x48008000
+#define OMAP2_CM_BASE 0x48008000
#endif
#ifdef OMAP_3430
-#define OMAP2_CM_BASE (OMAP3430_L4_CORE_BASE + 0x04000)
+#define OMAP2_CM_BASE (OMAP3430_L4_CORE_BASE + 0x04000)
#endif
#ifdef OMAP_3530
-#define OMAP2_CM_BASE (OMAP3530_L4_CORE_BASE + 0x04000)
+#define OMAP2_CM_BASE (OMAP3530_L4_CORE_BASE + 0x04000)
#endif
#ifdef OMAP_4430
-#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000)
+#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000)
#endif
#ifdef OMAP_5430
-#define OMAP2_CM_BASE (OMAP5430_L4_CORE_BASE + 0x04000)
+#define OMAP2_CM_BASE (OMAP5430_L4_CORE_BASE + 0x04000)
#endif
#ifdef TI_AM335X
-#define OMAP2_CM_BASE (TI_AM335X_L4_WAKEUP_BASE + 0x200000)
+#define OMAP2_CM_BASE (TI_AM335X_L4_WAKEUP_BASE + 0x200000)
#endif
#ifdef TI_DM37XX
-#define OMAP2_CM_BASE 0x48004000
+#define OMAP2_CM_BASE 0x48004000
#endif
#define OMAP2_CM_CLKSEL_MPU 0x140
@@ -175,7 +175,7 @@
#define OMAP2_CM_ICLKEN1_CORE 0x210
#define OMAP2_CM_ICLKEN2_CORE 0x214
#define OMAP2_CM_CLKSEL2_CORE 0x244
-#define OMAP3_CM_IDLEST1_CORE 0xa20
+#define OMAP3_CM_IDLEST1_CORE 0xa20
#define OMAP2_CM_SIZE (0x1000)
/*
@@ -187,38 +187,38 @@
/*
* bit defines for OMAP2_CM_FCLKEN2_CORE
*/
-#define OMAP2_CM_FCLKEN1_CORE_EN_DSS1 __BIT(0)
-#define OMAP2_CM_FCLKEN1_CORE_EN_DSS2 __BIT(1)
-#define OMAP2_CM_FCLKEN1_CORE_EN_TV __BIT(2)
-#define OMAP2_CM_FCLKEN1_CORE_RESa __BIT(3)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT2 __BIT(4)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT3 __BIT(5)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT4 __BIT(6)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT5 __BIT(7)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT6 __BIT(8)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT7 __BIT(9)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT8 __BIT(10)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT9 __BIT(11)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT10 __BIT(12)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT11 __BIT(13)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT12 __BIT(14)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MCBSP1 __BIT(15)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MCBSP2 __BIT(16)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MCSPI1 __BIT(17)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MCSPI2 __BIT(18)
-#define OMAP2_CM_FCLKEN1_CORE_RESb __BITS(20,19)
-#define OMAP2_CM_FCLKEN1_CORE_EN_UART1 __BIT(21)
-#define OMAP2_CM_FCLKEN1_CORE_EN_UART2 __BIT(22)
-#define OMAP2_CM_FCLKEN1_CORE_EN_HDQ __BIT(23)
-#define OMAP2_CM_FCLKEN1_CORE_RESc __BIT(24)
-#define OMAP2_CM_FCLKEN1_CORE_EN_FAC __BIT(25)
-#define OMAP2_CM_FCLKEN1_CORE_RESd __BIT(26)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MSPRO __BIT(27)
-#define OMAP2_CM_FCLKEN1_CORE_RESe __BIT(28)
-#define OMAP2_CM_FCLKEN1_CORE_EN_WDT4 __BIT(29)
-#define OMAP2_CM_FCLKEN1_CORE_RESf __BIT(30)
-#define OMAP2_CM_FCLKEN1_CORE_EN_CAM __BIT(31)
-#define OMAP2_CM_FCLKEN1_CORE_RESV \
+#define OMAP2_CM_FCLKEN1_CORE_EN_DSS1 __BIT(0)
+#define OMAP2_CM_FCLKEN1_CORE_EN_DSS2 __BIT(1)
+#define OMAP2_CM_FCLKEN1_CORE_EN_TV __BIT(2)
+#define OMAP2_CM_FCLKEN1_CORE_RESa __BIT(3)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT2 __BIT(4)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT3 __BIT(5)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT4 __BIT(6)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT5 __BIT(7)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT6 __BIT(8)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT7 __BIT(9)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT8 __BIT(10)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT9 __BIT(11)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT10 __BIT(12)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT11 __BIT(13)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT12 __BIT(14)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MCBSP1 __BIT(15)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MCBSP2 __BIT(16)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MCSPI1 __BIT(17)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MCSPI2 __BIT(18)
+#define OMAP2_CM_FCLKEN1_CORE_RESb __BITS(20,19)
+#define OMAP2_CM_FCLKEN1_CORE_EN_UART1 __BIT(21)
+#define OMAP2_CM_FCLKEN1_CORE_EN_UART2 __BIT(22)
+#define OMAP2_CM_FCLKEN1_CORE_EN_HDQ __BIT(23)
+#define OMAP2_CM_FCLKEN1_CORE_RESc __BIT(24)
+#define OMAP2_CM_FCLKEN1_CORE_EN_FAC __BIT(25)
+#define OMAP2_CM_FCLKEN1_CORE_RESd __BIT(26)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MSPRO __BIT(27)
+#define OMAP2_CM_FCLKEN1_CORE_RESe __BIT(28)
+#define OMAP2_CM_FCLKEN1_CORE_EN_WDT4 __BIT(29)
+#define OMAP2_CM_FCLKEN1_CORE_RESf __BIT(30)
+#define OMAP2_CM_FCLKEN1_CORE_EN_CAM __BIT(31)
+#define OMAP2_CM_FCLKEN1_CORE_RESV \
(OMAP2_CM_FCLKEN1_CORE_RESa \
|OMAP2_CM_FCLKEN1_CORE_RESb \
|OMAP2_CM_FCLKEN1_CORE_RESc \
@@ -230,25 +230,25 @@
/*
* bit defines for OMAP2_CM_FCLKEN2_CORE
*/
-#define OMAP2_CM_FCLKEN2_CORE_EN_USB __BIT(0)
-#define OMAP2_CM_FCLKEN2_CORE_EN_SSI __BIT(1)
-#define OMAP2_CM_FCLKEN2_CORE_EN_UART3 __BIT(2)
-#define OMAP2_CM_FCLKEN2_CORE_EN_MCBSP3 __BIT(3)
-#define OMAP2_CM_FCLKEN2_CORE_EN_MCBSP4 __BIT(4)
-#define OMAP2_CM_FCLKEN2_CORE_EN_MCBSP5 __BIT(5)
-#define OMAP2_CM_FCLKEN2_CORE_RESa __BIT(6)
-#define OMAP2_CM_FCLKEN2_CORE_EN_MMCHS1 __BIT(7)
-#define OMAP2_CM_FCLKEN2_CORE_EN_MMCHS2 __BIT(8)
-#define OMAP2_CM_FCLKEN2_CORE_EN_NCSPI3 __BIT(9)
-#define OMAP2_CM_FCLKEN2_CORE_EN_GPIO5 __BIT(10)
-#define OMAP2_CM_FCLKEN2_CORE_RESb __BITS(15,11)
-#define OMAP2_CM_FCLKEN2_CORE_EN_MMCHSDB1 __BIT(16)
-#define OMAP2_CM_FCLKEN2_CORE_EN_MMCHSDB2 __BIT(17)
-#define OMAP2_CM_FCLKEN2_CORE_RESc __BIT(18)
-#define OMAP2_CM_FCLKEN2_CORE_I2CHS1 __BIT(19)
-#define OMAP2_CM_FCLKEN2_CORE_I2CHS2 __BIT(20)
-#define OMAP2_CM_FCLKEN2_CORE_RESd __BITS(31,21)
-#define OMAP2_CM_FCLKEN2_CORE_RESV \
+#define OMAP2_CM_FCLKEN2_CORE_EN_USB __BIT(0)
+#define OMAP2_CM_FCLKEN2_CORE_EN_SSI __BIT(1)
+#define OMAP2_CM_FCLKEN2_CORE_EN_UART3 __BIT(2)
+#define OMAP2_CM_FCLKEN2_CORE_EN_MCBSP3 __BIT(3)
+#define OMAP2_CM_FCLKEN2_CORE_EN_MCBSP4 __BIT(4)
+#define OMAP2_CM_FCLKEN2_CORE_EN_MCBSP5 __BIT(5)
+#define OMAP2_CM_FCLKEN2_CORE_RESa __BIT(6)
+#define OMAP2_CM_FCLKEN2_CORE_EN_MMCHS1 __BIT(7)
+#define OMAP2_CM_FCLKEN2_CORE_EN_MMCHS2 __BIT(8)
+#define OMAP2_CM_FCLKEN2_CORE_EN_NCSPI3 __BIT(9)
+#define OMAP2_CM_FCLKEN2_CORE_EN_GPIO5 __BIT(10)
+#define OMAP2_CM_FCLKEN2_CORE_RESb __BITS(15,11)
+#define OMAP2_CM_FCLKEN2_CORE_EN_MMCHSDB1 __BIT(16)
+#define OMAP2_CM_FCLKEN2_CORE_EN_MMCHSDB2 __BIT(17)
+#define OMAP2_CM_FCLKEN2_CORE_RESc __BIT(18)
+#define OMAP2_CM_FCLKEN2_CORE_I2CHS1 __BIT(19)
+#define OMAP2_CM_FCLKEN2_CORE_I2CHS2 __BIT(20)
+#define OMAP2_CM_FCLKEN2_CORE_RESd __BITS(31,21)
+#define OMAP2_CM_FCLKEN2_CORE_RESV \
(OMAP2_CM_FCLKEN2_CORE_RESa \
|OMAP2_CM_FCLKEN2_CORE_RESb \
|OMAP2_CM_FCLKEN2_CORE_RESc \
@@ -258,37 +258,37 @@
/*
* bit defines for OMAP2_CM_ICLKEN1_CORE
*/
-#define OMAP2_CM_ICLKEN1_CORE_EN_DSS __BIT(0)
-#define OMAP2_CM_ICLKEN1_CORE_RESa __BITS(3,1)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT2 __BIT(4)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT3 __BIT(5)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT4 __BIT(6)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT5 __BIT(7)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT6 __BIT(8)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT7 __BIT(9)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT8 __BIT(10)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT9 __BIT(11)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT10 __BIT(12)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT11 __BIT(13)
-#define OMAP2_CM_ICLKEN1_CORE_EN_GPT12 __BIT(14)
-#define OMAP2_CM_ICLKEN1_CORE_EN_MCBSP1 __BIT(15)
-#define OMAP2_CM_ICLKEN1_CORE_EN_MCBSP2 __BIT(16)
-#define OMAP2_CM_ICLKEN1_CORE_EN_MCSPI1 __BIT(17)
-#define OMAP2_CM_ICLKEN1_CORE_EN_MCSPI2 __BIT(18)
-#define OMAP2_CM_ICLKEN1_CORE_EN_I2C1 __BIT(19)
-#define OMAP2_CM_ICLKEN1_CORE_EN_I2C2 __BIT(20)
-#define OMAP2_CM_ICLKEN1_CORE_EN_UART1 __BIT(21)
-#define OMAP2_CM_ICLKEN1_CORE_EN_UART2 __BIT(22)
-#define OMAP2_CM_ICLKEN1_CORE_EN_HDQ __BIT(23)
-#define OMAP2_CM_ICLKEN1_CORE_RESb __BIT(24)
-#define OMAP2_CM_ICLKEN1_CORE_EN_FAC __BIT(25)
-#define OMAP2_CM_ICLKEN1_CORE_RESc __BIT(26)
-#define OMAP2_CM_ICLKEN1_CORE_EN_MSPR0 __BIT(27)
-#define OMAP2_CM_ICLKEN1_CORE_RESd __BIT(28)
-#define OMAP2_CM_ICLKEN1_CORE_EN_WDT4 __BIT(29)
-#define OMAP2_CM_ICLKEN1_CORE_EN_MAILBOXES __BIT(30)
-#define OMAP2_CM_ICLKEN1_CORE_EN_CAM __BIT(31)
-#define OMAP2_CM_ICLKEN1_CORE_RESV \
+#define OMAP2_CM_ICLKEN1_CORE_EN_DSS __BIT(0)
+#define OMAP2_CM_ICLKEN1_CORE_RESa __BITS(3,1)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT2 __BIT(4)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT3 __BIT(5)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT4 __BIT(6)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT5 __BIT(7)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT6 __BIT(8)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT7 __BIT(9)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT8 __BIT(10)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT9 __BIT(11)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT10 __BIT(12)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT11 __BIT(13)
+#define OMAP2_CM_ICLKEN1_CORE_EN_GPT12 __BIT(14)
+#define OMAP2_CM_ICLKEN1_CORE_EN_MCBSP1 __BIT(15)
+#define OMAP2_CM_ICLKEN1_CORE_EN_MCBSP2 __BIT(16)
+#define OMAP2_CM_ICLKEN1_CORE_EN_MCSPI1 __BIT(17)
+#define OMAP2_CM_ICLKEN1_CORE_EN_MCSPI2 __BIT(18)
+#define OMAP2_CM_ICLKEN1_CORE_EN_I2C1 __BIT(19)
+#define OMAP2_CM_ICLKEN1_CORE_EN_I2C2 __BIT(20)
+#define OMAP2_CM_ICLKEN1_CORE_EN_UART1 __BIT(21)
+#define OMAP2_CM_ICLKEN1_CORE_EN_UART2 __BIT(22)
+#define OMAP2_CM_ICLKEN1_CORE_EN_HDQ __BIT(23)
+#define OMAP2_CM_ICLKEN1_CORE_RESb __BIT(24)
+#define OMAP2_CM_ICLKEN1_CORE_EN_FAC __BIT(25)
+#define OMAP2_CM_ICLKEN1_CORE_RESc __BIT(26)
+#define OMAP2_CM_ICLKEN1_CORE_EN_MSPR0 __BIT(27)
+#define OMAP2_CM_ICLKEN1_CORE_RESd __BIT(28)
+#define OMAP2_CM_ICLKEN1_CORE_EN_WDT4 __BIT(29)
+#define OMAP2_CM_ICLKEN1_CORE_EN_MAILBOXES __BIT(30)
+#define OMAP2_CM_ICLKEN1_CORE_EN_CAM __BIT(31)
+#define OMAP2_CM_ICLKEN1_CORE_RESV \
(OMAP2_CM_ICLKEN1_CORE_RESa \
|OMAP2_CM_ICLKEN1_CORE_RESb \
|OMAP2_CM_ICLKEN1_CORE_RESc \
@@ -298,33 +298,33 @@
/*
* bit defines for OMAP2_CM_ICLKEN2_CORE
*/
-#define OMAP2_CM_ICLKEN2_CORE_EN_USB __BIT(0)
-#define OMAP2_CM_ICLKEN2_CORE_EN_SSI __BIT(1)
-#define OMAP2_CM_ICLKEN2_CORE_EN_UART3 __BIT(2)
-#define OMAP2_CM_ICLKEN2_CORE_EN_MCBSP3 __BIT(3)
-#define OMAP2_CM_ICLKEN2_CORE_EN_MCBSP4 __BIT(4)
-#define OMAP2_CM_ICLKEN2_CORE_EN_MCBSP5 __BIT(5)
-#define OMAP2_CM_ICLKEN2_CORE_EN_USBHS __BIT(6)
-#define OMAP2_CM_ICLKEN2_CORE_EN_MMCHS1 __BIT(7)
-#define OMAP2_CM_ICLKEN2_CORE_EN_MMCHS2 __BIT(8)
-#define OMAP2_CM_ICLKEN2_CORE_EN_NCSPI3 __BIT(9)
-#define OMAP2_CM_ICLKEN2_CORE_EN_GPIO5 __BIT(10)
-#define OMAP2_CM_ICLKEN2_CORE_EN_MDM_INTC __BIT(11)
-#define OMAP2_CM_ICLKEN2_CORE_RESV __BIT(31,12)
+#define OMAP2_CM_ICLKEN2_CORE_EN_USB __BIT(0)
+#define OMAP2_CM_ICLKEN2_CORE_EN_SSI __BIT(1)
+#define OMAP2_CM_ICLKEN2_CORE_EN_UART3 __BIT(2)
+#define OMAP2_CM_ICLKEN2_CORE_EN_MCBSP3 __BIT(3)
+#define OMAP2_CM_ICLKEN2_CORE_EN_MCBSP4 __BIT(4)
+#define OMAP2_CM_ICLKEN2_CORE_EN_MCBSP5 __BIT(5)
+#define OMAP2_CM_ICLKEN2_CORE_EN_USBHS __BIT(6)
+#define OMAP2_CM_ICLKEN2_CORE_EN_MMCHS1 __BIT(7)
+#define OMAP2_CM_ICLKEN2_CORE_EN_MMCHS2 __BIT(8)
+#define OMAP2_CM_ICLKEN2_CORE_EN_NCSPI3 __BIT(9)
+#define OMAP2_CM_ICLKEN2_CORE_EN_GPIO5 __BIT(10)
+#define OMAP2_CM_ICLKEN2_CORE_EN_MDM_INTC __BIT(11)
+#define OMAP2_CM_ICLKEN2_CORE_RESV __BIT(31,12)
/*
* bit defines for OMAP2_CM_CLKSEL2_CORE
*/
-#define OMAP2_CM_CLKSEL2_CORE_GPTn(n, v) \
+#define OMAP2_CM_CLKSEL2_CORE_GPTn(n, v) \
(((v) & 0x3) << (2 + ((((n) - 2) << 1))))
-# define CLKSEL2_CORE_GPT_FUNC_32K_CLK 0x0
-# define CLKSEL2_CORE_GPT_SYS_CLK 0x1
-# define CLKSEL2_CORE_GPT_ALT_CLK 0x2
-# define CLKSEL2_CORE_GPT_ALT_RESV 0x3
-
-#define OMAP2_CM_CLKSEL2_CORE_RESa __BITS(1,0)
-#define OMAP2_CM_CLKSEL2_CORE_RESb __BITS(31,24)
-#define OMAP2_CM_CLKSEL2_CORE_RESV \
+# define CLKSEL2_CORE_GPT_FUNC_32K_CLK 0x0
+# define CLKSEL2_CORE_GPT_SYS_CLK 0x1
+# define CLKSEL2_CORE_GPT_ALT_CLK 0x2
+# define CLKSEL2_CORE_GPT_ALT_RESV 0x3
+
+#define OMAP2_CM_CLKSEL2_CORE_RESa __BITS(1,0)
+#define OMAP2_CM_CLKSEL2_CORE_RESb __BITS(31,24)
+#define OMAP2_CM_CLKSEL2_CORE_RESV \
(OMAP2_CM_CLKSEL2_CORE_RESa \
|OMAP2_CM_CLKSEL2_CORE_RESb)
@@ -343,7 +343,7 @@
#define OMAP4_CM_DIV_M2_DPLL_MPU 0x170
#define OMAP4_CM_SYS_CLKSEL_CLKIN __BITS(2,0)
-#define OMAP4_CM_CLKSEL_FREQS { 0, 12000, 13000, 16800, 19200, 26000, 27000, 38400 }
+#define OMAP4_CM_CLKSEL_FREQS { 0, 12000, 13000, 16800, 19200, 26000, 27000, 38400 }
#define OMAP4_CM_CLKSEL_MULT 1000
#define OMAP4_CM_CLKSEL_DPLL_MPU_DCC_EN __BIT(22)
@@ -363,46 +363,46 @@
#define TI_AM335X_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIVCHACK __BIT(5)
#define TI_AM335X_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIV __BITS(4,0)
-#define OMAP4_CM_L3INIT_CORE 0x5300 /* OMAP2_CM_BASE */
-#define OMAP5_CM_L3INIT_CORE 0x5600 /* OMAP2_CM_BASE */
-#define OMAP4_CM_L3INIT_HSMMC1_CLKCTRL 0x0008
-#define OMAP4_CM_L3INIT_HSMMC2_CLKCTRL 0x0030
-#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL_DIV2 __BIT(25)
-#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL __BIT(24)
-#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_OPTFCLKEN_32KHZ_CLK __BIT(8)
-#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE __BITS(1,0)
-#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE_HW 2
+#define OMAP4_CM_L3INIT_CORE 0x5300 /* OMAP2_CM_BASE */
+#define OMAP5_CM_L3INIT_CORE 0x5600 /* OMAP2_CM_BASE */
+#define OMAP4_CM_L3INIT_HSMMC1_CLKCTRL 0x0008
+#define OMAP4_CM_L3INIT_HSMMC2_CLKCTRL 0x0030
+#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL_DIV2 __BIT(25)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL __BIT(24)
+#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_OPTFCLKEN_32KHZ_CLK __BIT(8)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE __BITS(1,0)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE_HW 2
#define OMAP4_CM_L3INIT_HSI_CLKCTRL 0x0038
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL 0x0058
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P2 __BIT(25)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P1 __BIT(24)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_FUNC48M_CLK __BIT(15)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK __BIT(14)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P1_CLK __BIT(13)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK __BIT(12)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P1_CLK __BIT(11)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK __BIT(10)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK __BIT(9)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P1_CLK __BIT(8)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK __BIT(7)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK __BIT(6)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE __BITS(1,0)
-#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE_HW 2
-#define OMAP4_CM_L3INIT_USB_OTG_HS_CLKCTRL 0x0060
-#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_CLKSEL_60M __BIT(24)
-#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_XCLK __BIT(8)
-#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
-#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
-#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL 0x0068
-#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK __BIT(10)
-#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK __BIT(9)
-#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH0_CLK __BIT(8)
-#define OMAP5_CM_L3INIT_SATA_CLKCTRL 0x0088
-#define OMAP5_CM_L3INIT_SATA_CLKCTRL_OPTFCLKEN_REF_CLK __BIT(8)
-#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL 0x00F0
-#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_REFCLK960M __BIT(8)
-#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
-#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL 0x0058
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P2 __BIT(25)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P1 __BIT(24)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_FUNC48M_CLK __BIT(15)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK __BIT(14)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P1_CLK __BIT(13)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK __BIT(12)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P1_CLK __BIT(11)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK __BIT(10)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK __BIT(9)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P1_CLK __BIT(8)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK __BIT(7)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK __BIT(6)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE_HW 2
+#define OMAP4_CM_L3INIT_USB_OTG_HS_CLKCTRL 0x0060
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_CLKSEL_60M __BIT(24)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_XCLK __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL 0x0068
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK __BIT(10)
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK __BIT(9)
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH0_CLK __BIT(8)
+#define OMAP5_CM_L3INIT_SATA_CLKCTRL 0x0088
+#define OMAP5_CM_L3INIT_SATA_CLKCTRL_OPTFCLKEN_REF_CLK __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL 0x00F0
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_REFCLK960M __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
/*
* Power Management registers base, offsets, and size
@@ -426,43 +426,43 @@
#define OMAP2_PRM_BASE 0x48306000
#endif
-#define OMAP2_PRM_SIZE 0x00002000 /* 8k */
+#define OMAP2_PRM_SIZE 0x00002000 /* 8k */
/* module offsets */
-#define OCP_MOD 0x0800
-#define MPU_MOD 0x0900
-#define CORE_MOD 0x0a00
-#define GFX_MOD 0x0b00
-#define WKUP_MOD 0x0c00
-#define PLL_MOD 0x0d00
+#define OCP_MOD 0x0800
+#define MPU_MOD 0x0900
+#define CORE_MOD 0x0a00
+#define GFX_MOD 0x0b00
+#define WKUP_MOD 0x0c00
+#define PLL_MOD 0x0d00
/* module offsets specific to chip */
-#define OMAP24XX_GR_MOD OCP_MOD
-#define OMAP24XX_DSP_MOD 0x1000
-#define OMAP2430_MDM_MOD 0x1400
-#define OMAP3430_IVA2_MOD 0x0000 /* IVA2 before base! */
-#define OMAP3430ES2_SGX_MOD GFX_MOD
-#define OMAP3430_CCR_MOD PLL_MOD
-#define OMAP3430_DSS_MOD 0x0e00
-#define OMAP3430_CAM_MOD 0x0f00
-#define OMAP3430_PER_MOD 0x1000
-#define OMAP3430_EMU_MOD 0x1100
-#define OMAP3430_GR_MOD 0x1200
-#define OMAP3430_NEON_MOD 0x1300
-#define OMAP3430ES2_USBHOST_MOD 0x1400
-
-#define OMAP2_RM_RSTCTRL 0x50
-#define OMAP2_RM_RSTTIME 0x54
-#define OMAP2_RM_RSTST 0x58
-#define OMAP2_PM_WKDEP 0xc8
-#define OMAP2_PM_PWSTCTRL 0xe0
-#define OMAP2_PM_PWSTST 0xe4
-#define OMAP2_PM_PREPWSTST 0xe8
-#define OMAP2_PRM_IRQSTATUS 0xf8
-#define OMAP2_PRM_IRQENABLE 0xfc
+#define OMAP24XX_GR_MOD OCP_MOD
+#define OMAP24XX_DSP_MOD 0x1000
+#define OMAP2430_MDM_MOD 0x1400
+#define OMAP3430_IVA2_MOD 0x0000 /* IVA2 before base! */
+#define OMAP3430ES2_SGX_MOD GFX_MOD
+#define OMAP3430_CCR_MOD PLL_MOD
+#define OMAP3430_DSS_MOD 0x0e00
+#define OMAP3430_CAM_MOD 0x0f00
+#define OMAP3430_PER_MOD 0x1000
+#define OMAP3430_EMU_MOD 0x1100
+#define OMAP3430_GR_MOD 0x1200
+#define OMAP3430_NEON_MOD 0x1300
+#define OMAP3430ES2_USBHOST_MOD 0x1400
+
+#define OMAP2_RM_RSTCTRL 0x50
+#define OMAP2_RM_RSTTIME 0x54
+#define OMAP2_RM_RSTST 0x58
+#define OMAP2_PM_WKDEP 0xc8
+#define OMAP2_PM_PWSTCTRL 0xe0
+#define OMAP2_PM_PWSTST 0xe4
+#define OMAP2_PM_PREPWSTST 0xe8
+#define OMAP2_PRM_IRQSTATUS 0xf8
+#define OMAP2_PRM_IRQENABLE 0xfc
-#define OMAP_RST_DPLL3 __BIT(2)
-#define OMAP_RST_GS __BIT(1)
+#define OMAP_RST_DPLL3 __BIT(2)
+#define OMAP_RST_GS __BIT(1)
#define OMAP3_PRM_CLKSEL 0x40 // from PLL_MOD
#define OMAP3_PRM_CLKSEL_CLKIN __BITS(2,0)
@@ -472,7 +472,7 @@
#define OMAP3_PRM_CLKSEL_CLKIN_26000KHZ 3
#define OMAP3_PRM_CLKSEL_CLKIN_38400KHZ 4
#define OMAP3_PRM_CLKSEL_CLKIN_16800KHZ 5
-#define OMAP3_PRM_CLKSEL_FREQS { 12000, 13000, 19200, 26000, 38400, 16800, 0, 0 }
+#define OMAP3_PRM_CLKSEL_FREQS { 12000, 13000, 19200, 26000, 38400, 16800, 0, 0 }
#define OMAP3_PRM_CLKSEL_MULT 1000
#define OMAP4_PRM_RSTCTRL 0x7b00
@@ -483,18 +483,18 @@
/*
* L3 Interconnect Target Agent Common Registers
*/
-#define OMAP2_TA_GPMC 0x68002400
-#define OMAP2_TA_L4_CORE 0x68006800
+#define OMAP2_TA_GPMC 0x68002400
+#define OMAP2_TA_L4_CORE 0x68006800
/*
* L3 Interconnect Target Agent Common Register offsets
*/
-#define OMAP2_TA_COMPONENT 0x00
-#define OMAP2_TA_CORE 0x18
-#define OMAP2_TA_AGENT_CONTROL 0x20
-#define OMAP2_TA_AGENT_STATUS 0x28
-#define OMAP2_TA_ERROR_LOG 0x58
-#define OMAP2_TA_ERROR_LOG_ADDR 0x60
+#define OMAP2_TA_COMPONENT 0x00
+#define OMAP2_TA_CORE 0x18
+#define OMAP2_TA_AGENT_CONTROL 0x20
+#define OMAP2_TA_AGENT_STATUS 0x28
+#define OMAP2_TA_ERROR_LOG 0x58
+#define OMAP2_TA_ERROR_LOG_ADDR 0x60
/*
* OMAP2_TA_COMPONENT bits
@@ -511,113 +511,113 @@
/*
* OMAP2_TA_AGENT_CONTROL bits
*/
-#define TA_AGENT_CONTROL_CORE_RESET __BIT(0)
-#define TA_AGENT_CONTROL_CORE_REJECT __BIT(4)
-#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE __BITS(10,8)
-#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_SHFT 8
-#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_NONE 0
-#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_1 1
-#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_4 2
-#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_16 3
-#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_64 4
-#define TA_AGENT_CONTROL_CORE_SERROR_REP __BIT(24)
-#define TA_AGENT_CONTROL_CORE_REQ_TIMEOUT_REP __BIT(25)
+#define TA_AGENT_CONTROL_CORE_RESET __BIT(0)
+#define TA_AGENT_CONTROL_CORE_REJECT __BIT(4)
+#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE __BITS(10,8)
+#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_SHFT 8
+#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_NONE 0
+#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_1 1
+#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_4 2
+#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_16 3
+#define TA_AGENT_CONTROL_CORE_TIMEOUT_BASE_64 4
+#define TA_AGENT_CONTROL_CORE_SERROR_REP __BIT(24)
+#define TA_AGENT_CONTROL_CORE_REQ_TIMEOUT_REP __BIT(25)
/*
* OMAP2_TA_AGENT_STATUS bits
*/
-#define TA_AGENT_STATUS_CORE_RESET __BIT(0)
-#define TA_AGENT_STATUS_RESVa __BITS(3,1)
-#define TA_AGENT_STATUS_REQ_WAITING __BIT(4)
-#define TA_AGENT_STATUS_RESP_ACTIVE __BIT(5)
-#define TA_AGENT_STATUS_BURST __BIT(6)
-#define TA_AGENT_STATUS_READEX __BIT(7)
-#define TA_AGENT_STATUS_REQ_TIMEOUT __BIT(8)
-#define TA_AGENT_STATUS_RESVb __BITS(11,9)
-#define TA_AGENT_STATUS_TIMEBASE __BITS(15,12)
-#define TA_AGENT_STATUS_BURST_CLOSE __BIT(16)
-#define TA_AGENT_STATUS_RESVc __BITS(23,17)
-#define TA_AGENT_STATUS_SERROR __BIT(24) /* XXX */
-#define TA_AGENT_STATUS_RESVd __BITS(31,25)
+#define TA_AGENT_STATUS_CORE_RESET __BIT(0)
+#define TA_AGENT_STATUS_RESVa __BITS(3,1)
+#define TA_AGENT_STATUS_REQ_WAITING __BIT(4)
+#define TA_AGENT_STATUS_RESP_ACTIVE __BIT(5)
+#define TA_AGENT_STATUS_BURST __BIT(6)
+#define TA_AGENT_STATUS_READEX __BIT(7)
+#define TA_AGENT_STATUS_REQ_TIMEOUT __BIT(8)
+#define TA_AGENT_STATUS_RESVb __BITS(11,9)
+#define TA_AGENT_STATUS_TIMEBASE __BITS(15,12)
+#define TA_AGENT_STATUS_BURST_CLOSE __BIT(16)
+#define TA_AGENT_STATUS_RESVc __BITS(23,17)
+#define TA_AGENT_STATUS_SERROR __BIT(24) /* XXX */
+#define TA_AGENT_STATUS_RESVd __BITS(31,25)
/*
* OMAP2_TA_ERROR_LOG bits
*/
-#define TA_ERROR_LOG_CMD __BITS(2,0)
-#define TA_ERROR_LOG_RESa __BITS(7,3)
-#define TA_ERROR_LOG_INITID __BITS(15,8) /* initiator */
-#define TA_ERROR_LOG_RESb __BITS(23,16)
-#define TA_ERROR_LOG_CODE __BITS(27,24) /* error */
-#define TA_ERROR_LOG_RESc __BITS(30,28)
-#define TA_ERROR_LOG_MULTI __BIT(31) /* write to clear */
+#define TA_ERROR_LOG_CMD __BITS(2,0)
+#define TA_ERROR_LOG_RESa __BITS(7,3)
+#define TA_ERROR_LOG_INITID __BITS(15,8) /* initiator */
+#define TA_ERROR_LOG_RESb __BITS(23,16)
+#define TA_ERROR_LOG_CODE __BITS(27,24) /* error */
+#define TA_ERROR_LOG_RESc __BITS(30,28)
+#define TA_ERROR_LOG_MULTI __BIT(31) /* write to clear */
/*
* L4 Interconnect CORE address space
*/
-#define OMAP2430_L4_S3220_2430_WATCHDOGOCP24 0x48027000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC2 0x4802B000
-#define OMAP2430_L4_S3220_2430_AP 0x48040000
-#define OMAP2430_L4_S3220_2430_IA 0x48040800
-#define OMAP2430_L4_S3220_2430_LA 0x48041000
-#define OMAP2430_L4_S3220_2430_MPU_SS 0x4804A000
-#define OMAP2430_L4_S3220_2430_DISPLAY_SUBS 0x48051000
-#define OMAP2430_L4_S3220_2430_CAMERA_CORE 0x48053000
-#define OMAP2430_L4_S3220_2430_SDMA 0x48057000
-#define OMAP2430_L4_S3220_2430_SSI 0x4805C000
-#define OMAP2430_L4_S3220_2430_USB_OTG_FS 0x4805F000
-#define OMAP2430_L4_S3220_2430_XTI 0x48069000
-#define OMAP2430_L4_S3220_2430_UART1 0x4806B000
-#define OMAP2430_L4_S3220_2430_UART2 0x4806D000
-#define OMAP2430_L4_S3220_2430_UART3 0x4806F000
-#define OMAP2430_L4_S3220_2430_MSHSI2C1 0x48071000
-#define OMAP2430_L4_S3220_2430_MSHSI2C2 0x48073000
-#define OMAP2430_L4_S3220_2430_MCBSP1 0x48075000
-#define OMAP2430_L4_S3220_2430_MCBSP2 0x48077000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC3 0x48079000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC4 0x4807B000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC5 0x4807D000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC6 0x4807F000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC7 0x48081000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC8 0x48083000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC9 0x48085000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC10 0x48087000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC11 0x48089000
-#define OMAP2430_L4_S3220_2430_DMTIMER_DMC12 0x4808B000
-#define OMAP2430_L4_S3220_2430_MCBSP3 0x4808D000
-#define OMAP2430_L4_S3220_2430_MCBSP4 0x4808F000
-#define OMAP2430_L4_S3220_2430_FAC 0x48093000
-#define OMAP2430_L4_S3220_2430_MAILBOX1 0x48095000
-#define OMAP2430_L4_S3220_2430_MCBSP5 0x48097000
-#define OMAP2430_L4_S3220_2430_MCSPI1 0x48099000
-#define OMAP2430_L4_S3220_2430_MCSPI2 0x4809B000
-#define OMAP2430_L4_S3220_2430_MMCHS1 0x4809D000
-#define OMAP2430_L4_S3220_2430_MSPRO 0x4809F000
-#define OMAP2430_L4_S3220_2430_RNG 0x480A1000
-#define OMAP2430_L4_S3220_2430_DESOCP 0x480A3000
-#define OMAP2430_L4_S3220_2430_SHA1MD5OCP 0x480A5000
-#define OMAP2430_L4_S3220_2430_AESOCP 0x480A7000
-#define OMAP2430_L4_S3220_2430_PKA 0x480AA000
-#define OMAP2430_L4_S3220_2430_USBHHCOCP 0x480AE000
-#define OMAP2430_L4_S3220_2430_MGATE 0x480B1000
-#define OMAP2430_L4_S3220_2430_HDQ1WOCP 0x480B3000
-#define OMAP2430_L4_S3220_2430_MMCHS2 0x480B5000
-#define OMAP2430_L4_S3220_2430_GPIO 0x480B7000
-#define OMAP2430_L4_S3220_2430_MCSPI3 0x480B9000
-#define OMAP2430_L4_S3220_2430_MODEM_INTH 0x480C3000
+#define OMAP2430_L4_S3220_2430_WATCHDOGOCP24 0x48027000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC2 0x4802B000
+#define OMAP2430_L4_S3220_2430_AP 0x48040000
+#define OMAP2430_L4_S3220_2430_IA 0x48040800
+#define OMAP2430_L4_S3220_2430_LA 0x48041000
+#define OMAP2430_L4_S3220_2430_MPU_SS 0x4804A000
+#define OMAP2430_L4_S3220_2430_DISPLAY_SUBS 0x48051000
+#define OMAP2430_L4_S3220_2430_CAMERA_CORE 0x48053000
+#define OMAP2430_L4_S3220_2430_SDMA 0x48057000
+#define OMAP2430_L4_S3220_2430_SSI 0x4805C000
+#define OMAP2430_L4_S3220_2430_USB_OTG_FS 0x4805F000
+#define OMAP2430_L4_S3220_2430_XTI 0x48069000
+#define OMAP2430_L4_S3220_2430_UART1 0x4806B000
+#define OMAP2430_L4_S3220_2430_UART2 0x4806D000
+#define OMAP2430_L4_S3220_2430_UART3 0x4806F000
+#define OMAP2430_L4_S3220_2430_MSHSI2C1 0x48071000
+#define OMAP2430_L4_S3220_2430_MSHSI2C2 0x48073000
+#define OMAP2430_L4_S3220_2430_MCBSP1 0x48075000
+#define OMAP2430_L4_S3220_2430_MCBSP2 0x48077000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC3 0x48079000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC4 0x4807B000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC5 0x4807D000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC6 0x4807F000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC7 0x48081000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC8 0x48083000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC9 0x48085000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC10 0x48087000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC11 0x48089000
+#define OMAP2430_L4_S3220_2430_DMTIMER_DMC12 0x4808B000
+#define OMAP2430_L4_S3220_2430_MCBSP3 0x4808D000
+#define OMAP2430_L4_S3220_2430_MCBSP4 0x4808F000
+#define OMAP2430_L4_S3220_2430_FAC 0x48093000
+#define OMAP2430_L4_S3220_2430_MAILBOX1 0x48095000
+#define OMAP2430_L4_S3220_2430_MCBSP5 0x48097000
+#define OMAP2430_L4_S3220_2430_MCSPI1 0x48099000
+#define OMAP2430_L4_S3220_2430_MCSPI2 0x4809B000
+#define OMAP2430_L4_S3220_2430_MMCHS1 0x4809D000
+#define OMAP2430_L4_S3220_2430_MSPRO 0x4809F000
+#define OMAP2430_L4_S3220_2430_RNG 0x480A1000
+#define OMAP2430_L4_S3220_2430_DESOCP 0x480A3000
+#define OMAP2430_L4_S3220_2430_SHA1MD5OCP 0x480A5000
+#define OMAP2430_L4_S3220_2430_AESOCP 0x480A7000
+#define OMAP2430_L4_S3220_2430_PKA 0x480AA000
+#define OMAP2430_L4_S3220_2430_USBHHCOCP 0x480AE000
+#define OMAP2430_L4_S3220_2430_MGATE 0x480B1000
+#define OMAP2430_L4_S3220_2430_HDQ1WOCP 0x480B3000
+#define OMAP2430_L4_S3220_2430_MMCHS2 0x480B5000
+#define OMAP2430_L4_S3220_2430_GPIO 0x480B7000
+#define OMAP2430_L4_S3220_2430_MCSPI3 0x480B9000
+#define OMAP2430_L4_S3220_2430_MODEM_INTH 0x480C3000
/*
* L3 Interconnect Sideband Interconnect register base
*/
-#define OMAP2_SI_BASE 0x68000400
+#define OMAP2_SI_BASE 0x68000400
/*
* L3 Interconnect Sideband Interconnect register offsets
*/
-#define OMAP2_SI_CONTOL 0x0020
-#define OMAP2_SI_FLAG_STATUS_0 0x0110 /* APE_app */
-#define OMAP2_SI_FLAG_STATUS_1 0x0130 /* APE_dbg */
-#define OMAP2_SI_FLAG_STATUS_2 0x0150 /* MODEM_app */
-#define OMAP2_SI_FLAG_STATUS_3 0x0170 /* MODEM_dbg */
+#define OMAP2_SI_CONTOL 0x0020
+#define OMAP2_SI_FLAG_STATUS_0 0x0110 /* APE_app */
+#define OMAP2_SI_FLAG_STATUS_1 0x0130 /* APE_dbg */
+#define OMAP2_SI_FLAG_STATUS_2 0x0150 /* MODEM_app */
+#define OMAP2_SI_FLAG_STATUS_3 0x0170 /* MODEM_dbg */
/*
* Interrupts
@@ -659,7 +659,7 @@
#define INTC_IDLE_TURBO 0x2
#define INTC_IDLE_FUNCIDLE 0x1
-#define INTC_ILR_PRIORTY_SHFT 2
+#define INTC_ILR_PRIORTY_SHFT 2
#define INTC_ILR_FIQNIRQ 0x1 /* intr is a FIQ */
/*
@@ -785,16 +785,16 @@
#define GPIO_CLEARIRQENABLE2 0x070
#define GPIO_SETIRQENABLE2 0x074
#define GPIO_CLEANWKUENA 0x080
-#define GPIO_SETWKUENA 0x084
-#define GPIO_CLEARDATAOUT 0x090
-#define GPIO_SETDATAOUT 0x094
+#define GPIO_SETWKUENA 0x084
+#define GPIO_CLEARDATAOUT 0x090
+#define GPIO_SETDATAOUT 0x094
/*
* I2C
*/
-#define I2C1_BASE_3530 0x48070000
-#define I2C2_BASE_3530 0x48072000
-#define I2C3_BASE_3530 0x48060000
+#define I2C1_BASE_3530 0x48070000
+#define I2C2_BASE_3530 0x48072000
+#define I2C3_BASE_3530 0x48060000
/*
* USB Host
@@ -810,53 +810,53 @@
/*
* SDRC
*/
-#define OMAP3530_SDRC_BASE 0x6d000000
-#define OMAP3530_SDRC_SIZE 0x00010000 /* 16KB */
+#define OMAP3530_SDRC_BASE 0x6d000000
+#define OMAP3530_SDRC_SIZE 0x00010000 /* 16KB */
/*
* DMA
*/
-#define OMAP3530_SDMA_BASE 0x48056000
-#define OMAP3530_SDMA_SIZE 0x00001000 /* 4KB */
+#define OMAP3530_SDMA_BASE 0x48056000
+#define OMAP3530_SDMA_SIZE 0x00001000 /* 4KB */
/*
* PL310 L2CC (44xx)
*/
-#define OMAP4_SCU_BASE 0x48240000
-#define OMAP4_L2CC_BASE 0x48242000
-#define OMAP4_L2CC_SIZE 0x00001000 /* 4KB */
+#define OMAP4_SCU_BASE 0x48240000
+#define OMAP4_L2CC_BASE 0x48242000
+#define OMAP4_L2CC_SIZE 0x00001000 /* 4KB */
-#define OMAP4_CONTROL_ID_CODE 0x4a002204
+#define OMAP4_CONTROL_ID_CODE 0x4a002204
-#define AHCI1_BASE_OMAP5 0x4a140000
+#define AHCI1_BASE_OMAP5 0x4a140000
/* These also apply to OMAP5 */
-#define OMAP4_WUGEN_BASE 0x48281000
-#define OMAP4_WKG_CONTROL_0 0x00000000
-#define OMAP4_WKG_CONTROL_1 0x00000400
-#define OMAP4_AUX_CORE_BOOT0 0x00000800
-#define OMAP4_AUX_CORE_BOOT1 0x00000804
-
-#define OMAP5_PRM_FRAC_INCREMENTER_NUMERATOR 0x48243210
-#define PRM_FRAC_INCR_NUM_ABE_LP_MODE __BITS(27,16)
-#define PRM_FRAC_INCR_NUM_SYS_MODE __BITS(11,0)
-#define OMAP5_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD 0x48243214
-#define PRM_FRAC_INCR_DENUM_RELOAD __BIT(16)
-#define PRM_FRAC_INCR_DENUM_DENOMINATOR __BITS(11,0)
-#define OMAP5_GTIMER_FREQ 6144000 /* 6.144Mhz */
+#define OMAP4_WUGEN_BASE 0x48281000
+#define OMAP4_WKG_CONTROL_0 0x00000000
+#define OMAP4_WKG_CONTROL_1 0x00000400
+#define OMAP4_AUX_CORE_BOOT0 0x00000800
+#define OMAP4_AUX_CORE_BOOT1 0x00000804
+
+#define OMAP5_PRM_FRAC_INCREMENTER_NUMERATOR 0x48243210
+#define PRM_FRAC_INCR_NUM_ABE_LP_MODE __BITS(27,16)
+#define PRM_FRAC_INCR_NUM_SYS_MODE __BITS(11,0)
+#define OMAP5_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD 0x48243214
+#define PRM_FRAC_INCR_DENUM_RELOAD __BIT(16)
+#define PRM_FRAC_INCR_DENUM_DENOMINATOR __BITS(11,0)
+#define OMAP5_GTIMER_FREQ 6144000 /* 6.144Mhz */
#ifdef TI_AM335X
-#define TI_AM335X_CTLMOD_BASE 0x44e10000
-#define CTLMOD_CONTROL_STATUS 0x40
-#define CTLMOD_CONTROL_STATUS_SYSBOOT1 __BITS(23,22)
+#define TI_AM335X_CTLMOD_BASE 0x44e10000
+#define CTLMOD_CONTROL_STATUS 0x40
+#define CTLMOD_CONTROL_STATUS_SYSBOOT1 __BITS(23,22)
#endif
#if defined(OMAP4) || defined(TI_AM335X)
-#define EMIF_SDRAM_CONFIG 8
-#define SDRAM_CONFIG_WIDTH __BITS(15,14)
-#define SDRAM_CONFIG_RSIZE __BITS(9,7)
-#define SDRAM_CONFIG_IBANK __BITS(6,4)
-#define SDRAM_CONFIG_EBANK __BIT(3)
-#define SDRAM_CONFIG_PAGESIZE __BITS(2,0)
+#define EMIF_SDRAM_CONFIG 8
+#define SDRAM_CONFIG_WIDTH __BITS(15,14)
+#define SDRAM_CONFIG_RSIZE __BITS(9,7)
+#define SDRAM_CONFIG_IBANK __BITS(6,4)
+#define SDRAM_CONFIG_EBANK __BIT(3)
+#define SDRAM_CONFIG_PAGESIZE __BITS(2,0)
#endif
#endif /* _ARM_OMAP_OMAP2_REG_H_ */
