Module Name: src
Committed By: joerg
Date: Tue Apr 15 18:40:34 UTC 2014
Modified Files:
src/share/mk: bsd.own.mk
src/sys/lib/libunwind: Registers.hpp unwind_registers.S
Log Message:
Add basic Alpha support to libunwind.
To generate a diff of this commit:
cvs rdiff -u -r1.797 -r1.798 src/share/mk/bsd.own.mk
cvs rdiff -u -r1.11 -r1.12 src/sys/lib/libunwind/Registers.hpp
cvs rdiff -u -r1.9 -r1.10 src/sys/lib/libunwind/unwind_registers.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/share/mk/bsd.own.mk
diff -u src/share/mk/bsd.own.mk:1.797 src/share/mk/bsd.own.mk:1.798
--- src/share/mk/bsd.own.mk:1.797 Tue Apr 15 11:44:26 2014
+++ src/share/mk/bsd.own.mk Tue Apr 15 18:40:34 2014
@@ -1,4 +1,4 @@
-# $NetBSD: bsd.own.mk,v 1.797 2014/04/15 11:44:26 joerg Exp $
+# $NetBSD: bsd.own.mk,v 1.798 2014/04/15 18:40:34 joerg Exp $
# This needs to be before bsd.init.mk
.if defined(BSD_MK_COMPAT_FILE)
@@ -99,6 +99,7 @@ HAVE_LIBGCC?= no
HAVE_LIBGCC?= yes
.endif
+_LIBC_UNWIND_SUPPORT.alpha= yes
_LIBC_UNWIND_SUPPORT.i386= yes
_LIBC_UNWIND_SUPPORT.m68k= yes
_LIBC_UNWIND_SUPPORT.powerpc= yes
Index: src/sys/lib/libunwind/Registers.hpp
diff -u src/sys/lib/libunwind/Registers.hpp:1.11 src/sys/lib/libunwind/Registers.hpp:1.12
--- src/sys/lib/libunwind/Registers.hpp:1.11 Tue Apr 15 11:44:26 2014
+++ src/sys/lib/libunwind/Registers.hpp Tue Apr 15 18:40:34 2014
@@ -653,6 +653,73 @@ private:
uint32_t reg[REGNO_SPARC_PC + 1];
};
+enum {
+ DWARF_ALPHA_R0 = 0,
+ DWARF_ALPHA_R30 = 30,
+ DWARF_ALPHA_F0 = 32,
+ DWARF_ALPHA_F30 = 62,
+
+ REGNO_ALPHA_R0 = 0,
+ REGNO_ALPHA_R26 = 26,
+ REGNO_ALPHA_R30 = 30,
+ REGNO_ALPHA_PC = 31,
+ REGNO_ALPHA_F0 = 32,
+ REGNO_ALPHA_F30 = 62,
+};
+
+class Registers_Alpha {
+public:
+ enum {
+ LAST_REGISTER = REGNO_ALPHA_F30,
+ LAST_RESTORE_REG = REGNO_ALPHA_F30,
+ RETURN_REG = REGNO_ALPHA_R26,
+ RETURN_OFFSET = 0,
+ };
+ typedef uint32_t reg_t;
+
+ __dso_hidden Registers_Alpha();
+
+ static int dwarf2regno(int num) { return num; }
+
+ bool validRegister(int num) const {
+ return num >= 0 && num <= REGNO_ALPHA_PC;
+ }
+
+ uint64_t getRegister(int num) const {
+ assert(validRegister(num));
+ return reg[num];
+ }
+
+ void setRegister(int num, uint64_t value) {
+ assert(validRegister(num));
+ reg[num] = value;
+ }
+
+ uint64_t getIP() const { return reg[REGNO_ALPHA_PC]; }
+
+ void setIP(uint64_t value) { reg[REGNO_ALPHA_PC] = value; }
+
+ uint64_t getSP() const { return reg[REGNO_ALPHA_R30]; }
+
+ void setSP(uint64_t value) { reg[REGNO_ALPHA_R30] = value; }
+
+ bool validFloatVectorRegister(int num) const {
+ return num >= REGNO_ALPHA_F0 && num <= REGNO_ALPHA_F30;
+ }
+
+ void copyFloatVectorRegister(int num, uint64_t addr_) {
+ assert(validFloatVectorRegister(num));
+ const void *addr = reinterpret_cast<const void *>(addr_);
+ memcpy(fpreg + (num - REGNO_ALPHA_F0), addr, sizeof(fpreg[0]));
+ }
+
+ __dso_hidden void jumpto() const __dead;
+
+private:
+ uint64_t reg[REGNO_ALPHA_PC + 1];
+ uint64_t fpreg[31];
+};
+
#if __i386__
typedef Registers_x86 NativeUnwindRegisters;
#elif __x86_64__
@@ -671,6 +738,8 @@ typedef Registers_SH3 NativeUnwindRegist
typedef Registers_SPARC64 NativeUnwindRegisters;
#elif __sparc__
typedef Registers_SPARC NativeUnwindRegisters;
+#elif __alpha__
+typedef Registers_Alpha NativeUnwindRegisters;
#endif
} // namespace _Unwind
Index: src/sys/lib/libunwind/unwind_registers.S
diff -u src/sys/lib/libunwind/unwind_registers.S:1.9 src/sys/lib/libunwind/unwind_registers.S:1.10
--- src/sys/lib/libunwind/unwind_registers.S:1.9 Tue Apr 15 11:44:26 2014
+++ src/sys/lib/libunwind/unwind_registers.S Tue Apr 15 18:40:34 2014
@@ -589,3 +589,146 @@ ENTRY(_ZNK7_Unwind15Registers_SPARC6jump
ld [%o0 + 32], %o0
END(_ZNK7_Unwind15Registers_SPARC6jumptoEv)
#endif
+
+#if defined(__alpha__)
+ .set nomacro
+ .set noat
+ .hidden _ZN7_Unwind15Registers_AlphaC1Ev
+LEAF_NOPROFILE(_ZN7_Unwind15Registers_AlphaC1Ev, 1)
+ stq $0, 0($16)
+ stq $1, 8($16)
+ stq $2, 16($16)
+ stq $3, 24($16)
+ stq $4, 32($16)
+ stq $5, 40($16)
+ stq $6, 48($16)
+ stq $7, 56($16)
+ stq $8, 64($16)
+ stq $9, 72($16)
+ stq $10, 80($16)
+ stq $11, 88($16)
+ stq $12, 96($16)
+ stq $13, 104($16)
+ stq $14, 112($16)
+ stq $15, 120($16)
+ stq $16, 128($16)
+ stq $17, 136($16)
+ stq $18, 144($16)
+ stq $19, 152($16)
+ stq $20, 160($16)
+ stq $21, 168($16)
+ stq $22, 176($16)
+ stq $23, 184($16)
+ stq $24, 192($16)
+ stq $25, 200($16)
+ stq $26, 208($16)
+ stq $27, 216($16)
+ stq $28, 224($16)
+ stq $29, 232($16)
+ stq $30, 240($16)
+ stq $26, 248($16)
+
+ stt $f0, 256($16)
+ stt $f1, 264($16)
+ stt $f2, 272($16)
+ stt $f3, 280($16)
+ stt $f4, 288($16)
+ stt $f5, 296($16)
+ stt $f6, 304($16)
+ stt $f7, 312($16)
+ stt $f8, 320($16)
+ stt $f9, 328($16)
+ stt $f10, 336($16)
+ stt $f11, 344($16)
+ stt $f12, 352($16)
+ stt $f13, 360($16)
+ stt $f14, 368($16)
+ stt $f15, 376($16)
+ stt $f16, 384($16)
+ stt $f17, 392($16)
+ stt $f18, 400($16)
+ stt $f19, 408($16)
+ stt $f20, 416($16)
+ stt $f21, 424($16)
+ stt $f22, 432($16)
+ stt $f23, 440($16)
+ stt $f24, 448($16)
+ stt $f25, 456($16)
+ stt $f26, 464($16)
+ stt $f27, 472($16)
+ stt $f28, 480($16)
+ stt $f29, 488($16)
+ stt $f30, 496($16)
+ ret $31, ($26), 1
+END(_ZN7_Unwind15Registers_AlphaC1Ev)
+
+ .set nomacro
+ .set noat
+ .hidden _ZNK7_Unwind15Registers_Alpha6jumptoEv
+LEAF_NOPROFILE(_ZNK7_Unwind15Registers_Alpha6jumptoEv, 1)
+ ldq $0, 0($16)
+ ldq $1, 8($16)
+ ldq $2, 16($16)
+ ldq $3, 24($16)
+ ldq $4, 32($16)
+ ldq $5, 40($16)
+ ldq $6, 48($16)
+ ldq $7, 56($16)
+ ldq $8, 64($16)
+ ldq $9, 72($16)
+ ldq $10, 80($16)
+ ldq $11, 88($16)
+ ldq $12, 96($16)
+ ldq $13, 104($16)
+ ldq $14, 112($16)
+ ldq $15, 120($16)
+ ldq $17, 136($16)
+ ldq $18, 144($16)
+ ldq $19, 152($16)
+ ldq $20, 160($16)
+ ldq $21, 168($16)
+ ldq $22, 176($16)
+ ldq $23, 184($16)
+ ldq $24, 192($16)
+ ldq $25, 200($16)
+ ldq $27, 216($16)
+ ldq $28, 224($16)
+ ldq $29, 232($16)
+ ldq $30, 240($16)
+ ldq $26, 248($16)
+
+ ldt $f0, 256($16)
+ ldt $f1, 264($16)
+ ldt $f2, 272($16)
+ ldt $f3, 280($16)
+ ldt $f4, 288($16)
+ ldt $f5, 296($16)
+ ldt $f6, 304($16)
+ ldt $f7, 312($16)
+ ldt $f8, 320($16)
+ ldt $f9, 328($16)
+ ldt $f10, 336($16)
+ ldt $f11, 344($16)
+ ldt $f12, 352($16)
+ ldt $f13, 360($16)
+ ldt $f14, 368($16)
+ ldt $f15, 376($16)
+ ldt $f16, 384($16)
+ ldt $f17, 392($16)
+ ldt $f18, 400($16)
+ ldt $f19, 408($16)
+ ldt $f20, 416($16)
+ ldt $f21, 424($16)
+ ldt $f22, 432($16)
+ ldt $f23, 440($16)
+ ldt $f24, 448($16)
+ ldt $f25, 456($16)
+ ldt $f26, 464($16)
+ ldt $f27, 472($16)
+ ldt $f28, 480($16)
+ ldt $f29, 488($16)
+ ldt $f30, 496($16)
+ ldq $16, 128($16)
+ ret $31, ($26), 1
+END(_ZNK7_Unwind15Registers_Alpha6jumptoEv)
+#endif
