Module Name: src
Committed By: joerg
Date: Sat Apr 26 20:15:48 UTC 2014
Modified Files:
src/share/mk: bsd.own.mk
src/sys/lib/libunwind: Registers.hpp unwind_registers.S
Log Message:
Add initial unwind support for MIPS and MIPS64.
To generate a diff of this commit:
cvs rdiff -u -r1.800 -r1.801 src/share/mk/bsd.own.mk
cvs rdiff -u -r1.13 -r1.14 src/sys/lib/libunwind/Registers.hpp
cvs rdiff -u -r1.11 -r1.12 src/sys/lib/libunwind/unwind_registers.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/share/mk/bsd.own.mk
diff -u src/share/mk/bsd.own.mk:1.800 src/share/mk/bsd.own.mk:1.801
--- src/share/mk/bsd.own.mk:1.800 Tue Apr 22 13:20:58 2014
+++ src/share/mk/bsd.own.mk Sat Apr 26 20:15:48 2014
@@ -1,4 +1,4 @@
-# $NetBSD: bsd.own.mk,v 1.800 2014/04/22 13:20:58 joerg Exp $
+# $NetBSD: bsd.own.mk,v 1.801 2014/04/26 20:15:48 joerg Exp $
# This needs to be before bsd.init.mk
.if defined(BSD_MK_COMPAT_FILE)
@@ -97,6 +97,10 @@ _LIBC_UNWIND_SUPPORT.alpha= yes
_LIBC_UNWIND_SUPPORT.hppa= yes
_LIBC_UNWIND_SUPPORT.i386= yes
_LIBC_UNWIND_SUPPORT.m68k= yes
+_LIBC_UNWIND_SUPPORT.mipseb= yes
+_LIBC_UNWIND_SUPPORT.mipsel= yes
+_LIBC_UNWIND_SUPPORT.mips64eb= yes
+_LIBC_UNWIND_SUPPORT.mipse64l= yes
_LIBC_UNWIND_SUPPORT.powerpc= yes
_LIBC_UNWIND_SUPPORT.sh3el= yes
_LIBC_UNWIND_SUPPORT.sh3eb= yes
Index: src/sys/lib/libunwind/Registers.hpp
diff -u src/sys/lib/libunwind/Registers.hpp:1.13 src/sys/lib/libunwind/Registers.hpp:1.14
--- src/sys/lib/libunwind/Registers.hpp:1.13 Sat Apr 19 21:21:24 2014
+++ src/sys/lib/libunwind/Registers.hpp Sat Apr 26 20:15:48 2014
@@ -793,6 +793,150 @@ private:
uint32_t fpreg[56];
};
+enum {
+ DWARF_MIPS_R1 = 0,
+ DWARF_MIPS_R31 = 31,
+ DWARF_MIPS_F0 = 32,
+ DWARF_MIPS_F31 = 63,
+
+ REGNO_MIPS_PC = 0,
+ REGNO_MIPS_R1 = 0,
+ REGNO_MIPS_R29 = 29,
+ REGNO_MIPS_R31 = 31,
+ REGNO_MIPS_F0 = 33,
+ REGNO_MIPS_F31 = 64
+};
+
+class Registers_MIPS {
+public:
+ enum {
+ LAST_REGISTER = REGNO_MIPS_F31,
+ LAST_RESTORE_REG = REGNO_MIPS_F31,
+ RETURN_REG = REGNO_MIPS_R31,
+ RETURN_OFFSET = 0,
+ };
+
+ __dso_hidden Registers_MIPS();
+
+ static int dwarf2regno(int num) {
+ if (num >= DWARF_MIPS_R1 && num <= DWARF_MIPS_R31)
+ return REGNO_MIPS_R1 + (num - DWARF_MIPS_R1);
+ if (num >= DWARF_MIPS_F0 && num <= DWARF_MIPS_F31)
+ return REGNO_MIPS_F0 + (num - DWARF_MIPS_F0);
+ return LAST_REGISTER + 1;
+ }
+
+ bool validRegister(int num) const {
+ return num >= REGNO_MIPS_PC && num <= REGNO_MIPS_R31;
+ }
+
+ uint64_t getRegister(int num) const {
+ assert(validRegister(num));
+ return reg[num];
+ }
+
+ void setRegister(int num, uint64_t value) {
+ assert(validRegister(num));
+ reg[num] = value;
+ }
+
+ uint64_t getIP() const { return reg[REGNO_MIPS_PC]; }
+
+ void setIP(uint64_t value) { reg[REGNO_MIPS_PC] = value; }
+
+ uint64_t getSP() const { return reg[REGNO_MIPS_R29]; }
+
+ void setSP(uint64_t value) { reg[REGNO_MIPS_R29] = value; }
+
+ bool validFloatVectorRegister(int num) const {
+ return num >= DWARF_MIPS_F0 && num <= DWARF_MIPS_F31;
+ }
+
+ void copyFloatVectorRegister(int num, uint64_t addr_) {
+ assert(validFloatVectorRegister(num));
+ const void *addr = reinterpret_cast<const void *>(addr_);
+ memcpy(fpreg + (num - REGNO_MIPS_F0), addr, sizeof(fpreg[0]));
+ }
+
+ __dso_hidden void jumpto() const __dead;
+
+private:
+ uint32_t reg[REGNO_MIPS_R31 + 1];
+ uint64_t fpreg[32];
+};
+
+enum {
+ DWARF_MIPS64_R1 = 0,
+ DWARF_MIPS64_R31 = 31,
+ DWARF_MIPS64_F0 = 32,
+ DWARF_MIPS64_F31 = 63,
+
+ REGNO_MIPS64_PC = 0,
+ REGNO_MIPS64_R1 = 0,
+ REGNO_MIPS64_R29 = 29,
+ REGNO_MIPS64_R31 = 31,
+ REGNO_MIPS64_F0 = 33,
+ REGNO_MIPS64_F31 = 64
+};
+
+class Registers_MIPS64 {
+public:
+ enum {
+ LAST_REGISTER = REGNO_MIPS64_F31,
+ LAST_RESTORE_REG = REGNO_MIPS64_F31,
+ RETURN_REG = REGNO_MIPS64_R31,
+ RETURN_OFFSET = 0,
+ };
+
+ __dso_hidden Registers_MIPS64();
+
+ static int dwarf2regno(int num) {
+ if (num >= DWARF_MIPS64_R1 && num <= DWARF_MIPS64_R31)
+ return REGNO_MIPS64_R1 + (num - DWARF_MIPS64_R1);
+ if (num >= DWARF_MIPS64_F0 && num <= DWARF_MIPS64_F31)
+ return REGNO_MIPS64_F0 + (num - DWARF_MIPS64_F0);
+ return LAST_REGISTER + 1;
+ }
+
+ bool validRegister(int num) const {
+ return num >= REGNO_MIPS64_PC && num <= REGNO_MIPS64_R31;
+ }
+
+ uint64_t getRegister(int num) const {
+ assert(validRegister(num));
+ return reg[num];
+ }
+
+ void setRegister(int num, uint64_t value) {
+ assert(validRegister(num));
+ reg[num] = value;
+ }
+
+ uint64_t getIP() const { return reg[REGNO_MIPS64_PC]; }
+
+ void setIP(uint64_t value) { reg[REGNO_MIPS64_PC] = value; }
+
+ uint64_t getSP() const { return reg[REGNO_MIPS64_R29]; }
+
+ void setSP(uint64_t value) { reg[REGNO_MIPS64_R29] = value; }
+
+ bool validFloatVectorRegister(int num) const {
+ return num >= DWARF_MIPS64_F0 && num <= DWARF_MIPS64_F31;
+ }
+
+ void copyFloatVectorRegister(int num, uint64_t addr_) {
+ assert(validFloatVectorRegister(num));
+ const void *addr = reinterpret_cast<const void *>(addr_);
+ memcpy(fpreg + (num - REGNO_MIPS64_F0), addr, sizeof(fpreg[0]));
+ }
+
+ __dso_hidden void jumpto() const __dead;
+
+private:
+ uint64_t reg[REGNO_MIPS64_R31 + 1];
+ uint64_t fpreg[32];
+};
+
#if __i386__
typedef Registers_x86 NativeUnwindRegisters;
#elif __x86_64__
@@ -805,6 +949,10 @@ typedef Registers_arm32 NativeUnwindRegi
typedef Registers_vax NativeUnwindRegisters;
#elif __m68k__
typedef Registers_M68K NativeUnwindRegisters;
+#elif __mips_n64 || __mips_n32
+typedef Registers_MIPS64 NativeUnwindRegisters;
+#elif __mips__
+typedef Registers_MIPS NativeUnwindRegisters;
#elif __sh3__
typedef Registers_SH3 NativeUnwindRegisters;
#elif __sparc64__
Index: src/sys/lib/libunwind/unwind_registers.S
diff -u src/sys/lib/libunwind/unwind_registers.S:1.11 src/sys/lib/libunwind/unwind_registers.S:1.12
--- src/sys/lib/libunwind/unwind_registers.S:1.11 Sat Apr 19 21:21:24 2014
+++ src/sys/lib/libunwind/unwind_registers.S Sat Apr 26 20:15:48 2014
@@ -733,6 +733,298 @@ LEAF_NOPROFILE(_ZNK7_Unwind15Registers_A
END(_ZNK7_Unwind15Registers_Alpha6jumptoEv)
#endif
+#if defined(__mips_n64) || defined(__mips_n32)
+ .set noat
+LEAF(_ZN7_Unwind16Registers_MIPS64C1Ev)
+#if 0
+ FP_S $f0, 256($4)
+ FP_S $f1, 264($4)
+ FP_S $f2, 272($4)
+ FP_S $f3, 280($4)
+ FP_S $f4, 288($4)
+ FP_S $f5, 296($4)
+ FP_S $f6, 304($4)
+ FP_S $f7, 312($4)
+ FP_S $f8, 320($4)
+ FP_S $f9, 328($4)
+ FP_S $f10, 336($4)
+ FP_S $f11, 344($4)
+ FP_S $f12, 352($4)
+ FP_S $f13, 360($4)
+ FP_S $f14, 368($4)
+ FP_S $f15, 376($4)
+ FP_S $f16, 384($4)
+ FP_S $f17, 392($4)
+ FP_S $f18, 400($4)
+ FP_S $f19, 408($4)
+ FP_S $f20, 416($4)
+ FP_S $f21, 424($4)
+ FP_S $f22, 432($4)
+ FP_S $f23, 440($4)
+ FP_S $f24, 448($4)
+ FP_S $f25, 456($4)
+ FP_S $f26, 464($4)
+ FP_S $f27, 472($4)
+ FP_S $f28, 480($4)
+ FP_S $f29, 488($4)
+ FP_S $f30, 496($4)
+ FP_S $f31, 504($4)
+#endif
+ sd $31, 0($4)
+ sd $1, 4($4)
+ sd $2, 8($4)
+ sd $3, 12($4)
+ sd $4, 16($4)
+ sd $5, 20($4)
+ sd $6, 24($4)
+ sd $7, 28($4)
+ sd $8, 32($4)
+ sd $9, 36($4)
+ sd $10, 40($4)
+ sd $11, 44($4)
+ sd $12, 48($4)
+ sd $13, 52($4)
+ sd $14, 56($4)
+ sd $15, 60($4)
+ sd $16, 64($4)
+ sd $17, 68($4)
+ sd $18, 72($4)
+ sd $19, 76($4)
+ sd $20, 80($4)
+ sd $21, 84($4)
+ sd $22, 88($4)
+ sd $23, 92($4)
+ sd $24, 96($4)
+ sd $25, 100($4)
+ sd $26, 104($4)
+ sd $27, 108($4)
+ sd $28, 112($4)
+ sd $29, 116($4)
+ sd $30, 120($4)
+ sd $31, 124($4)
+ jr $31
+ nop
+END(_ZN7_Unwind16Registers_MIPS64C1Ev)
+
+LEAF(_ZNK7_Unwind16Registers_MIPS646jumptoEv)
+#if 0
+ FP_L $f0, 256($4)
+ FP_L $f1, 264($4)
+ FP_L $f2, 272($4)
+ FP_L $f3, 280($4)
+ FP_L $f4, 288($4)
+ FP_L $f5, 296($4)
+ FP_L $f6, 304($4)
+ FP_L $f7, 312($4)
+ FP_L $f8, 320($4)
+ FP_L $f9, 328($4)
+ FP_L $f10, 336($4)
+ FP_L $f11, 344($4)
+ FP_L $f12, 352($4)
+ FP_L $f13, 360($4)
+ FP_L $f14, 368($4)
+ FP_L $f15, 376($4)
+ FP_L $f16, 384($4)
+ FP_L $f17, 392($4)
+ FP_L $f18, 400($4)
+ FP_L $f19, 408($4)
+ FP_L $f20, 416($4)
+ FP_L $f21, 424($4)
+ FP_L $f22, 432($4)
+ FP_L $f23, 440($4)
+ FP_L $f24, 448($4)
+ FP_L $f25, 456($4)
+ FP_L $f26, 464($4)
+ FP_L $f27, 472($4)
+ FP_L $f28, 480($4)
+ FP_L $f29, 488($4)
+ FP_L $f30, 496($4)
+ FP_L $f31, 504($4)
+#endif
+
+ ld $31, 0($4)
+ ld $1, 8($4)
+ ld $2, 16($4)
+ ld $3, 24($4)
+ ld $5, 40($4)
+ ld $6, 48($4)
+ ld $7, 56($4)
+ ld $8, 64($4)
+ ld $9, 72($4)
+ ld $10, 80($4)
+ ld $11, 88($4)
+ ld $12, 96($4)
+ ld $13, 104($4)
+ ld $14, 112($4)
+ ld $15, 120($4)
+ ld $16, 128($4)
+ ld $17, 136($4)
+ ld $18, 144($4)
+ ld $19, 152($4)
+ ld $20, 160($4)
+ ld $21, 168($4)
+ ld $22, 176($4)
+ ld $23, 184($4)
+ ld $24, 192($4)
+ ld $25, 200($4)
+ ld $26, 208($4)
+ ld $27, 216($4)
+ ld $28, 224($4)
+ ld $29, 232($4)
+ ld $30, 240($4)
+ ld $4, 32($4)
+ jr $31
+ nop
+END(_ZNK7_Unwind16Registers_MIPS646jumptoEv)
+#elif defined(__mips__)
+ .set noat
+LEAF(_ZN7_Unwind14Registers_MIPSC1Ev)
+#if 0
+#if __mips > 1
+ FP_S $f0, 128($4)
+ FP_S $f1, 136($4)
+ FP_S $f2, 144($4)
+ FP_S $f3, 152($4)
+ FP_S $f4, 160($4)
+ FP_S $f5, 168($4)
+ FP_S $f6, 176($4)
+ FP_S $f7, 184($4)
+ FP_S $f8, 192($4)
+ FP_S $f9, 200($4)
+ FP_S $f10, 208($4)
+ FP_S $f11, 216($4)
+ FP_S $f12, 224($4)
+ FP_S $f13, 232($4)
+ FP_S $f14, 240($4)
+ FP_S $f15, 248($4)
+ FP_S $f16, 256($4)
+ FP_S $f17, 264($4)
+ FP_S $f18, 272($4)
+ FP_S $f19, 280($4)
+ FP_S $f20, 288($4)
+ FP_S $f21, 296($4)
+ FP_S $f22, 304($4)
+ FP_S $f23, 312($4)
+ FP_S $f24, 320($4)
+ FP_S $f25, 328($4)
+ FP_S $f26, 336($4)
+ FP_S $f27, 344($4)
+ FP_S $f28, 352($4)
+ FP_S $f29, 360($4)
+ FP_S $f30, 368($4)
+ FP_S $f31, 376($4)
+#endif
+#endif
+ sw $31, 0($4)
+ sw $1, 4($4)
+ sw $2, 8($4)
+ sw $3, 12($4)
+ sw $4, 16($4)
+ sw $5, 20($4)
+ sw $6, 24($4)
+ sw $7, 28($4)
+ sw $8, 32($4)
+ sw $9, 36($4)
+ sw $10, 40($4)
+ sw $11, 44($4)
+ sw $12, 48($4)
+ sw $13, 52($4)
+ sw $14, 56($4)
+ sw $15, 60($4)
+ sw $16, 64($4)
+ sw $17, 68($4)
+ sw $18, 72($4)
+ sw $19, 76($4)
+ sw $20, 80($4)
+ sw $21, 84($4)
+ sw $22, 88($4)
+ sw $23, 92($4)
+ sw $24, 96($4)
+ sw $25, 100($4)
+ sw $26, 104($4)
+ sw $27, 108($4)
+ sw $28, 112($4)
+ sw $29, 116($4)
+ sw $30, 120($4)
+ sw $31, 124($4)
+ jr $31
+ nop
+END(_ZN7_Unwind14Registers_MIPSC1Ev)
+
+LEAF(_ZNK7_Unwind14Registers_MIPS6jumptoEv)
+#if 0
+#if __mips > 1
+ FP_L $f0, 128($4)
+ FP_L $f1, 136($4)
+ FP_L $f2, 144($4)
+ FP_L $f3, 152($4)
+ FP_L $f4, 160($4)
+ FP_L $f5, 168($4)
+ FP_L $f6, 176($4)
+ FP_L $f7, 184($4)
+ FP_L $f8, 192($4)
+ FP_L $f9, 200($4)
+ FP_L $f10, 208($4)
+ FP_L $f11, 216($4)
+ FP_L $f12, 224($4)
+ FP_L $f13, 232($4)
+ FP_L $f14, 240($4)
+ FP_L $f15, 248($4)
+ FP_L $f16, 256($4)
+ FP_L $f17, 264($4)
+ FP_L $f18, 272($4)
+ FP_L $f19, 280($4)
+ FP_L $f20, 288($4)
+ FP_L $f21, 296($4)
+ FP_L $f22, 304($4)
+ FP_L $f23, 312($4)
+ FP_L $f24, 320($4)
+ FP_L $f25, 328($4)
+ FP_L $f26, 336($4)
+ FP_L $f27, 344($4)
+ FP_L $f28, 352($4)
+ FP_L $f29, 360($4)
+ FP_L $f30, 368($4)
+ FP_L $f31, 376($4)
+#endif
+#endif
+
+ lw $31, 0($4)
+ lw $1, 4($4)
+ lw $2, 8($4)
+ lw $3, 12($4)
+ lw $5, 20($4)
+ lw $6, 24($4)
+ lw $7, 28($4)
+ lw $8, 32($4)
+ lw $9, 36($4)
+ lw $10, 40($4)
+ lw $11, 44($4)
+ lw $12, 48($4)
+ lw $13, 52($4)
+ lw $14, 56($4)
+ lw $15, 60($4)
+ lw $16, 64($4)
+ lw $17, 68($4)
+ lw $18, 72($4)
+ lw $19, 76($4)
+ lw $20, 80($4)
+ lw $21, 84($4)
+ lw $22, 88($4)
+ lw $23, 92($4)
+ lw $24, 96($4)
+ lw $25, 100($4)
+ lw $26, 104($4)
+ lw $27, 108($4)
+ lw $28, 112($4)
+ lw $29, 116($4)
+ lw $30, 120($4)
+ lw $4, 16($4)
+ jr $31
+ nop
+END(_ZNK7_Unwind14Registers_MIPS6jumptoEv)
+#endif
+
#if defined(__hppa__)
LEAF_ENTRY_NOPROFILE(_ZN7_Unwind14Registers_HPPAC1Ev)
stw %r2, 0(%r26)
