Module Name: src
Committed By: msaitoh
Date: Thu Jul 3 17:24:33 UTC 2014
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
Fix some entries:
- Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
- Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
- Desc 0x57 and 0x59 are 4K fixed DTLB.
- Fix string of desc 0xc2 and it's not fixed to 4K.
- Desc 0xca is 4K fixed L2 shared TLB.
- Add desc 0xa0.
BUG: A lot of CPUs have multiple CAI_DTLB and/or CAI_DTLB2 entries. Currently
TLB info is indexed in ci_cinfo[CAI_COUNT], so some info is overwritten.
Nowadays CPUs have very complexed TLBs. It's hard to manage with CAI_* index.
We should think to separate TLB info structure from ci_cinfo[CAI_COUNT]
in struct cpu_info.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.17 src/sys/arch/x86/include/cacheinfo.h:1.18
--- src/sys/arch/x86/include/cacheinfo.h:1.17 Mon Oct 28 05:41:49 2013
+++ src/sys/arch/x86/include/cacheinfo.h Thu Jul 3 17:24:33 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.17 2013/10/28 05:41:49 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.18 2014/07/03 17:24:33 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -224,29 +224,30 @@ __CI_TBL(CAI_ITLB, 0x4f, 0xff, 32,
__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
-__CI_TBL(CAI_ITLB, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \
+__CI_TBL(CAI_ITLB2, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \
__CI_TBL(CAI_DTLB2, 0x56, 4, 16, 4 * 1024 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0x57, 4, 16, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0x59, 0xff, 16, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \
+__CI_TBL(CAI_DTLB, 0x57, 4, 16, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB, 0x59, 0xff, 16, 4 * 1024, NULL), \
+__CI_TBL(CAI_DTLB2, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \
__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
__CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \
__CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \
__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
+__CI_TBL(CAI_DTLB, 0xa0, 0xff, 32, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
-__CI_TBL(CAI_ITLB, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \
+__CI_TBL(CAI_ITLB2, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \
__CI_TBL(CAI_ITLB, 0xb2, 4, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb5, 8, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb6, 8,128, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xba, 4, 64, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB, 0xc0, 4, 8, 4 * 1024, "4K/4M: 8 entries"), \
+__CI_TBL(CAI_DTLB2, 0xc0, 4, 8, 4 * 1024, "4K/4M: 8 entries"), \
__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "4K/2M: 1024 entries"), \
-__CI_TBL(CAI_DTLB, 0xc2, 4, 16, 4 * 1024, "2M/4M: 16 entries"), \
-__CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, "4K/4M: 512 entries"), \
+__CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "4K/2M: 16 entries"), \
+__CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \
__CI_TBL(CAI_ICACHE, 0x09, 4, 32 * 1024, 64, NULL), \
