Module Name: src
Committed By: skrll
Date: Wed Jul 30 07:11:57 UTC 2014
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_arm11x6.S
Log Message:
Trailing whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.4 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.5
--- src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S:1.4 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S Wed Jul 30 07:11:57 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.4 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.5 2014/07/30 07:11:57 skrll Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -63,7 +63,7 @@
#include <machine/asm.h>
#include <arm/locore.h>
-RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.4 2014/03/30 01:15:03 matt Exp $")
+RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.5 2014/07/30 07:11:57 skrll Exp $")
#if 0
#define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -74,7 +74,7 @@ RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v
*
* Erratum 411920 in ARM1136 (fixed in r1p4)
* Erratum 415045 in ARM1176 (fixed in r0p5?)
- *
+ *
* - value of arg 'reg' Should Be Zero
*/
#define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -143,20 +143,20 @@ ENTRY_NP(arm11x6_icache_sync_range)
/* Erratum ARM1176 371367 */
mrs r2, cpsr /* save the CPSR */
cpsid ifa /* disable interrupts (irq,fiq,abort) */
- mov r3, #0
+ mov r3, #0
mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
- add r3, pc, #0x24
+ add r3, pc, #0x24
mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
msr cpsr_cx, r2 /* local_irq_restore */
- nop
- nop
- nop
- nop
- nop
- nop
- nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
mcrr p15, 0, r1, r0, c12 /* clean and invalidate D cache range */ /* XXXNH */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
@@ -170,20 +170,20 @@ ENTRY_NP(arm11x6_idcache_wbinv_range)
/* Erratum ARM1176 371367 */
mrs r2, cpsr /* save the CPSR */
cpsid ifa /* disable interrupts (irq,fiq,abort) */
- mov r3, #0
+ mov r3, #0
mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
- add r3, pc, #0x24
+ add r3, pc, #0x24
mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
msr cpsr_cx, r2 /* local_irq_restore */
- nop
- nop
- nop
- nop
- nop
- nop
- nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
@@ -192,7 +192,7 @@ END(arm11x6_idcache_wbinv_range)
/*
* Preload the cache before issuing the WFI by conditionally disabling the
- * mcr intstructions the first time around the loop. Ensure the function is
+ * mcr intstructions the first time around the loop. Ensure the function is
* cacheline aligned.
*/
.arch armv6
