Module Name: src
Committed By: reinoud
Date: Thu Aug 28 17:59:46 UTC 2014
Modified Files:
src/sys/arch/arm/samsung: exynos4_reg.h exynos5_reg.h
Log Message:
Add comments to Exynos4 PLL registers and add Exynos5 PLL registers
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/samsung/exynos4_reg.h
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/samsung/exynos5_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/samsung/exynos4_reg.h
diff -u src/sys/arch/arm/samsung/exynos4_reg.h:1.9 src/sys/arch/arm/samsung/exynos4_reg.h:1.10
--- src/sys/arch/arm/samsung/exynos4_reg.h:1.9 Thu Aug 28 11:48:22 2014
+++ src/sys/arch/arm/samsung/exynos4_reg.h Thu Aug 28 17:59:46 2014
@@ -116,11 +116,11 @@
#define EXYNOS4_SYSREG_OFFSET 0x00010000
#define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */
#define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* Clock(s) management unit */
-#define EXYNOS4_CMU_EPPL 0x0003C010
-#define EXYNOS4_CMU_VPPL 0x0003C020
+#define EXYNOS4_CMU_EPPL 0x0003C010 /* Audio and ext. interf. clock */
+#define EXYNOS4_CMU_VPPL 0x0003C020 /* Video core (dither?) clock */
#define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* Clock(s) management unit */
-#define EXYNOS4_CMU_MPLL 0x00040008
-#define EXYNOS4_CMU_APLL 0x00044000
+#define EXYNOS4_CMU_MPLL 0x00040008 /* MEM cntr. clock */
+#define EXYNOS4_CMU_APLL 0x00044000 /* ARM core clock */
#define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */
#define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */
#define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */
Index: src/sys/arch/arm/samsung/exynos5_reg.h
diff -u src/sys/arch/arm/samsung/exynos5_reg.h:1.12 src/sys/arch/arm/samsung/exynos5_reg.h:1.13
--- src/sys/arch/arm/samsung/exynos5_reg.h:1.12 Thu Aug 21 14:06:39 2014
+++ src/sys/arch/arm/samsung/exynos5_reg.h Thu Aug 28 17:59:46 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos5_reg.h,v 1.12 2014/08/21 14:06:39 reinoud Exp $ */
+/* $NetBSD: exynos5_reg.h,v 1.13 2014/08/28 17:59:46 reinoud Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -56,8 +56,15 @@
#define EXYNOS5_SDRAM_PBASE 0x40000000
#define EXYNOS5_CMU_COREPART_OFFSET 0x00010000
+#define EXYNOS5_CMU_APLL 0x00010000 /* ARM core clock */
+#define EXYNOS5_CMU_MPLL 0x00014000 /* MEM cntr. clock */
#define EXYNOS5_CMU_TOPPART_OFFSET 0x00020000
+#define EXYNOS5_CMU_CPLL 0x00020020 /* Video hardware codec clock */
+#define EXYNOS5_CMU_EPLL 0x00020030 /* Audio and ext. interf. clock */
+#define EXYNOS5_CMU_VPLL 0x00020040 /* Dither PLL (EMI reduction) clock */
+#define EXYNOS5_CMU_GPLL 0x00020050 /* Graphic 3D proc. clock */
#define EXYNOS5_CMU_MEMPART_OFFSET 0x00030000
+#define EXYNOS5_CMU_BPLL 0x00030010
#define EXYNOS5_ALIVE_OFFSET 0x00040000
#define EXYNOS5_SYSREG_OFFSET 0x00050000
#define EXYNOS5_TMU_OFFSET 0x00060000
