Module Name: src
Committed By: reinoud
Date: Tue Sep 30 14:23:41 UTC 2014
Modified Files:
src/sys/arch/arm/samsung: exynos_soc.c exynos_usb.c exynos_var.h
Log Message:
arch/arm/samsung/ cleanup : move SoC specific power and phy routines into
exynos_soc.c and move Odroid board specific tweaks to odroid_machdep.c
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/samsung/exynos_soc.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/samsung/exynos_usb.c
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/samsung/exynos_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/samsung/exynos_soc.c
diff -u src/sys/arch/arm/samsung/exynos_soc.c:1.22 src/sys/arch/arm/samsung/exynos_soc.c:1.23
--- src/sys/arch/arm/samsung/exynos_soc.c:1.22 Tue Sep 30 12:55:29 2014
+++ src/sys/arch/arm/samsung/exynos_soc.c Tue Sep 30 14:23:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_soc.c,v 1.22 2014/09/30 12:55:29 reinoud Exp $ */
+/* $NetBSD: exynos_soc.c,v 1.23 2014/09/30 14:23:41 reinoud Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.22 2014/09/30 12:55:29 reinoud Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.23 2014/09/30 14:23:41 reinoud Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -201,6 +201,7 @@ exynos_cpu_boot(int cpu)
}
+#ifdef EXYNOS4
/*
* The latency values used below are `magic' and probably chosen empirically.
* For the 4210 variant the data latency is lower, a 0x110. This is currently
@@ -211,7 +212,7 @@ exynos_cpu_boot(int cpu)
*/
int
-exynos_l2cc_init(void)
+exynos4_l2cc_init(void)
{
const uint32_t tag_latency = 0x110;
const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120;
@@ -268,6 +269,7 @@ exynos_l2cc_init(void)
return 0;
}
+#endif
#endif /* ARM_TRUSTZONE_FIRMWARE */
@@ -469,19 +471,6 @@ exynos_dump_clocks(void)
/* XXX clock stuff needs major work XXX */
-static void
-exynos_init_clkout_for_usb(void)
-{
-#ifdef EXYNOS4
- bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
- EXYNOS_PMU_DEBUG_CLKOUT, 0x900);
-#endif
-#ifdef EXYNOS5
- bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
- EXYNOS_PMU_DEBUG_CLKOUT, 0x1000);
-#endif
-}
-
void
exynos_clocks_bootstrap(void)
@@ -606,7 +595,7 @@ exynos_device_register(device_t self, vo
* XXX KLUDGE ALERT XXX
* The iot mainbus supplies is completely wrong since it scales
* addresses by 2. The simplest remedy is to replace with our
- * bus space used for the armcore regisers (which armperiph uses).
+ * bus space used for the armcore registers (which armperiph uses).
*/
struct mainbus_attach_args * const mb = aux;
mb->mb_iot = &exynos_bs_tag;
@@ -678,3 +667,339 @@ exynos_device_register_post_config(devic
exyo_device_register_post_config(self, aux);
}
+
+/*
+ * USB power SoC dependent handling
+ */
+
+#ifdef EXYNOS4
+static struct exynos_gpio_pinset e4_uhost_pwr_pinset = {
+ .pinset_group = "ETC6",
+ .pinset_func = 0,
+ .pinset_mask = __BIT(6) | __BIT(7),
+};
+#endif
+
+
+#ifdef EXYNOS5
+static struct exynos_gpio_pinset e5_uhost_pwr_pinset = {
+ .pinset_group = "ETC6",
+ .pinset_func = 0,
+ .pinset_mask = __BIT(5) | __BIT(6),
+};
+static struct exynos_gpio_pinset e5_usb3_bus0_pinset = {
+ .pinset_group = "GPK3",
+ .pinset_func = 2,
+ .pinset_mask = __BIT(0) | __BIT(1) | __BIT(3),
+};
+static struct exynos_gpio_pinset e5_usb3_bus1_pinset = {
+ .pinset_group = "GPK2",
+ .pinset_func = 2,
+ .pinset_mask = __BIT(4) | __BIT(5) | __BIT(7),
+};
+#endif
+
+
+void
+exynos_usb_soc_powerup(void)
+{
+ struct exynos_gpio_pindata XuhostOVERCUR;
+ struct exynos_gpio_pindata XuhostPWREN;
+
+#ifdef EXYNOS4
+ exynos_gpio_pinset_acquire(&e4_uhost_pwr_pinset);
+ exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 6, &XuhostPWREN);
+ exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 7, &XuhostOVERCUR);
+
+ /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
+ exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
+ DELAY(80000);
+#endif
+#ifdef EXYNOS5
+ if (IS_EXYNOS5410_P()) {
+ struct exynos_gpio_pindata Xovercur2, Xovercur3;
+ struct exynos_gpio_pindata Xvbus;
+
+ /* BUS 0 */
+ exynos_gpio_pinset_acquire(&e5_usb3_bus0_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 0, &Xovercur2);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 1, &Xovercur3);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 3, &Xvbus);
+
+ /* enable power and set overcur inactive by pulling them up */
+ exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP);
+
+ /* BUS 1 */
+ exynos_gpio_pinset_acquire(&e5_usb3_bus1_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 4, &Xovercur2);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 5, &Xovercur3);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 7, &Xvbus);
+
+ /* enable power and set overcur inactive by pulling them up */
+ exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP);
+
+ /* enable power to the hub */
+ exynos_gpio_pinset_acquire(&e5_uhost_pwr_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 5, &XuhostPWREN);
+ exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 6, &XuhostOVERCUR);
+
+ /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
+ exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
+ DELAY(80000);
+ }
+ /* XXX 5422 XXX */
+#endif
+}
+
+
+/*
+ * USB Phy SoC dependent handling
+ */
+
+/* XXX 5422 not handled since its unknown how it handles this XXX*/
+static void
+exynos_usb2_set_isolation(bool on)
+{
+ uint32_t en_mask, regval;
+ bus_addr_t reg;
+
+ /* enable PHY */
+ reg = EXYNOS_PMU_USB_PHY_CTRL;
+
+ if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) {
+ /* set usbhost mode */
+ regval = on ? 0 : USB20_PHY_HOST_LINK_EN;
+ bus_space_write_4(&exynos_bs_tag, exynos_sysreg_bsh,
+ EXYNOS5_SYSREG_USB20_PHY_TYPE, regval);
+ reg = EXYNOS_PMU_USBHOST_PHY_CTRL;
+ }
+
+ /* do enable PHY */
+ en_mask = PMU_PHY_ENABLE;
+ regval = bus_space_read_4(&exynos_bs_tag, exynos_pmu_bsh, reg);
+ regval = on ? regval & ~en_mask : regval | en_mask;
+
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ reg, regval);
+
+ if (IS_EXYNOS4X12_P()) {
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval);
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval);
+ }
+}
+
+
+#ifdef EXYNOS4
+static void
+exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
+{
+ uint32_t phypwr, rstcon, clkreg;
+
+ /* write clock value */
+ clkreg = FSEL_CLKSEL_24M;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYCLK, clkreg);
+
+ /* set device and host to normal */
+ phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR);
+
+ /* enable analog, enable otg, unsleep phy0 (host) */
+ phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR, phypwr);
+
+ if (IS_EXYNOS4X12_P()) {
+ /* enable hsic0 (host), enable hsic1 and phy1 (otg) */
+ phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR);
+ phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
+ PHYPWR_NORMAL_MASK_HSIC1 |
+ PHYPWR_NORMAL_MASK_PHY1);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR, phypwr);
+ }
+
+ /* reset both phy and link of device */
+ rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON);
+ rstcon |= RSTCON_DEVPHY_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ DELAY(10000);
+ rstcon &= ~RSTCON_DEVPHY_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+
+ if (IS_EXYNOS4X12_P()) {
+ /* reset both phy and link of host */
+ rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON);
+ rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ DELAY(10000);
+ rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ }
+
+ /* wait for everything to be initialized */
+ DELAY(80000);
+}
+#endif
+
+
+#ifdef EXYNOS5
+static void
+exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
+{
+ uint32_t phyhost; //, phyotg;
+ uint32_t phyhsic1, phyhsic2, hsic_ctrl;
+ uint32_t ehcictrl; //, ohcictrl;
+
+ /* host configuration: */
+ phyhost = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_CTRL0);
+
+ /* host phy reference clock; assumption its 24 MHz now */
+ phyhost &= ~HOST_CTRL0_FSEL_MASK;
+ phyhost |= __SHIFTIN(HOST_CTRL0_FSEL_MASK, FSEL_CLKSEL_24M);
+
+ /* enable normal mode of operation */
+ phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+
+ /* host phy reset */
+ phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL |
+ HOST_CTRL0_SIDDQ | HOST_CTRL0_COMMONON_N);
+
+ /* host link reset */
+ phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST;
+
+ /* do the reset */
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_CTRL0, phyhost);
+ DELAY(10000);
+ phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_CTRL0, phyhost);
+
+#if 0
+ /* otg configuration: */
+ phyotg = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_OTG_SYS);
+
+ /* otg phy refrence clock: assumption its 24 Mhz now */
+ phyotg &= ~OTG_SYS_FSEL_MASK;
+ phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M);
+
+ /* enable normal mode of operation */
+ phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP |
+ OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK |
+ OTG_SYS_COMMON_ON);
+
+ /* OTG phy and link reset */
+ phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST |
+ OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK;
+
+ /* do the reset */
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_OTG_SYS, phyotg);
+ DELAY(10000);
+ phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG |
+ OTG_SYS_PHYLINK_SWRST);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_OTG_SYS, phyotg);
+#endif
+
+ /* HSIC phy configuration: */
+ hsic_ctrl = HSIC_CTRL_FORCESUSPEND | HSIC_CTRL_FORCESLEEP |
+ HSIC_CTRL_SIDDQ;
+
+ phyhsic1 = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HSIC_CTRL1);
+ phyhsic2 = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HSIC_CTRL1);
+
+ phyhsic1 &= ~hsic_ctrl;
+ phyhsic2 &= ~hsic_ctrl;
+
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HSIC_CTRL1, phyhsic1);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HSIC_CTRL2, phyhsic2);
+ DELAY(10000);
+
+ hsic_ctrl = REFCLKDIV_12 | REFCLKSEL_HSIC_DEFAULT |
+ HSIC_CTRL_UTMI_SWRST;
+
+ phyhsic1 |= hsic_ctrl;
+ phyhsic2 |= hsic_ctrl;
+
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HSIC_CTRL1, phyhsic1);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HSIC_CTRL2, phyhsic2);
+
+ DELAY(10000);
+
+ hsic_ctrl = HSIC_CTRL_PHY_SWRST | HSIC_CTRL_UTMI_SWRST;
+
+ phyhsic1 &= ~hsic_ctrl;
+ phyhsic2 &= ~hsic_ctrl;
+
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HSIC_CTRL1, phyhsic1);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HSIC_CTRL2, phyhsic2);
+ DELAY(20000);
+
+ /* enable EHCI DMA burst: */
+ ehcictrl = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_EHCICTRL);
+ ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN |
+ HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
+ HOST_EHCICTRL_ENA_INCR16;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_EHCICTRL, ehcictrl);
+ DELAY(10000);
+}
+
+
+static void
+exynos5422_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
+{
+ aprint_error("%s not implemented\n", __func__);
+}
+#endif
+
+
+void
+exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh)
+{
+ /* disable phy isolation */
+ exynos_usb2_set_isolation(false);
+
+#ifdef EXYNOS4
+ exynos4_usb2phy_enable(usb2phy_bsh);
+#endif
+#ifdef EXYNOS5
+ if (IS_EXYNOS5410_P()) {
+ exynos5410_usb2phy_enable(usb2phy_bsh);
+ /* TBD: USB3 phy init */
+ } else if (IS_EXYNOS5422_P()) {
+ exynos5422_usb2phy_enable(usb2phy_bsh);
+ /* TBD: USB3 phy init */
+ }
+#endif
+}
+
+
Index: src/sys/arch/arm/samsung/exynos_usb.c
diff -u src/sys/arch/arm/samsung/exynos_usb.c:1.12 src/sys/arch/arm/samsung/exynos_usb.c:1.13
--- src/sys/arch/arm/samsung/exynos_usb.c:1.12 Tue Sep 30 12:56:26 2014
+++ src/sys/arch/arm/samsung/exynos_usb.c Tue Sep 30 14:23:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_usb.c,v 1.12 2014/09/30 12:56:26 reinoud Exp $ */
+/* $NetBSD: exynos_usb.c,v 1.13 2014/09/30 14:23:41 reinoud Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_usb.c,v 1.12 2014/09/30 12:56:26 reinoud Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_usb.c,v 1.13 2014/09/30 14:23:41 reinoud Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -78,9 +78,6 @@ struct exynos_usb_softc {
bus_space_handle_t sc_ohci_bsh;
bus_space_handle_t sc_usb2phy_bsh;
- bus_space_handle_t sc_sysreg_bsh;
- bus_space_handle_t sc_pmureg_bsh;
-
device_t sc_ohci_dev;
device_t sc_ehci_dev;
@@ -88,41 +85,14 @@ struct exynos_usb_softc {
void *sc_intrh;
} exynos_usb_sc;
+
struct exynos_usb_attach_args {
const char *name;
};
-#ifdef EXYNOS4
-static struct exynos_gpio_pinset e4_uhost_pwr_pinset = {
- .pinset_group = "ETC6",
- .pinset_func = 0,
- .pinset_mask = __BIT(6) | __BIT(7),
-};
-#endif
-
-
-#ifdef EXYNOS5
-static struct exynos_gpio_pinset e5_uhost_pwr_pinset = {
- .pinset_group = "ETC6",
- .pinset_func = 0,
- .pinset_mask = __BIT(5) | __BIT(6),
-};
-static struct exynos_gpio_pinset e5_usb3_bus0_pinset = {
- .pinset_group = "GPK3",
- .pinset_func = 2,
- .pinset_mask = __BIT(0) | __BIT(1) | __BIT(3),
-};
-static struct exynos_gpio_pinset e5_usb3_bus1_pinset = {
- .pinset_group = "GPK2",
- .pinset_func = 2,
- .pinset_mask = __BIT(4) | __BIT(5) | __BIT(7),
-};
-#endif
-
-
+/* forwards */
static int exynos_usb_intr(void *arg);
-static void exynos_usb_phy_init(struct exynos_usb_softc *sc);
static int exynos_usb_match(device_t, cfdata_t, void *);
@@ -149,8 +119,6 @@ exynos_usb_attach(device_t parent, devic
struct exynos_usb_softc * const sc = &exynos_usb_sc;
struct exyo_attach_args *exyoaa = (struct exyo_attach_args *) aux;
struct exyo_locators *loc = &exyoaa->exyo_loc;
- struct exynos_gpio_pindata XuhostOVERCUR;
- struct exynos_gpio_pindata XuhostPWREN;
bus_size_t ehci_offset, ohci_offset, usb2phy_offset;
/* no locators expected */
@@ -167,20 +135,15 @@ exynos_usb_attach(device_t parent, devic
// sc->sc_dmat = exyoaa->exyo_coherent_dmat;
#ifdef EXYNOS4
- if (IS_EXYNOS4_P()) {
- ehci_offset = EXYNOS4_USB2_HOST_EHCI_OFFSET;
- ohci_offset = EXYNOS4_USB2_HOST_OHCI_OFFSET;
- usb2phy_offset = EXYNOS4_USB2_HOST_PHYCTRL_OFFSET;
- }
+ ehci_offset = EXYNOS4_USB2_HOST_EHCI_OFFSET;
+ ohci_offset = EXYNOS4_USB2_HOST_OHCI_OFFSET;
+ usb2phy_offset = EXYNOS4_USB2_HOST_PHYCTRL_OFFSET;
#endif
#ifdef EXYNOS5
- if (IS_EXYNOS5_P()) {
- ehci_offset = EXYNOS5_USB2_HOST_EHCI_OFFSET;
- ohci_offset = EXYNOS5_USB2_HOST_OHCI_OFFSET;
- usb2phy_offset = EXYNOS5_USB2_HOST_PHYCTRL_OFFSET;
- }
+ ehci_offset = EXYNOS5_USB2_HOST_EHCI_OFFSET;
+ ohci_offset = EXYNOS5_USB2_HOST_OHCI_OFFSET;
+ usb2phy_offset = EXYNOS5_USB2_HOST_PHYCTRL_OFFSET;
#endif
- KASSERT(ehci_offset);
bus_space_subregion(sc->sc_bst, exyoaa->exyo_core_bsh,
ehci_offset, EXYNOS_BLOCK_SIZE,
@@ -192,67 +155,14 @@ exynos_usb_attach(device_t parent, devic
usb2phy_offset, EXYNOS_BLOCK_SIZE,
&sc->sc_usb2phy_bsh);
- sc->sc_pmureg_bsh = exynos_pmu_bsh;
- sc->sc_sysreg_bsh = exynos_sysreg_bsh;
-
aprint_naive("\n");
aprint_normal("\n");
/* power up USB subsystem */
-#ifdef EXYNOS4
- if (IS_EXYNOS4_P()) {
- exynos_gpio_pinset_acquire(&e4_uhost_pwr_pinset);
- exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 6, &XuhostPWREN);
- exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 7, &XuhostOVERCUR);
-
- /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
- exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
- exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
- DELAY(80000);
- }
-#endif
-#ifdef EXYNOS5
- if (IS_EXYNOS5410_P()) {
- struct exynos_gpio_pindata Xovercur2, Xovercur3;
- struct exynos_gpio_pindata Xvbus;
-
- /* BUS 0 */
- exynos_gpio_pinset_acquire(&e5_usb3_bus0_pinset);
- exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 0, &Xovercur2);
- exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 1, &Xovercur3);
- exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 3, &Xvbus);
-
- /* enable power and set overcur inactive by pulling them up */
- exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP);
- exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP);
- exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP);
-
- /* BUS 1 */
- exynos_gpio_pinset_acquire(&e5_usb3_bus1_pinset);
- exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 4, &Xovercur2);
- exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 5, &Xovercur3);
- exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 7, &Xvbus);
-
- /* enable power and set overcur inactive by pulling them up */
- exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP);
- exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP);
- exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP);
-
- /* enable power to the hub */
- exynos_gpio_pinset_acquire(&e5_uhost_pwr_pinset);
- exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 5, &XuhostPWREN);
- exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 6, &XuhostOVERCUR);
-
- /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
- exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
- exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
- DELAY(80000);
- }
-#endif
-
+ exynos_usb_soc_powerup();
/* init USB phys */
- exynos_usb_phy_init(sc);
+ exynos_usb_phy_init(sc->sc_usb2phy_bsh);
/*
* Disable interrupts
@@ -441,251 +351,3 @@ exynos_ehci_attach(device_t parent, devi
}
#endif
-
-/*
- * USB Phy init
- */
-
-/* XXX 5422 not handled since its unknown how it handles this XXX*/
-static void
-exynos_usb2_set_isolation(struct exynos_usb_softc *sc, bool on)
-{
- uint32_t en_mask, regval;
- bus_addr_t reg;
-
- /* enable PHY */
- reg = EXYNOS_PMU_USB_PHY_CTRL;
-
- if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) {
- /* set usbhost mode */
- regval = on ? 0 : USB20_PHY_HOST_LINK_EN;
- bus_space_write_4(sc->sc_bst, sc->sc_sysreg_bsh,
- EXYNOS5_SYSREG_USB20_PHY_TYPE, regval);
- reg = EXYNOS_PMU_USBHOST_PHY_CTRL;
- }
-
- /* do enable PHY */
- en_mask = PMU_PHY_ENABLE;
- regval = bus_space_read_4(sc->sc_bst, sc->sc_pmureg_bsh, reg);
- regval = on ? regval & ~en_mask : regval | en_mask;
-
- bus_space_write_4(sc->sc_bst, sc->sc_pmureg_bsh,
- reg, regval);
-
- if (IS_EXYNOS4X12_P()) {
- bus_space_write_4(sc->sc_bst, sc->sc_pmureg_bsh,
- EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval);
- bus_space_write_4(sc->sc_bst, sc->sc_pmureg_bsh,
- EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval);
- }
-}
-
-
-#ifdef EXYNOS4
-static void
-exynos4_usb2phy_enable(struct exynos_usb_softc *sc)
-{
- uint32_t phypwr, rstcon, clkreg;
-
- /* write clock value */
- clkreg = FSEL_CLKSEL_24M;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYCLK, clkreg);
-
- /* set device and host to normal */
- phypwr = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYPWR);
-
- /* enable analog, enable otg, unsleep phy0 (host) */
- phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYPWR, phypwr);
-
- if (IS_EXYNOS4X12_P()) {
- /* enable hsic0 (host), enable hsic1 and phy1 (otg) */
- phypwr = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYPWR);
- phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
- PHYPWR_NORMAL_MASK_HSIC1 |
- PHYPWR_NORMAL_MASK_PHY1);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHYPWR, phypwr);
- }
-
- /* reset both phy and link of device */
- rstcon = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON);
- rstcon |= RSTCON_DEVPHY_SWRST;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON, rstcon);
- DELAY(10000);
- rstcon &= ~RSTCON_DEVPHY_SWRST;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON, rstcon);
-
- if (IS_EXYNOS4X12_P()) {
- /* reset both phy and link of host */
- rstcon = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON);
- rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON, rstcon);
- DELAY(10000);
- rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_RSTCON, rstcon);
- }
-
- /* wait for everything to be initialized */
- DELAY(80000);
-}
-#endif
-
-
-#ifdef EXYNOS5
-static void
-exynos5410_usb2phy_enable(struct exynos_usb_softc *sc)
-{
- uint32_t phyhost; //, phyotg;
- uint32_t phyhsic1, phyhsic2, hsic_ctrl;
- uint32_t ehcictrl; //, ohcictrl;
-
- /* host configuration: */
- phyhost = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HOST_CTRL0);
-
- /* host phy reference clock; assumption its 24 MHz now */
- phyhost &= ~HOST_CTRL0_FSEL_MASK;
- phyhost |= __SHIFTIN(HOST_CTRL0_FSEL_MASK, FSEL_CLKSEL_24M);
-
- /* enable normal mode of operation */
- phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
-
- /* host phy reset */
- phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL |
- HOST_CTRL0_SIDDQ | HOST_CTRL0_COMMONON_N);
-
- /* host link reset */
- phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST;
-
- /* do the reset */
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HOST_CTRL0, phyhost);
- DELAY(10000);
- phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HOST_CTRL0, phyhost);
-
-#if 0
- /* otg configuration: */
- phyotg = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_OTG_SYS);
-
- /* otg phy refrence clock: assumption its 24 Mhz now */
- phyotg &= ~OTG_SYS_FSEL_MASK;
- phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M);
-
- /* enable normal mode of operation */
- phyotg &= ~(OTG_SYS_FORCESUSPEND | OTG_SYS_FORCESLEEP |
- OTG_SYS_SIDDQ_UOTG | OTG_SYS_REFCLKSEL_MASK |
- OTG_SYS_COMMON_ON);
-
- /* OTG phy and link reset */
- phyotg |= OTG_SYS_PHY0_SWRST | OTG_SYS_PHYLINK_SWRST |
- OTG_SYS_OTGDISABLE | OTG_SYS_REFCLKSEL_MASK;
-
- /* do the reset */
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_OTG_SYS, phyotg);
- DELAY(10000);
- phyotg &= ~(OTG_SYS_PHY0_SWRST | OTG_SYS_LINK_SWRST_UOTG |
- OTG_SYS_PHYLINK_SWRST);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_OTG_SYS, phyotg);
-#endif
-
- /* HSIC phy configuration: */
- hsic_ctrl = HSIC_CTRL_FORCESUSPEND | HSIC_CTRL_FORCESLEEP |
- HSIC_CTRL_SIDDQ;
-
- phyhsic1 = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HSIC_CTRL1);
- phyhsic2 = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HSIC_CTRL1);
-
- phyhsic1 &= ~hsic_ctrl;
- phyhsic2 &= ~hsic_ctrl;
-
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HSIC_CTRL1, phyhsic1);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HSIC_CTRL2, phyhsic2);
- DELAY(10000);
-
- hsic_ctrl = REFCLKDIV_12 | REFCLKSEL_HSIC_DEFAULT |
- HSIC_CTRL_UTMI_SWRST;
-
- phyhsic1 |= hsic_ctrl;
- phyhsic2 |= hsic_ctrl;
-
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HSIC_CTRL1, phyhsic1);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HSIC_CTRL2, phyhsic2);
-
- DELAY(10000);
-
- hsic_ctrl = HSIC_CTRL_PHY_SWRST | HSIC_CTRL_UTMI_SWRST;
-
- phyhsic1 &= ~hsic_ctrl;
- phyhsic2 &= ~hsic_ctrl;
-
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HSIC_CTRL1, phyhsic1);
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HSIC_CTRL2, phyhsic2);
- DELAY(20000);
-
- /* enable EHCI DMA burst: */
- ehcictrl = bus_space_read_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HOST_EHCICTRL);
- ehcictrl |= HOST_EHCICTRL_ENA_INCRXALIGN |
- HOST_EHCICTRL_ENA_INCR4 | HOST_EHCICTRL_ENA_INCR8 |
- HOST_EHCICTRL_ENA_INCR16;
- bus_space_write_4(sc->sc_bst, sc->sc_usb2phy_bsh,
- USB_PHY_HOST_EHCICTRL, ehcictrl);
- DELAY(10000);
-}
-
-
-static void
-exynos5422_usb2phy_enable(struct exynos_usb_softc *sc)
-{
- aprint_error_dev(sc->sc_self, "%s not implemented\n", __func__);
-}
-#endif
-
-
-static void
-exynos_usb_phy_init(struct exynos_usb_softc *sc)
-{
- /* disable phy isolation */
- exynos_usb2_set_isolation(sc, false);
-
-#ifdef EXYNOS4
- if (IS_EXYNOS4_P())
- exynos4_usb2phy_enable(sc);
-#endif
-#ifdef EXYNOS5
- if (IS_EXYNOS5410_P()) {
- exynos5410_usb2phy_enable(sc);
- /* TBD: USB3 phy init */
- }
- if (IS_EXYNOS5422_P()) {
- exynos5422_usb2phy_enable(sc);
- /* TBD: USB3 phy init */
- }
- /* XXX exynos5422 */
-#endif
-}
-
Index: src/sys/arch/arm/samsung/exynos_var.h
diff -u src/sys/arch/arm/samsung/exynos_var.h:1.17 src/sys/arch/arm/samsung/exynos_var.h:1.18
--- src/sys/arch/arm/samsung/exynos_var.h:1.17 Tue Sep 30 12:55:29 2014
+++ src/sys/arch/arm/samsung/exynos_var.h Tue Sep 30 14:23:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_var.h,v 1.17 2014/09/30 12:55:29 reinoud Exp $ */
+/* $NetBSD: exynos_var.h,v 1.18 2014/09/30 14:23:41 reinoud Exp $ */
/*-
* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
@@ -124,6 +124,9 @@ extern bus_space_handle_t exynos_sysreg_
extern void exynos_bootstrap(vaddr_t, vaddr_t);
extern void exynos_dma_bootstrap(psize_t memsize);
extern void exynos_gpio_bootstrap(void);
+extern void exynos_wdt_reset(void);
+
+extern void exynos_init_clkout_for_usb(void); // board specific
extern void exynos_clocks_bootstrap(void);
extern void exynos_sysctl_cpufreq_init(void);
@@ -131,9 +134,11 @@ extern uint64_t exynos_get_cpufreq(void)
extern void exynos_device_register(device_t self, void *aux);
extern void exynos_device_register_post_config(device_t self, void *aux);
+extern void exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh);
+extern void exynos_usb_soc_powerup(void);
+
extern void exyo_device_register(device_t self, void *aux);
extern void exyo_device_register_post_config(device_t self, void *aux);
-extern void exynos_wdt_reset(void);
extern bool exynos_gpio_pinset_available(const struct exynos_gpio_pinset *);
extern void exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *);
@@ -166,7 +171,9 @@ exynos_gpio_pindata_ctl(const struct exy
extern int exynos_do_idle(void);
extern int exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr);
extern int exynos_cpu_boot(int cpu);
-extern int exynos_l2cc_init(void);
+#ifdef EXYNOS4
+extern int exynos4_l2cc_init(void);
+#endif
#endif
#endif /* _ARM_SAMSUNG_EXYNOS_VAR_H_ */
