Module Name: src
Committed By: jmcneill
Date: Sat Nov 15 13:40:39 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_ir.c awin_reg.h
Log Message:
Fix CIR setup. Works on A31 now.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/allwinner/awin_ir.c
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/allwinner/awin_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_ir.c
diff -u src/sys/arch/arm/allwinner/awin_ir.c:1.1 src/sys/arch/arm/allwinner/awin_ir.c:1.2
--- src/sys/arch/arm/allwinner/awin_ir.c:1.1 Sun Nov 2 23:55:48 2014
+++ src/sys/arch/arm/allwinner/awin_ir.c Sat Nov 15 13:40:39 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_ir.c,v 1.1 2014/11/02 23:55:48 jmcneill Exp $ */
+/* $NetBSD: awin_ir.c,v 1.2 2014/11/15 13:40:39 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "opt_ddb.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: awin_ir.c,v 1.1 2014/11/02 23:55:48 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: awin_ir.c,v 1.2 2014/11/15 13:40:39 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -175,11 +175,11 @@ awin_ir_init(struct awin_ir_softc *sc, s
clk = bus_space_read_4(sc->sc_bst, prcm_bsh,
AWIN_A31_PRCM_CIR_CLK_REG);
clk &= ~AWIN_CLK_SRC_SEL;
- clk |= 1; /* HOSC */
+ clk |= __SHIFTIN(AWIN_CLK_SRC_SEL_CIR_HOSC, AWIN_CLK_SRC_SEL);
clk &= ~AWIN_CLK_DIV_RATIO_M;
- clk |= 7; /* (24MHz / 3MHz) - 1 */
+ clk |= __SHIFTIN(7, AWIN_CLK_DIV_RATIO_M);
clk &= ~AWIN_CLK_DIV_RATIO_N;
- clk |= 0; /* 1 - 1 */
+ clk |= __SHIFTIN(0, AWIN_CLK_DIV_RATIO_N);
clk |= AWIN_CLK_ENABLE;
bus_space_write_4(sc->sc_bst, prcm_bsh,
AWIN_A31_PRCM_CIR_CLK_REG, clk);
@@ -203,7 +203,7 @@ awin_ir_intr(void *priv)
IR_WRITE(sc, AWIN_IR_RXSTA_REG, sta & AWIN_IR_RXSTA_MASK);
- if (sta & AWIN_IR_RXSTA_RA) {
+ if (sta & AWIN_IR_RXSTA_RPE) {
mutex_enter(&sc->sc_lock);
sc->sc_avail = __SHIFTOUT(sta, AWIN_IR_RXSTA_RAC);
cv_broadcast(&sc->sc_cv);
@@ -217,17 +217,25 @@ static int
awin_ir_open(void *priv, int flag, int mode, struct proc *p)
{
struct awin_ir_softc *sc = priv;
- uint32_t ctl, rxint;
+ uint32_t ctl, rxint, cir;
ctl = __SHIFTIN(AWIN_IR_CTL_MD_CIR, AWIN_IR_CTL_MD);
IR_WRITE(sc, AWIN_IR_CTL_REG, ctl);
+ cir = __SHIFTIN(3, AWIN_IR_CIR_SCS);
+ cir |= __SHIFTIN(0, AWIN_IR_CIR_SCS2);
+ cir |= __SHIFTIN(8, AWIN_IR_CIR_NTHR);
+ cir |= __SHIFTIN(2, AWIN_IR_CIR_ITHR);
+ cir |= __SHIFTIN(99, AWIN_IR_CIR_ATHR);
+ cir |= __SHIFTIN(0, AWIN_IR_CIR_ATHC);
+ IR_WRITE(sc, AWIN_IR_CIR_REG, cir);
+
IR_WRITE(sc, AWIN_IR_RXCTL_REG, AWIN_IR_RXCTL_RPPI);
IR_WRITE(sc, AWIN_IR_RXSTA_REG, AWIN_IR_RXSTA_MASK);
- rxint = AWIN_IR_RXINT_RAI_EN;
- rxint |= __SHIFTIN(0, AWIN_IR_RXINT_RAL);
+ rxint = AWIN_IR_RXINT_RPEI_EN;
+ rxint |= __SHIFTIN(31, AWIN_IR_RXINT_RAL);
IR_WRITE(sc, AWIN_IR_RXINT_REG, rxint);
ctl |= AWIN_IR_CTL_GEN;
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.49 src/sys/arch/arm/allwinner/awin_reg.h:1.50
--- src/sys/arch/arm/allwinner/awin_reg.h:1.49 Fri Nov 14 00:31:54 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Sat Nov 15 13:40:39 2014
@@ -816,7 +816,7 @@ struct awin_mmc_idma_descriptor {
#define AWIN_IR_TXSTA_TPE __BIT(1)
#define AWIN_IR_TXSTA_TU __BIT(0)
-#define AWIN_IR_RXINT_RAL __BITS(11,8)
+#define AWIN_IR_RXINT_RAL __BITS(13,8)
#define AWIN_IR_RXINT_DRQ_EN __BIT(5)
#define AWIN_IR_RXINT_RAI_EN __BIT(4)
#define AWIN_IR_RXINT_CRCI_EN __BIT(3)
@@ -833,6 +833,8 @@ struct awin_mmc_idma_descriptor {
#define AWIN_IR_RXSTA_ROI __BIT(0)
#define AWIN_IR_CIR_SCS2 __BIT(24)
+#define AWIN_IR_CIR_ATHC __BIT(23)
+#define AWIN_IR_CIR_ATHR __BITS(22,16)
#define AWIN_IR_CIR_ITHR __BITS(15,8)
#define AWIN_IR_CIR_NTHR __BITS(7,2)
#define AWIN_IR_CIR_SCS __BITS(1,0)
@@ -1072,6 +1074,8 @@ struct awin_mmc_idma_descriptor {
#define AWIN_CLK_SRC_SEL_DE_PLL3 0
#define AWIN_CLK_SRC_SEL_DE_PLL7 1
#define AWIN_CLK_SRC_SEL_DE_PLL5 2
+#define AWIN_CLK_SRC_SEL_CIR_LOSC 0
+#define AWIN_CLK_SRC_SEL_CIR_HOSC 1
#define AWIN_CLK_DIV_RATIO_N __BITS(17,16)
#define AWIN_CLK_DIV_RATIO_M __BITS(3,0)
