Module Name: src
Committed By: jmcneill
Date: Sun Nov 23 13:39:58 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_reg.h awin_twi.c
Log Message:
Don't assume that U-Boot has enabled the TWI clock. Also, for A31, set
the "iflg-rwc" device property for gttwsi.
To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/arm/allwinner/awin_reg.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/allwinner/awin_twi.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.52 src/sys/arch/arm/allwinner/awin_reg.h:1.53
--- src/sys/arch/arm/allwinner/awin_reg.h:1.52 Sat Nov 15 20:04:07 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Sun Nov 23 13:39:58 2014
@@ -2039,6 +2039,7 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_AHB_RESET1_REG 0x02C4
#define AWIN_A31_AHB_RESET2_REG 0x02C8
#define AWIN_A31_APB1_RESET_REG 0x02D0
+#define AWIN_A31_APB2_RESET_REG 0x02D8
#define AWIN_A31_PRCM_APB0_GATING_CIR __BIT(1)
@@ -2144,6 +2145,11 @@ struct awin_mmc_idma_descriptor {
#define AWIN_A31_APB1_RESET_DIGITAL_MIC_RST __BIT(4)
#define AWIN_A31_APB1_RESET_CODEC_RST __BIT(0)
+#define AWIN_A31_APB2_RESET_TWI3_RST __BIT(3)
+#define AWIN_A31_APB2_RESET_TWI2_RST __BIT(2)
+#define AWIN_A31_APB2_RESET_TWI1_RST __BIT(1)
+#define AWIN_A31_APB2_RESET_TWI0_RST __BIT(0)
+
#define AWIN_A31_WDOG1_IRQ_EN_REG 0x00A0
#define AWIN_A31_WDOG1_IRQ_STA_REG 0x00A4
#define AWIN_A31_WDOG1_CTRL_REG 0x00B0
Index: src/sys/arch/arm/allwinner/awin_twi.c
diff -u src/sys/arch/arm/allwinner/awin_twi.c:1.4 src/sys/arch/arm/allwinner/awin_twi.c:1.5
--- src/sys/arch/arm/allwinner/awin_twi.c:1.4 Sun Oct 12 14:06:18 2014
+++ src/sys/arch/arm/allwinner/awin_twi.c Sun Nov 23 13:39:58 2014
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.4 2014/10/12 14:06:18 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.5 2014/11/23 13:39:58 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -45,6 +45,10 @@ __KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v
#include <arm/allwinner/awin_reg.h>
#include <arm/allwinner/awin_var.h>
+#define TWI_CCR_REG 0x14
+#define TWI_CCR_CLK_M __BITS(6,3)
+#define TWI_CCR_CLK_N __BITS(2,0)
+
static int awin_twi_match(device_t, cfdata_t, void *);
static void awin_twi_attach(device_t, device_t, void *);
@@ -109,12 +113,14 @@ awin_twi_attach(device_t parent, device_
struct awin_twi_softc * const asc = device_private(self);
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
+ prop_dictionary_t cfg = device_properties(self);
bus_space_handle_t bsh;
+ uint32_t ccr;
awin_twi_ports |= __BIT(loc->loc_port);
/*
- * Acquite the PIO pins needed for the TWI port.
+ * Acquire the PIO pins needed for the TWI port.
*/
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
awin_gpio_pinset_acquire(&awin_twi_pinsets_a31[loc->loc_port]);
@@ -123,12 +129,38 @@ awin_twi_attach(device_t parent, device_
}
/*
+ * Clock gating, soft reset
+ */
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_APB1_GATING_REG, AWIN_APB_GATING1_TWI0 << loc->loc_port, 0);
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A31_APB2_RESET_REG,
+ AWIN_A31_APB2_RESET_TWI0_RST << loc->loc_port, 0);
+ }
+
+ /*
* Get a bus space handle for this TWI port.
*/
bus_space_subregion(aio->aio_core_bst, aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &bsh);
/*
+ * A31 specific quirk
+ */
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ prop_dictionary_set_bool(cfg, "iflg-rwc", true);
+ }
+
+ /*
+ * Set clock rate to 100kHz. From the datasheet:
+ * For 100Khz standard speed 2Wire, CLK_N=2, CLK_M=11
+ * F0=48M/2^2=12Mhz, F1=F0/(10*(11+1)) = 0.1Mhz
+ */
+ ccr = __SHIFTIN(11, TWI_CCR_CLK_M) | __SHIFTIN(2, TWI_CCR_CLK_N);
+ bus_space_write_4(aio->aio_core_bst, bsh, TWI_CCR_REG, ccr);
+
+ /*
* Do the MI attach
*/
gttwsi_attach_subr(self, aio->aio_core_bst, bsh);
