Module Name: src Committed By: martin Date: Sun Nov 16 10:33:57 UTC 2014
Modified Files: src/sys/arch/arm/allwinner [netbsd-7]: awin_ir.c awin_reg.h src/sys/arch/evbarm/conf [netbsd-7]: BPI CUBIEBOARD Log Message: Pull up following revision(s) (requested by jmcneill in ticket #241): sys/arch/evbarm/conf/BPI: revision 1.12 sys/arch/arm/allwinner/awin_ir.c: revision 1.2 sys/arch/arm/allwinner/awin_ir.c: revision 1.3 sys/arch/arm/allwinner/awin_ir.c: revision 1.4 sys/arch/evbarm/conf/CUBIEBOARD: revision 1.35 sys/arch/arm/allwinner/awin_reg.h: revision 1.50 sys/arch/arm/allwinner/awin_reg.h: revision 1.51 Fix CIR setup. Works on A31 now. hide a debug printf add A20 IR support enable awinir, cir To generate a diff of this commit: cvs rdiff -u -r1.1.2.2 -r1.1.2.3 src/sys/arch/arm/allwinner/awin_ir.c cvs rdiff -u -r1.14.2.4 -r1.14.2.5 src/sys/arch/arm/allwinner/awin_reg.h cvs rdiff -u -r1.2.2.6 -r1.2.2.7 src/sys/arch/evbarm/conf/BPI cvs rdiff -u -r1.12.2.4 -r1.12.2.5 src/sys/arch/evbarm/conf/CUBIEBOARD Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/allwinner/awin_ir.c diff -u src/sys/arch/arm/allwinner/awin_ir.c:1.1.2.2 src/sys/arch/arm/allwinner/awin_ir.c:1.1.2.3 --- src/sys/arch/arm/allwinner/awin_ir.c:1.1.2.2 Sun Nov 9 14:42:33 2014 +++ src/sys/arch/arm/allwinner/awin_ir.c Sun Nov 16 10:33:57 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: awin_ir.c,v 1.1.2.2 2014/11/09 14:42:33 martin Exp $ */ +/* $NetBSD: awin_ir.c,v 1.1.2.3 2014/11/16 10:33:57 martin Exp $ */ /*- * Copyright (c) 2014 Jared D. McNeill <jmcne...@invisible.ca> @@ -29,7 +29,7 @@ #include "opt_ddb.h" #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: awin_ir.c,v 1.1.2.2 2014/11/09 14:42:33 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: awin_ir.c,v 1.1.2.3 2014/11/16 10:33:57 martin Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -60,6 +60,7 @@ struct awin_ir_softc { device_t sc_i2cdev; void *sc_ih; size_t sc_avail; + int sc_port; }; #define IR_READ(sc, reg) \ @@ -118,6 +119,7 @@ awin_ir_attach(device_t parent, device_t sc->sc_dev = self; sc->sc_bst = aio->aio_core_bst; + sc->sc_port = loc->loc_port; mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_IR); cv_init(&sc->sc_cv, "awinir"); bus_space_subregion(sc->sc_bst, aio->aio_core_bsh, @@ -175,16 +177,39 @@ awin_ir_init(struct awin_ir_softc *sc, s clk = bus_space_read_4(sc->sc_bst, prcm_bsh, AWIN_A31_PRCM_CIR_CLK_REG); clk &= ~AWIN_CLK_SRC_SEL; - clk |= 1; /* HOSC */ + clk |= __SHIFTIN(AWIN_CLK_SRC_SEL_CIR_HOSC, AWIN_CLK_SRC_SEL); clk &= ~AWIN_CLK_DIV_RATIO_M; - clk |= 7; /* (24MHz / 3MHz) - 1 */ + clk |= __SHIFTIN(7, AWIN_CLK_DIV_RATIO_M); clk &= ~AWIN_CLK_DIV_RATIO_N; - clk |= 0; /* 1 - 1 */ + clk |= __SHIFTIN(0, AWIN_CLK_DIV_RATIO_N); clk |= AWIN_CLK_ENABLE; bus_space_write_4(sc->sc_bst, prcm_bsh, AWIN_A31_PRCM_CIR_CLK_REG, clk); bus_space_unmap(sc->sc_bst, prcm_bsh, prcm_size); + } else { + const struct awin_gpio_pinset pinset = + { 'B', AWIN_PIO_PB_IR0_FUNC, AWIN_PIO_PB_IR0_PINS }; + uint32_t clk; + + awin_gpio_pinset_acquire(&pinset); + + awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh, + AWIN_APB0_GATING_REG, + AWIN_APB_GATING0_IR0 << sc->sc_port, + 0); + + clk = bus_space_read_4(aio->aio_core_bst, aio->aio_ccm_bsh, + AWIN_IR0_CLK_REG + (sc->sc_port * 4)); + clk &= ~AWIN_CLK_SRC_SEL; + clk |= __SHIFTIN(AWIN_CLK_SRC_SEL_OSC24M, AWIN_CLK_SRC_SEL); + clk &= ~AWIN_CLK_DIV_RATIO_M; + clk |= __SHIFTIN(7, AWIN_CLK_DIV_RATIO_M); + clk &= ~AWIN_CLK_DIV_RATIO_N; + clk |= __SHIFTIN(0, AWIN_CLK_DIV_RATIO_N); + clk |= AWIN_CLK_ENABLE; + bus_space_write_4(aio->aio_core_bst, aio->aio_ccm_bsh, + AWIN_IR0_CLK_REG + (sc->sc_port * 4), clk); } } @@ -196,14 +221,16 @@ awin_ir_intr(void *priv) sta = IR_READ(sc, AWIN_IR_RXSTA_REG); +#ifdef AWIN_IR_DEBUG printf("%s: sta = 0x%08x\n", __func__, sta); +#endif if ((sta & AWIN_IR_RXSTA_MASK) == 0) return 0; IR_WRITE(sc, AWIN_IR_RXSTA_REG, sta & AWIN_IR_RXSTA_MASK); - if (sta & AWIN_IR_RXSTA_RA) { + if (sta & AWIN_IR_RXSTA_RPE) { mutex_enter(&sc->sc_lock); sc->sc_avail = __SHIFTOUT(sta, AWIN_IR_RXSTA_RAC); cv_broadcast(&sc->sc_cv); @@ -217,17 +244,27 @@ static int awin_ir_open(void *priv, int flag, int mode, struct proc *p) { struct awin_ir_softc *sc = priv; - uint32_t ctl, rxint; + uint32_t ctl, rxint, cir; ctl = __SHIFTIN(AWIN_IR_CTL_MD_CIR, AWIN_IR_CTL_MD); IR_WRITE(sc, AWIN_IR_CTL_REG, ctl); + cir = __SHIFTIN(3, AWIN_IR_CIR_SCS); + cir |= __SHIFTIN(0, AWIN_IR_CIR_SCS2); + cir |= __SHIFTIN(8, AWIN_IR_CIR_NTHR); + cir |= __SHIFTIN(2, AWIN_IR_CIR_ITHR); + if (awin_chip_id() == AWIN_CHIP_ID_A31) { + cir |= __SHIFTIN(99, AWIN_IR_CIR_ATHR); + cir |= __SHIFTIN(0, AWIN_IR_CIR_ATHC); + } + IR_WRITE(sc, AWIN_IR_CIR_REG, cir); + IR_WRITE(sc, AWIN_IR_RXCTL_REG, AWIN_IR_RXCTL_RPPI); IR_WRITE(sc, AWIN_IR_RXSTA_REG, AWIN_IR_RXSTA_MASK); - rxint = AWIN_IR_RXINT_RAI_EN; - rxint |= __SHIFTIN(0, AWIN_IR_RXINT_RAL); + rxint = AWIN_IR_RXINT_RPEI_EN; + rxint |= __SHIFTIN(31, AWIN_IR_RXINT_RAL); IR_WRITE(sc, AWIN_IR_RXINT_REG, rxint); ctl |= AWIN_IR_CTL_GEN; Index: src/sys/arch/arm/allwinner/awin_reg.h diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.14.2.4 src/sys/arch/arm/allwinner/awin_reg.h:1.14.2.5 --- src/sys/arch/arm/allwinner/awin_reg.h:1.14.2.4 Fri Nov 14 13:37:39 2014 +++ src/sys/arch/arm/allwinner/awin_reg.h Sun Nov 16 10:33:57 2014 @@ -816,7 +816,7 @@ struct awin_mmc_idma_descriptor { #define AWIN_IR_TXSTA_TPE __BIT(1) #define AWIN_IR_TXSTA_TU __BIT(0) -#define AWIN_IR_RXINT_RAL __BITS(11,8) +#define AWIN_IR_RXINT_RAL __BITS(13,8) #define AWIN_IR_RXINT_DRQ_EN __BIT(5) #define AWIN_IR_RXINT_RAI_EN __BIT(4) #define AWIN_IR_RXINT_CRCI_EN __BIT(3) @@ -833,6 +833,8 @@ struct awin_mmc_idma_descriptor { #define AWIN_IR_RXSTA_ROI __BIT(0) #define AWIN_IR_CIR_SCS2 __BIT(24) +#define AWIN_IR_CIR_ATHC __BIT(23) +#define AWIN_IR_CIR_ATHR __BITS(22,16) #define AWIN_IR_CIR_ITHR __BITS(15,8) #define AWIN_IR_CIR_NTHR __BITS(7,2) #define AWIN_IR_CIR_SCS __BITS(1,0) @@ -905,7 +907,7 @@ struct awin_mmc_idma_descriptor { #define AWIN_SPI0_CLK_REG 0x00A0 #define AWIN_SPI1_CLK_REG 0x00A4 #define AWIN_SPI2_CLK_REG 0x00A8 -#define AWIN_IR0_CLK_REG 0x00B9 +#define AWIN_IR0_CLK_REG 0x00B0 #define AWIN_IR1_CLK_REG 0x00B4 #define AWIN_IIS_CLK_REG 0x00B8 #define AWIN_AC97_CLK_REG 0x00BC @@ -1072,6 +1074,8 @@ struct awin_mmc_idma_descriptor { #define AWIN_CLK_SRC_SEL_DE_PLL3 0 #define AWIN_CLK_SRC_SEL_DE_PLL7 1 #define AWIN_CLK_SRC_SEL_DE_PLL5 2 +#define AWIN_CLK_SRC_SEL_CIR_LOSC 0 +#define AWIN_CLK_SRC_SEL_CIR_HOSC 1 #define AWIN_CLK_DIV_RATIO_N __BITS(17,16) #define AWIN_CLK_DIV_RATIO_M __BITS(3,0) Index: src/sys/arch/evbarm/conf/BPI diff -u src/sys/arch/evbarm/conf/BPI:1.2.2.6 src/sys/arch/evbarm/conf/BPI:1.2.2.7 --- src/sys/arch/evbarm/conf/BPI:1.2.2.6 Fri Nov 14 13:37:39 2014 +++ src/sys/arch/evbarm/conf/BPI Sun Nov 16 10:33:57 2014 @@ -1,5 +1,5 @@ # -# $NetBSD: BPI,v 1.2.2.6 2014/11/14 13:37:39 martin Exp $ +# $NetBSD: BPI,v 1.2.2.7 2014/11/16 10:33:57 martin Exp $ # # BPI -- Banana Pi - an Allwinner A20 Eval Board Kernel # @@ -236,6 +236,10 @@ iic* at awiniic? com0 at awinio? port 0 # UART0 (console) options CONADDR=0x01c28000, CONSPEED=115200 +# Consumer IR +awinir0 at awinio? +cir0 at awinir0 + # Operating System Timer (A10) awintmr0 at awinio? Index: src/sys/arch/evbarm/conf/CUBIEBOARD diff -u src/sys/arch/evbarm/conf/CUBIEBOARD:1.12.2.4 src/sys/arch/evbarm/conf/CUBIEBOARD:1.12.2.5 --- src/sys/arch/evbarm/conf/CUBIEBOARD:1.12.2.4 Fri Nov 14 13:37:39 2014 +++ src/sys/arch/evbarm/conf/CUBIEBOARD Sun Nov 16 10:33:57 2014 @@ -1,5 +1,5 @@ # -# $NetBSD: CUBIEBOARD,v 1.12.2.4 2014/11/14 13:37:39 martin Exp $ +# $NetBSD: CUBIEBOARD,v 1.12.2.5 2014/11/16 10:33:57 martin Exp $ # # CUBIEBOARD -- Allwinner A10/A20 Eval Board Kernel # @@ -234,6 +234,10 @@ iic* at awiniic? com0 at awinio? port 0 # UART0 (console) options CONADDR=0x01c28000, CONSPEED=115200 +# Consumer IR +awinir0 at awinio? +cir0 at awinir0 + # Operating System Timer (A10) awintmr0 at awinio?