Module Name: src
Committed By: macallan
Date: Sat Dec 6 14:33:34 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: ingenic_regs.h
Log Message:
moar registers!
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.1 src/sys/arch/mips/ingenic/ingenic_regs.h:1.2
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.1 Sat Nov 22 15:17:01 2014
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Sat Dec 6 14:33:34 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.1 2014/11/22 15:17:01 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.2 2014/12/06 14:33:34 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -46,7 +46,7 @@
#define JZ_WDOG_TCSR 0x1000200c
#define TCSR_PCK_EN 0x01 /* PCLK */
#define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */
- #define TCSR_EXT_EN 0x04 /* EXTCLK - 12MHz? */
+ #define TCSR_EXT_EN 0x04 /* EXTCLK - 48MHz */
#define TCSR_PRESCALE_M 0x38
#define TCSR_DIV_1 0x00
#define TCSR_DIV_4 0x08
@@ -63,11 +63,33 @@
#define TESR_TCST2 0x0004 /* enable counter 2 */
#define TESR_TCST3 0x0008 /* enable counter 3 */
#define TESR_TCST4 0x0010 /* enable counter 4 */
- #define TESR_TCST5 0x0014 /* enable counter 5 */
- #define TESR_TCST6 0x0018 /* enable counter 6 */
- #define TESR_TCST7 0x001c /* enable counter 7 */
+ #define TESR_TCST5 0x0020 /* enable counter 5 */
+ #define TESR_TCST6 0x0040 /* enable counter 6 */
+ #define TESR_TCST7 0x0080 /* enable counter 7 */
#define TESR_OST 0x8000 /* enable OST */
#define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */
+#define JZ_TC_TFR 0x10002020
+ #define TFR_FFLAG0 0x00000001 /* channel 0 */
+ #define TFR_FFLAG1 0x00000002 /* channel 1 */
+ #define TFR_FFLAG2 0x00000004 /* channel 2 */
+ #define TFR_FFLAG3 0x00000008 /* channel 3 */
+ #define TFR_FFLAG4 0x00000010 /* channel 4 */
+ #define TFR_FFLAG5 0x00000020 /* channel 5 */
+ #define TFR_FFLAG6 0x00000040 /* channel 6 */
+ #define TFR_FFLAG7 0x00000080 /* channel 7 */
+ #define TFR_OSTFLAG 0x00008000 /* OS timer */
+#define JZ_TC_TFSR 0x10002024 /* timer flag set */
+#define JZ_TC_TFCR 0x10002028 /* timer flag clear */
+#define JZ_TC_TMR 0x10002030 /* timer flag mask */
+#define JZ_TC_TMSR 0x10002034 /* timer flag mask set */
+#define JZ_TC_TMCR 0x10002038 /* timer flag mask clear*/
+
+#define JZ_TC_TDFR(n) (0x10002040 + (n * 0x10)) /* FULL compare */
+#define JZ_TC_TDHR(n) (0x10002044 + (n * 0x10)) /* HALF compare */
+#define JZ_TC_TCNT(n) (0x10002048 + (n * 0x10)) /* count */
+
+#define JZ_TC_TCSR(n) (0x1000204c + (n * 0x10))
+/* same bits as in JZ_WDOG_TCSR */
/* operating system timer */
#define JZ_OST_DATA 0x100020e0 /* compare */
@@ -102,4 +124,62 @@ readreg(uint32_t reg)
return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg);
}
-#endif /* INGENIC_REGS_H */
\ No newline at end of file
+/* extra CP0 registers */
+static inline uint32_t
+MFC0(uint32_t r, uint32_t s)
+{
+ uint32_t ret = 0x12345678;
+
+ __asm volatile("mfc0 %0, $%1, %2; nop;" : "=r"(ret) : "i"(r), "i"(s));
+ return ret;
+}
+
+#define MTC0(v, r, s) __asm volatile("mtc0 %0, $%1, %2; nop;" :: "r"(v), "i"(r), "i"(s))
+
+#define CP0_CORE_CTRL 12 /* select 2 */
+ #define CC_SW_RST0 1 /* reset core 0 */
+ #define CC_SW_RST1 2 /* reset core 1 */
+ #define CC_RPC0 0x100 /* dedicater reset entry core 0 */
+ #define CC_RPC1 0x200 /* -- || -- core 1 */
+ #define CC_SLEEP0M 0x10000 /* mask sleep core 0 */
+ #define CC_SLEEP1M 0x20000 /* mask sleep core 1 */
+
+/* cores status, 12 select 3 */
+#define CS_MIRQ0_P 0x00001 /* mailbox IRQ for 0 pending */
+#define CS_MIRQ1_P 0x00002 /* || core 1 */
+#define CS_IRQ0_P 0x00100 /* peripheral IRQ for core 0 */
+#define CS_IRQ1_P 0x00200 /* || core 1 */
+#define CS_SLEEP0 0x10000 /* core 0 sleeping */
+#define CS_SLEEP1 0x20000 /* core 1 sleeping */
+
+/* cores reset entry & IRQ masks - 12 select 4 */
+#define REIM_MIRQ0_M 0x00001 /* allow mailbox IRQ for core 0 */
+#define REIM_MIRQ1_M 0x00002 /* allow mailbox IRQ for core 1 */
+#define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */
+#define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */
+#define REIM_ENTRY_M 0xffff0000 /* reset exception entry if RPCn=1 */
+
+#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */
+
+/* interrupt controller */
+#define JZ_ICSR0 0x10001000 /* raw IRQ line status */
+#define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */
+#define JZ_ICMSR0 0x10001008 /* sets bits in mask register */
+#define JZ_ICMCR0 0x1000100c /* clears bits in maks register */
+#define JZ_ICPR0 0x10001010 /* line status after masking */
+
+#define JZ_ICSR1 0x10001020 /* raw IRQ line status */
+#define JZ_ICMR1 0x10001024 /* IRQ mask, 1 masks IRQ */
+#define JZ_ICMSR1 0x10001028 /* sets bits in mask register */
+#define JZ_ICMCR1 0x1000102c /* clears bits in maks register */
+#define JZ_ICPR1 0x10001030 /* line status after masking */
+
+#define JZ_DSR0 0x10001034 /* source for PDMA */
+#define JZ_DMR0 0x10001038 /* mask for PDMA */
+#define JZ_DPR0 0x1000103c /* pending for PDMA */
+
+#define JZ_DSR1 0x10001040 /* source for PDMA */
+#define JZ_DMR1 0x10001044 /* mask for PDMA */
+#define JZ_DPR1 0x10001048 /* pending for PDMA */
+
+#endif /* INGENIC_REGS_H */
