Module Name: src
Committed By: macallan
Date: Tue Dec 23 18:48:52 UTC 2014
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_dwctwo.c ingenic_regs.h
Log Message:
appease nick
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/apbus.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_dwctwo.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/ingenic/apbus.c
diff -u src/sys/arch/mips/ingenic/apbus.c:1.3 src/sys/arch/mips/ingenic/apbus.c:1.4
--- src/sys/arch/mips/ingenic/apbus.c:1.3 Tue Dec 23 16:16:03 2014
+++ src/sys/arch/mips/ingenic/apbus.c Tue Dec 23 18:48:52 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: apbus.c,v 1.3 2014/12/23 16:16:03 macallan Exp $ */
+/* $NetBSD: apbus.c,v 1.4 2014/12/23 18:48:52 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.3 2014/12/23 16:16:03 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.4 2014/12/23 18:48:52 macallan Exp $");
#include "locators.h"
#define _MIPS_BUS_DMA_PRIVATE
@@ -117,7 +117,7 @@ apbus_attach(device_t parent, device_t s
/* wake up the USB part */
reg = readreg(JZ_OPCR);
- reg |= SPENDN0 | SPENDN1;
+ reg |= OPCR_SPENDN0 | OPCR_SPENDN1;
writereg(JZ_OPCR, reg);
#ifdef INGENIC_DEBUG
Index: src/sys/arch/mips/ingenic/ingenic_dwctwo.c
diff -u src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.2 src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.3
--- src/sys/arch/mips/ingenic/ingenic_dwctwo.c:1.2 Tue Dec 23 15:13:30 2014
+++ src/sys/arch/mips/ingenic/ingenic_dwctwo.c Tue Dec 23 18:48:52 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_dwctwo.c,v 1.2 2014/12/23 15:13:30 macallan Exp $ */
+/* $NetBSD: ingenic_dwctwo.c,v 1.3 2014/12/23 18:48:52 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ingenic_dwctwo.c,v 1.2 2014/12/23 15:13:30 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ingenic_dwctwo.c,v 1.3 2014/12/23 18:48:52 macallan Exp $");
/*
* adapted from bcm2835_dwctwo.c
@@ -136,12 +136,15 @@ ingenic_dwc2_attach(device_t parent, dev
aprint_normal(": USB controller\n");
reg = readreg(JZ_USBPCR);
- reg |= VBUSVLDEXTSEL;
- reg |= VBUSVLDEXT;
- reg |= USB_MODE;
- reg |= COMMONONN;
- reg &= ~OTG_DISABLE;
+ reg |= PCR_VBUSVLDEXTSEL;
+ reg |= PCR_VBUSVLDEXT;
+ reg |= PCR_USB_MODE;
+ reg |= PCR_COMMONONN;
+ reg &= ~PCR_OTG_DISABLE;
writereg(JZ_USBPCR, reg);
+#ifdef INGENIC_DEBUG
+ printf("JZ_USBPCR %08x\n", reg);
+#endif
reg = readreg(JZ_USBPCR1);
reg |= PCR_SYNOPSYS;
@@ -150,6 +153,9 @@ ingenic_dwc2_attach(device_t parent, dev
reg |= PCR_CLK_48;
reg |= PCR_WORD_I_F0;
writereg(JZ_USBPCR1, reg);
+#ifdef INGENIC_DEBUG
+ printf("JZ_USBPCR1 %08x\n", reg);
+#endif
delay(10000);
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u src/sys/arch/mips/ingenic/ingenic_regs.h:1.4 src/sys/arch/mips/ingenic/ingenic_regs.h:1.5
--- src/sys/arch/mips/ingenic/ingenic_regs.h:1.4 Tue Dec 23 16:15:05 2014
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Tue Dec 23 18:48:52 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.4 2014/12/23 16:15:05 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.5 2014/12/23 18:48:52 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -164,41 +164,41 @@ MFC0(uint32_t r, uint32_t s)
/* power management */
#define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */
#define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */
- #define IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */
- #define GPU_CLK_STOP 0x40000000
- #define L2CM_M 0x0c000000
- #define L2CM_ON 0x00000000 /* L2 stays on in sleep */
- #define L2CM_RET 0x04000000 /* L2 retention mode in sleep */
- #define L2CM_OFF 0x08000000 /* L2 powers down in sleep */
- #define SPENDN0 0x00000080 /* OTG port forced down */
- #define SPENDN1 0x00000040 /* UHC port forced down */
- #define BUS_MODE 0x00000020 /* 1 - bursts */
- #define O1SE 0x00000010 /* EXTCLK on in sleep */
- #define PD 0x00000008 /* P0 down in sleep */
- #define ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */
- #define CPU_MODE 0x00000002 /* 1 access 'accelerated' */
- #define OSE 0x00000001 /* disable EXTCLK */
+ #define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */
+ #define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */
+ #define OPCR_L2CM_M 0x0c000000
+ #define OPCR_L2CM_ON 0x00000000 /* L2 stays on in sleep */
+ #define OPCR_L2CM_RET 0x04000000 /* L2 retention mode in sleep */
+ #define OPCR_L2CM_OFF 0x08000000 /* L2 powers down in sleep */
+ #define OPCR_SPENDN0 0x00000080 /* OTG port forced down */
+ #define OPCR_SPENDN1 0x00000040 /* UHC port forced down */
+ #define OPCR_BUS_MODE 0x00000020 /* 1 - bursts */
+ #define OPCR_O1SE 0x00000010 /* EXTCLK on in sleep */
+ #define OPCR_PD 0x00000008 /* P0 down in sleep */
+ #define OPCR_ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */
+ #define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */
+ #define OPCR_OSE 0x00000001 /* disable EXTCLK */
#define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */
#define JZ_USBPCR 0x1000003c
- #define USB_MODE 0x80000000 /* 1 - otg */
- #define AVLD_REG 0x40000000
- #define IDPULLUP_MASK 0x30000000
- #define INCR_MASK 0x08000000
- #define TCRISETUNE 0x04000000
- #define COMMONONN 0x02000000
- #define VBUSVLDEXT 0x01000000
- #define VBUSVLDEXTSEL 0x00800000
- #define POR 0x00400000
- #define SIDDQ 0x00200000
- #define OTG_DISABLE 0x00100000
- #define COMPDISTUNE_M 0x000e0000
- #define OTGTUNE 0x0001c000
- #define SQRXTUNE 0x00003800
- #define TXFSLSTUNE 0x00000780
- #define TXPREEMPHTUNE 0x00000040
- #define TXHSXVTUNE 0x00000030
- #define TXVREFTUNE 0x0000000f
-
+ #define PCR_USB_MODE 0x80000000 /* 1 - otg */
+ #define PCR_AVLD_REG 0x40000000
+ #define PCR_IDPULLUP_MASK 0x30000000
+ #define PCR_INCR_MASK 0x08000000
+ #define PCR_TCRISETUNE 0x04000000
+ #define PCR_COMMONONN 0x02000000
+ #define PCR_VBUSVLDEXT 0x01000000
+ #define PCR_VBUSVLDEXTSEL 0x00800000
+ #define PCR_POR 0x00400000
+ #define PCR_SIDDQ 0x00200000
+ #define PCR_OTG_DISABLE 0x00100000
+ #define PCR_COMPDISTN_M 0x000e0000
+ #define PCR_OTGTUNE 0x0001c000
+ #define PCR_SQRXTUNE 0x00003800
+ #define PCR_TXFSLSTUNE 0x00000780
+ #define PCR_TXPREEMPHTUNE 0x00000040
+ #define PCR_TXHSXVTUNE 0x00000030
+ #define PCR_TXVREFTUNE 0x0000000f
+
#define JZ_USBPCR1 0x10000048
#define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */
#define PCR_REFCLK_CORE 0x0c000000
