Module Name: src
Committed By: macallan
Date: Fri Dec 26 17:43:32 UTC 2014
Modified Files:
src/sys/arch/evbmips/ingenic: clock.c
Log Message:
use #ifdef USE_OST to switch between OS Timer and timer 5
always enable interrupts, not just with INGENIC_CLOCK_DEBUG
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbmips/ingenic/clock.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u src/sys/arch/evbmips/ingenic/clock.c:1.3 src/sys/arch/evbmips/ingenic/clock.c:1.4
--- src/sys/arch/evbmips/ingenic/clock.c:1.3 Tue Dec 23 15:07:33 2014
+++ src/sys/arch/evbmips/ingenic/clock.c Fri Dec 26 17:43:32 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: clock.c,v 1.3 2014/12/23 15:07:33 macallan Exp $ */
+/* $NetBSD: clock.c,v 1.4 2014/12/26 17:43:32 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.3 2014/12/23 15:07:33 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.4 2014/12/26 17:43:32 macallan Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -75,8 +75,8 @@ cpu_initclocks(void)
/* start the timer interrupt */
cnt = readreg(JZ_OST_CNT_LO);
ci->ci_next_cp0_clk_intr = cnt + ci->ci_cycles_per_hz;
- writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
writereg(JZ_TC_TFCR, TFR_OSTFLAG);
+ writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
/*
* XXX
* We can use OST or one of the regular timers to generate the 100hz
@@ -93,7 +93,7 @@ cpu_initclocks(void)
* For now, use OST and hope we'll figure out how to make it fire on
* INT2.
*/
-#if 1
+#ifdef USE_OST
writereg(JZ_TC_TMCR, TFR_OSTFLAG);
#else
writereg(JZ_TC_TECR, TESR_TCST5); /* disable timer 5 */
@@ -108,8 +108,9 @@ cpu_initclocks(void)
#ifdef INGENIC_CLOCK_DEBUG
printf("INTC %08x %08x\n", readreg(JZ_ICSR0), readreg(JZ_ICSR1));
- writereg(JZ_ICMCR0, 0x0c000000); /* TCU2, OST */
+ printf("ICMR0 %08x\n", readreg(JZ_ICMR0));
#endif
+ writereg(JZ_ICMCR0, 0x0c000000); /* TCU2, OST */
spl0();
#ifdef INGENIC_CLOCK_DEBUG
printf("TFR: %08x\n", readreg(JZ_TC_TFR));
@@ -191,8 +192,9 @@ void
ingenic_clockintr(uint32_t id)
{
struct cpu_info * const ci = curcpu();
+#ifdef USE_OST
uint32_t new_cnt;
-
+#endif
ci->ci_ev_count_compare.ev_count++;
/* clear flags */
@@ -200,6 +202,7 @@ ingenic_clockintr(uint32_t id)
KASSERT((ci->ci_cycles_per_hz & ~(0xffffffff)) == 0);
ci->ci_next_cp0_clk_intr += (uint32_t)(ci->ci_cycles_per_hz & 0xffffffff);
+#ifdef USE_OST
writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
/* Check for lost clock interrupts */
@@ -215,6 +218,10 @@ ingenic_clockintr(uint32_t id)
writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
curcpu()->ci_ev_count_compare_missed.ev_count++;
}
+ writereg(JZ_TC_TFCR, TFR_OSTFLAG);
+#else
+ writereg(JZ_TC_TFCR, TFR_FFLAG5);
+#endif
#ifdef INGENIC_CLOCK_DEBUG
cnt++;
