Module Name: src
Committed By: jmcneill
Date: Sat Feb 28 18:50:57 UTC 2015
Modified Files:
src/sys/arch/arm/amlogic: amlogic_board.c amlogic_crureg.h
amlogic_dwctwo.c
Log Message:
more usb phy / clk init
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/amlogic/amlogic_board.c \
src/sys/arch/arm/amlogic/amlogic_crureg.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/amlogic/amlogic_dwctwo.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/amlogic/amlogic_board.c
diff -u src/sys/arch/arm/amlogic/amlogic_board.c:1.3 src/sys/arch/arm/amlogic/amlogic_board.c:1.4
--- src/sys/arch/arm/amlogic/amlogic_board.c:1.3 Sat Feb 28 15:20:43 2015
+++ src/sys/arch/arm/amlogic/amlogic_board.c Sat Feb 28 18:50:57 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_board.c,v 1.3 2015/02/28 15:20:43 jmcneill Exp $ */
+/* $NetBSD: amlogic_board.c,v 1.4 2015/02/28 18:50:57 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "opt_amlogic.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.3 2015/02/28 15:20:43 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.4 2015/02/28 18:50:57 jmcneill Exp $");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
@@ -59,7 +59,7 @@ struct arm32_bus_dma_tag amlogic_dma_tag
AMLOGIC_CBUS_OFFSET + (x))
#define CBUS_WRITE(x, v) \
bus_space_write_4(&amlogic_bs_tag, amlogic_core_bsh, \
- AMLOGIC_CBUS_OFFSET + (x), (v))
+ AMLOGIC_CBUS_OFFSET + (x), (v))
void
amlogic_bootstrap(void)
@@ -157,15 +157,40 @@ amlogic_get_rate_a9periph(void)
return amlogic_get_rate_a9() / div;
}
+static void
+amlogic_usbphy_clkgate_enable(int port)
+{
+ switch (port) {
+ case 0:
+ CBUS_WRITE(EE_CLK_GATING1_REG,
+ CBUS_READ(EE_CLK_GATING1_REG) |
+ EE_CLK_GATING1_USB_GENERAL |
+ EE_CLK_GATING1_USB0);
+ CBUS_WRITE(EE_CLK_GATING2_REG,
+ CBUS_READ(EE_CLK_GATING2_REG) |
+ EE_CLK_GATING2_USB0_TO_DDR);
+ break;
+ case 1:
+ CBUS_WRITE(EE_CLK_GATING1_REG,
+ CBUS_READ(EE_CLK_GATING1_REG) |
+ EE_CLK_GATING1_USB_GENERAL |
+ EE_CLK_GATING1_USB1);
+ CBUS_WRITE(EE_CLK_GATING2_REG,
+ CBUS_READ(EE_CLK_GATING2_REG) |
+ EE_CLK_GATING2_USB1_TO_DDR);
+ break;
+ }
+}
+
void
amlogic_usbphy_init(int port)
{
bus_space_tag_t bst = &amlogic_bs_tag;
bus_space_handle_t bsh = amlogic_core_bsh;
- bus_size_t ctrl_reg, cfg_reg, gpioao_reg;
- uint32_t ctrl, cfg, gpioao;
+ bus_size_t ctrl_reg, cfg_reg, adp_bc_reg, gpioao_reg;
+ uint32_t ctrl, cfg, adp_bc, gpioao;
u_int pin, pol;
- bool gpio_power = false, gpio_reset = false;
+ bool gpio_power = false, gpio_reset = false, aca_enable = false;
gpioao_reg = AMLOGIC_GPIOAO_OFFSET;
@@ -173,6 +198,7 @@ amlogic_usbphy_init(int port)
case 0:
cfg_reg = PREI_USB_PHY_A_CFG_REG;
ctrl_reg = PREI_USB_PHY_A_CTRL_REG;
+ adp_bc_reg = PREI_USB_PHY_A_ADP_BC_REG;
pin = 5;
pol = 1;
gpio_power = true;
@@ -180,17 +206,26 @@ amlogic_usbphy_init(int port)
case 1:
cfg_reg = PREI_USB_PHY_B_CFG_REG;
ctrl_reg = PREI_USB_PHY_B_CTRL_REG;
+ adp_bc_reg = PREI_USB_PHY_B_ADP_BC_REG;
pin = 4;
pol = 0;
gpio_reset = true;
+ aca_enable = true;
break;
default:
return;
}
+ if (port == 0) {
+ CBUS_WRITE(RESET1_REG, RESET1_USB);
+ }
+
+ amlogic_usbphy_clkgate_enable(port);
+
if (gpio_power) {
gpioao = bus_space_read_4(bst, bsh, gpioao_reg);
gpioao |= __BIT(pin); /* OEN */
+ bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
if (pol) {
gpioao |= __BIT(pin + 16); /* OUT */
} else {
@@ -199,8 +234,6 @@ amlogic_usbphy_init(int port)
bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
}
- CBUS_WRITE(RESET1_REG, RESET1_USB);
-
delay(1000);
cfg = CBUS_READ(cfg_reg);
@@ -229,15 +262,40 @@ amlogic_usbphy_init(int port)
if ((ctrl & PREI_USB_PHY_CTRL_CLK_DET) == 0)
printf("WARNING: USB PHY port %d clock not detected\n", port);
+ if (aca_enable) {
+ adp_bc = CBUS_READ(adp_bc_reg);
+ adp_bc |= PREI_USB_PHY_ADP_BC_ACA_ENABLE;
+ CBUS_WRITE(adp_bc_reg, adp_bc);
+
+ delay(1000);
+
+ adp_bc = CBUS_READ(adp_bc_reg);
+ if (adp_bc & PREI_USB_PHY_ADP_BC_ACA_FLOATING)
+ printf("WARNING: USB PHY port %d failed to enable "
+ "ACA detection\n", port);
+ }
+
if (gpio_reset) {
/* Reset */
gpioao = bus_space_read_4(bst, bsh, gpioao_reg);
gpioao |= __BIT(pin); /* OEN */
+ bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
if (pol) {
gpioao |= __BIT(pin + 16); /* OUT */
} else {
gpioao &= ~__BIT(pin + 16); /* OUT */
}
bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
+
+ delay(1000);
+
+ if (pol) {
+ gpioao &= ~__BIT(pin + 16); /* OUT */
+ } else {
+ gpioao |= __BIT(pin + 16); /* OUT */
+ }
+ bus_space_write_4(bst, bsh, gpioao_reg, gpioao);
+
+ delay(60000);
}
}
Index: src/sys/arch/arm/amlogic/amlogic_crureg.h
diff -u src/sys/arch/arm/amlogic/amlogic_crureg.h:1.3 src/sys/arch/arm/amlogic/amlogic_crureg.h:1.4
--- src/sys/arch/arm/amlogic/amlogic_crureg.h:1.3 Sat Feb 28 15:20:43 2015
+++ src/sys/arch/arm/amlogic/amlogic_crureg.h Sat Feb 28 18:50:57 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_crureg.h,v 1.3 2015/02/28 15:20:43 jmcneill Exp $ */
+/* $NetBSD: amlogic_crureg.h,v 1.4 2015/02/28 18:50:57 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -31,6 +31,17 @@
#define CBUS_REG(n) ((n) << 2)
+#define EE_CLK_GATING0_REG CBUS_REG(0x1050)
+#define EE_CLK_GATING1_REG CBUS_REG(0x1051)
+#define EE_CLK_GATING2_REG CBUS_REG(0x1052)
+#define EE_CLK_GATING3_REG CBUS_REG(0x1054)
+
+#define EE_CLK_GATING1_USB_GENERAL __BIT(26)
+#define EE_CLK_GATING1_USB1 __BIT(22)
+#define EE_CLK_GATING1_USB0 __BIT(21)
+#define EE_CLK_GATING2_USB0_TO_DDR __BIT(9)
+#define EE_CLK_GATING2_USB1_TO_DDR __BIT(8)
+
#define HHI_SYS_CPU_CLK_CNTL1_REG CBUS_REG(0x1057)
#define HHI_SYS_CPU_CLK_CNTL1_SDIV __BITS(29,20)
#define HHI_SYS_CPU_CLK_CNTL1_PERIPH_CLK_MUX __BITS(8,6)
@@ -53,8 +64,10 @@
#define PREI_USB_PHY_A_CFG_REG CBUS_REG(0x2200)
#define PREI_USB_PHY_A_CTRL_REG CBUS_REG(0x2201)
+#define PREI_USB_PHY_A_ADP_BC_REG CBUS_REG(0x2203)
#define PREI_USB_PHY_B_CFG_REG CBUS_REG(0x2208)
#define PREI_USB_PHY_B_CTRL_REG CBUS_REG(0x2209)
+#define PREI_USB_PHY_B_ADP_BC_REG CBUS_REG(0x220b)
#define PREI_USB_PHY_CFG_CLK_32K_ALT_SEL __BIT(15)
@@ -64,6 +77,9 @@
#define PREI_USB_PHY_CTRL_POR __BIT(15)
#define PREI_USB_PHY_CTRL_CLK_DET __BIT(8)
+#define PREI_USB_PHY_ADP_BC_ACA_FLOATING __BIT(26)
+#define PREI_USB_PHY_ADP_BC_ACA_ENABLE __BIT(16)
+
#define WATCHDOG_TC_REG CBUS_REG(0x2640)
#define WATCHDOG_TC_CPUS __BITS(27,24)
#define WATCHDOG_TC_ENABLE __BIT(19)
Index: src/sys/arch/arm/amlogic/amlogic_dwctwo.c
diff -u src/sys/arch/arm/amlogic/amlogic_dwctwo.c:1.1 src/sys/arch/arm/amlogic/amlogic_dwctwo.c:1.2
--- src/sys/arch/arm/amlogic/amlogic_dwctwo.c:1.1 Sat Feb 28 15:20:43 2015
+++ src/sys/arch/arm/amlogic/amlogic_dwctwo.c Sat Feb 28 18:50:57 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: amlogic_dwctwo.c,v 1.1 2015/02/28 15:20:43 jmcneill Exp $ */
+/* $NetBSD: amlogic_dwctwo.c,v 1.2 2015/02/28 18:50:57 jmcneill Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amlogic_dwctwo.c,v 1.1 2015/02/28 15:20:43 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amlogic_dwctwo.c,v 1.2 2015/02/28 18:50:57 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -62,28 +62,28 @@ struct amlogic_dwctwo_softc {
static struct dwc2_core_params amlogic_dwctwo_params = {
.otg_cap = 2, /* 0 - HNP/SRP capable */
.otg_ver = 1, /* 1 - 2.0 */
- .dma_enable = 1, /* 1 - DMA (default, if available) */
- .dma_desc_enable = 1, /* 1 - Descriptor DMA (default, if available) */
- .speed = 0, /* 0 - High Speed */
+ .dma_enable = -1, /* 1 - DMA (default, if available) */
+ .dma_desc_enable = 0, /* 1 - Descriptor DMA (default, if available) */
+ .speed = -1, /* 0 - High Speed */
.enable_dynamic_fifo = 1, /* 1 - Allow dynamic FIFO sizing (default, if available) */
- .en_multiple_tx_fifo = 1, /* Specifies whether dedicated per-endpoint transmit FIFOs are enabled */
- .host_rx_fifo_size = 520, /* 520 DWORDs */
- .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
- .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
- .max_transfer_size = 65535,/* 2047 to 65,535 */
- .max_packet_count = 511, /* 15 to 511 */
- .host_channels = 8, /* 1 to 16 */
+ .en_multiple_tx_fifo = -1, /* Specifies whether dedicated per-endpoint transmit FIFOs are enabled */
+ .host_rx_fifo_size = 512, /* 512 DWORDs */
+ .host_nperio_tx_fifo_size = 500, /* 500 DWORDs */
+ .host_perio_tx_fifo_size = -1, /* 256 DWORDs */
+ .max_transfer_size = -1, /* 2047 to 65,535 */
+ .max_packet_count = -1, /* 15 to 511 */
+ .host_channels = -1, /* 1 to 16 */
.phy_type = 1, /* 1- UTMI+ Phy */
- .phy_utmi_width = 8, /* 8 bits */
- .phy_ulpi_ddr = 0, /* Single */
- .phy_ulpi_ext_vbus = 0,
- .i2c_enable = 0,
- .ulpi_fs_ls = 0, /* 0 - No (default) */
- .host_support_fs_ls_low_power = 0, /* 0 - Don't support low power mode (default) */
- .host_ls_low_power_phy_clk = 0, /* 1 - 48 MHz default when phy_type is UTMI+ or ULPI*/
- .ts_dline = 0, /* 0 - No (default) */
- .reload_ctl = 0, /* 0 - No (default for core < 2.92a) */
- .ahbcfg = 0x7, /* INCR16 */
+ .phy_utmi_width = -1, /* 8 bits */
+ .phy_ulpi_ddr = -1, /* Single */
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1, /* 0 - No (default) */
+ .host_support_fs_ls_low_power = -1, /* 0 - Don't support low power mode (default) */
+ .host_ls_low_power_phy_clk = -1, /* 1 - 48 MHz default when phy_type is UTMI+ or ULPI*/
+ .ts_dline = -1, /* 0 - No (default) */
+ .reload_ctl = -1, /* 0 - No (default for core < 2.92a) */
+ .ahbcfg = 0x3, /* INCR4 */
.uframe_sched = 1, /* True to enable microframe scheduler */
};
