Module Name: src Committed By: jmcneill Date: Sat Mar 7 21:32:47 UTC 2015
Modified Files: src/sys/arch/arm/amlogic: amlogic_board.c amlogic_crureg.h amlogic_reg.h amlogic_var.h Log Message: clk helpers for sdhc and rng To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/amlogic/amlogic_board.c cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/amlogic/amlogic_crureg.h cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/amlogic/amlogic_reg.h cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/amlogic/amlogic_var.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/amlogic/amlogic_board.c diff -u src/sys/arch/arm/amlogic/amlogic_board.c:1.7 src/sys/arch/arm/amlogic/amlogic_board.c:1.8 --- src/sys/arch/arm/amlogic/amlogic_board.c:1.7 Wed Mar 4 12:36:12 2015 +++ src/sys/arch/arm/amlogic/amlogic_board.c Sat Mar 7 21:32:47 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: amlogic_board.c,v 1.7 2015/03/04 12:36:12 jmcneill Exp $ */ +/* $NetBSD: amlogic_board.c,v 1.8 2015/03/07 21:32:47 jmcneill Exp $ */ /*- * Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca> @@ -29,7 +29,7 @@ #include "opt_amlogic.h" #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.7 2015/03/04 12:36:12 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.8 2015/03/07 21:32:47 jmcneill Exp $"); #define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> @@ -61,6 +61,10 @@ struct arm32_bus_dma_tag amlogic_dma_tag bus_space_write_4(&amlogic_bs_tag, amlogic_core_bsh, \ AMLOGIC_CBUS_OFFSET + (x), (v)) +#define CBUS_SET_CLEAR(x, s, c) \ + amlogic_reg_set_clear(&amlogic_bs_tag, amlogic_core_bsh, \ + AMLOGIC_CBUS_OFFSET + (x), (s), (c)) + void amlogic_bootstrap(void) { @@ -105,6 +109,26 @@ amlogic_get_rate_sys(void) } uint32_t +amlogic_get_rate_fixed(void) +{ + uint32_t cntl; + uint64_t clk; + u_int mul, div, od; + + clk = amlogic_get_rate_xtal(); + cntl = CBUS_READ(HHI_MPLL_CNTL_REG); + mul = __SHIFTOUT(cntl, HHI_MPLL_CNTL_MUL); + div = __SHIFTOUT(cntl, HHI_MPLL_CNTL_DIV); + od = __SHIFTOUT(cntl, HHI_MPLL_CNTL_OD); + + clk *= mul; + clk /= div; + clk >>= od; + + return (uint32_t)clk; +} + +uint32_t amlogic_get_rate_a9(void) { uint32_t cntl0, cntl1; @@ -164,6 +188,50 @@ amlogic_eth_init(void) CBUS_READ(EE_CLK_GATING1_REG) | EE_CLK_GATING1_ETHERNET); } +void +amlogic_rng_init(void) +{ + printf("%s: GATING0 = %#x, GATING3 = %#x\n", __func__, + CBUS_READ(EE_CLK_GATING0_REG), CBUS_READ(EE_CLK_GATING3_REG)); + + CBUS_WRITE(EE_CLK_GATING0_REG, + CBUS_READ(EE_CLK_GATING0_REG) | EE_CLK_GATING0_RNG); + CBUS_WRITE(EE_CLK_GATING3_REG, + CBUS_READ(EE_CLK_GATING3_REG) | EE_CLK_GATING3_RNG); + + printf("%s: GATING0 = %#x, GATING3 = %#x\n", __func__, + CBUS_READ(EE_CLK_GATING0_REG), CBUS_READ(EE_CLK_GATING3_REG)); +} + +void +amlogic_sdhc_init(void) +{ + /* CARD -> SDHC pin mux settings */ + CBUS_SET_CLEAR(PERIPHS_PIN_MUX_5_REG, 0, 0x00007c00); + CBUS_SET_CLEAR(PERIPHS_PIN_MUX_4_REG, 0, 0x7c000000); + CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x0000fc00); + CBUS_SET_CLEAR(PERIPHS_PIN_MUX_8_REG, 0, 0x00000600); + CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0x000000f0, 0); + + const uint32_t pupd_mask = __BITS(25,20); /* CARD_0-CARD_5 */ + CBUS_SET_CLEAR(CBUS_REG(0x203c), pupd_mask, 0); /* PU/PD */ + CBUS_SET_CLEAR(CBUS_REG(0x204a), pupd_mask, 0); /* PU/PD-EN */ + + const uint32_t io_mask = __BITS(27,22); /* CARD_0-CARD_5 */ + CBUS_SET_CLEAR(CBUS_REG(0x200c), io_mask, 0); /* OEN */ + + /* XXX ODROID-C1 specific */ + const uint32_t pwr_mask = __BIT(31); /* CARD_8 */ + CBUS_SET_CLEAR(CBUS_REG(0x201c), 0, pwr_mask); /* O */ + CBUS_SET_CLEAR(CBUS_REG(0x201b), 0, pwr_mask); /* OEN */ + const uint32_t cd_mask = __BIT(29); + CBUS_SET_CLEAR(CBUS_REG(0x201b), cd_mask, 0); /* OEN */ + + /* enable SDHC clk */ + CBUS_WRITE(EE_CLK_GATING0_REG, + CBUS_READ(EE_CLK_GATING0_REG) | EE_CLK_GATING0_SDHC); +} + static void amlogic_usbphy_clkgate_enable(int port) { Index: src/sys/arch/arm/amlogic/amlogic_crureg.h diff -u src/sys/arch/arm/amlogic/amlogic_crureg.h:1.5 src/sys/arch/arm/amlogic/amlogic_crureg.h:1.6 --- src/sys/arch/arm/amlogic/amlogic_crureg.h:1.5 Wed Mar 4 12:36:12 2015 +++ src/sys/arch/arm/amlogic/amlogic_crureg.h Sat Mar 7 21:32:47 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: amlogic_crureg.h,v 1.5 2015/03/04 12:36:12 jmcneill Exp $ */ +/* $NetBSD: amlogic_crureg.h,v 1.6 2015/03/07 21:32:47 jmcneill Exp $ */ /*- * Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca> @@ -36,6 +36,10 @@ #define EE_CLK_GATING2_REG CBUS_REG(0x1052) #define EE_CLK_GATING3_REG CBUS_REG(0x1054) +#define EE_CLK_GATING0_SDIO __BIT(17) +#define EE_CLK_GATING0_SDHC __BIT(14) +#define EE_CLK_GATING0_RNG __BIT(12) + #define EE_CLK_GATING1_USB_GENERAL __BIT(26) #define EE_CLK_GATING1_USB1 __BIT(22) #define EE_CLK_GATING1_USB0 __BIT(21) @@ -44,6 +48,7 @@ #define EE_CLK_GATING2_USB0_TO_DDR __BIT(9) #define EE_CLK_GATING2_USB1_TO_DDR __BIT(8) +#define EE_CLK_GATING3_RNG __BIT(21) #define HHI_SYS_CPU_CLK_CNTL1_REG CBUS_REG(0x1057) #define HHI_SYS_CPU_CLK_CNTL1_SDIV __BITS(29,20) @@ -59,12 +64,31 @@ #define HHI_SYS_PLL_CNTL_DIV __BITS(14,9) #define HHI_SYS_PLL_CNTL_OD __BITS(17,16) +#define HHI_MPLL_CNTL_REG CBUS_REG(0x10a0) +#define HHI_MPLL_CNTL_MUL __BITS(8,0) +#define HHI_MPLL_CNTL_DIV __BITS(13,9) +#define HHI_MPLL_CNTL_OD __BITS(17,16) + #define RESET1_REG CBUS_REG(0x1102) #define RESET1_USB __BIT(2) #define PREG_CTLREG0_ADDR_REG CBUS_REG(0x2000) #define PREG_CTLREG0_ADDR_CLKRATE __BITS(9,4) +#define PERIPHS_PIN_MUX_0_REG CBUS_REG(0x202c) +#define PERIPHS_PIN_MUX_1_REG CBUS_REG(0x202d) +#define PERIPHS_PIN_MUX_2_REG CBUS_REG(0x202e) +#define PERIPHS_PIN_MUX_3_REG CBUS_REG(0x202f) +#define PERIPHS_PIN_MUX_4_REG CBUS_REG(0x2030) +#define PERIPHS_PIN_MUX_5_REG CBUS_REG(0x2031) +#define PERIPHS_PIN_MUX_6_REG CBUS_REG(0x2032) +#define PERIPHS_PIN_MUX_7_REG CBUS_REG(0x2033) +#define PERIPHS_PIN_MUX_8_REG CBUS_REG(0x2034) +#define PERIPHS_PIN_MUX_9_REG CBUS_REG(0x2035) + +#define RAND64_ADDR0_REG CBUS_REG(0x2040) +#define RAND64_ADDR1_REG CBUS_REG(0x2041) + #define PREI_USB_PHY_A_CFG_REG CBUS_REG(0x2200) #define PREI_USB_PHY_A_CTRL_REG CBUS_REG(0x2201) #define PREI_USB_PHY_A_ADP_BC_REG CBUS_REG(0x2203) Index: src/sys/arch/arm/amlogic/amlogic_reg.h diff -u src/sys/arch/arm/amlogic/amlogic_reg.h:1.6 src/sys/arch/arm/amlogic/amlogic_reg.h:1.7 --- src/sys/arch/arm/amlogic/amlogic_reg.h:1.6 Wed Mar 4 12:36:12 2015 +++ src/sys/arch/arm/amlogic/amlogic_reg.h Sat Mar 7 21:32:47 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: amlogic_reg.h,v 1.6 2015/03/04 12:36:12 jmcneill Exp $ */ +/* $NetBSD: amlogic_reg.h,v 1.7 2015/03/07 21:32:47 jmcneill Exp $ */ /*- * Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca> @@ -35,22 +35,33 @@ #define AMLOGIC_CORE_SIZE 0x1b000000 #define AMLOGIC_CORE_VBASE 0xe0000000 +#define AMLOGIC_REF_FREQ 24000000 + #define AMLOGIC_CBUS_OFFSET 0x01100000 -#define AMLOGIC_UART0AO_OFFSET 0x081004c0 -#define AMLOGIC_UART2AO_OFFSET 0x081004e0 -#define AMLOGIC_UART_SIZE 0x20 -#define AMLOGIC_UART_FREQ 24000000 +#define AMLOGIC_RAND_OFFSET 0x01108100 +#define AMLOGIC_RAND_SIZE 0x8 + +#define AMLOGIC_SDIO_OFFSET 0x01108c20 +#define AMLOGIC_SDIO_SIZE 0x20 -#define AMLOGIC_MMC_OFFSET 0x01108e00 -#define AMLOGIC_MMC_SIZE 0x30 +#define AMLOGIC_SDHC_OFFSET 0x01108e00 +#define AMLOGIC_SDHC_SIZE 0x30 #define AMLOGIC_PL310_OFFSET 0x04200000 +#define AMLOGIC_DMC_OFFSET 0x08006000 +#define AMLOGIC_DMC_SIZE 0x400 + #define AMLOGIC_AOBUS_OFFSET 0x08100000 #define AMLOGIC_GPIOAO_OFFSET 0x08100024 +#define AMLOGIC_UART0AO_OFFSET 0x081004c0 +#define AMLOGIC_UART2AO_OFFSET 0x081004e0 +#define AMLOGIC_UART_SIZE 0x20 +#define AMLOGIC_UART_FREQ AMLOGIC_REF_FREQ + #define AMLOGIC_USB0_OFFSET 0x09040000 #define AMLOGIC_USB1_OFFSET 0x090c0000 #define AMLOGIC_USB_SIZE 0x40000 Index: src/sys/arch/arm/amlogic/amlogic_var.h diff -u src/sys/arch/arm/amlogic/amlogic_var.h:1.4 src/sys/arch/arm/amlogic/amlogic_var.h:1.5 --- src/sys/arch/arm/amlogic/amlogic_var.h:1.4 Thu Mar 5 23:43:53 2015 +++ src/sys/arch/arm/amlogic/amlogic_var.h Sat Mar 7 21:32:47 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: amlogic_var.h,v 1.4 2015/03/05 23:43:53 jmcneill Exp $ */ +/* $NetBSD: amlogic_var.h,v 1.5 2015/03/07 21:32:47 jmcneill Exp $ */ /*- * Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca> @@ -60,10 +60,24 @@ void amlogic_cpufreq_init(void); void amlogic_usbphy_init(int); void amlogic_eth_init(void); +void amlogic_sdhc_init(void); +void amlogic_rng_init(void); uint32_t amlogic_get_rate_xtal(void); uint32_t amlogic_get_rate_sys(void); +uint32_t amlogic_get_rate_fixed(void); uint32_t amlogic_get_rate_a9(void); uint32_t amlogic_get_rate_a9periph(void); +static void inline +amlogic_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh, + bus_size_t o, uint32_t set_mask, uint32_t clr_mask) +{ + const uint32_t old = bus_space_read_4(bst, bsh, o); + const uint32_t new = set_mask | (old & ~clr_mask); + if (old != new) { + bus_space_write_4(bst, bsh, o, new); + } +} + #endif /* _ARM_AMLOGIC_VAR_H */