Module Name: src
Committed By: jmcneill
Date: Sun Mar 29 10:41:59 UTC 2015
Added Files:
src/sys/arch/arm/nvidia: files.tegra soc_tegra124.c tegra_ahcisata.c
tegra_apbreg.h tegra_com.c tegra_ehci.c tegra_hdaudio.c
tegra_intr.h tegra_io.c tegra_mc.c tegra_mcreg.h tegra_pmc.c
tegra_pmcreg.h tegra_reg.h tegra_sdhc.c tegra_soc.c tegra_space.c
tegra_var.h
src/sys/arch/evbarm/conf: JETSONTK1 files.tegra mk.tegra std.tegra
src/sys/arch/evbarm/tegra: genassym.cf platform.h tegra_machdep.c
tegra_start.S
Log Message:
NVIDIA Tegra K1 support, work in progress.
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/nvidia/files.tegra \
src/sys/arch/arm/nvidia/soc_tegra124.c \
src/sys/arch/arm/nvidia/tegra_ahcisata.c \
src/sys/arch/arm/nvidia/tegra_apbreg.h \
src/sys/arch/arm/nvidia/tegra_com.c src/sys/arch/arm/nvidia/tegra_ehci.c \
src/sys/arch/arm/nvidia/tegra_hdaudio.c \
src/sys/arch/arm/nvidia/tegra_intr.h src/sys/arch/arm/nvidia/tegra_io.c \
src/sys/arch/arm/nvidia/tegra_mc.c src/sys/arch/arm/nvidia/tegra_mcreg.h \
src/sys/arch/arm/nvidia/tegra_pmc.c \
src/sys/arch/arm/nvidia/tegra_pmcreg.h \
src/sys/arch/arm/nvidia/tegra_reg.h src/sys/arch/arm/nvidia/tegra_sdhc.c \
src/sys/arch/arm/nvidia/tegra_soc.c src/sys/arch/arm/nvidia/tegra_space.c \
src/sys/arch/arm/nvidia/tegra_var.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbarm/conf/JETSONTK1 \
src/sys/arch/evbarm/conf/files.tegra src/sys/arch/evbarm/conf/mk.tegra \
src/sys/arch/evbarm/conf/std.tegra
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbarm/tegra/genassym.cf \
src/sys/arch/evbarm/tegra/platform.h \
src/sys/arch/evbarm/tegra/tegra_machdep.c \
src/sys/arch/evbarm/tegra/tegra_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/arm/nvidia/files.tegra
diff -u /dev/null src/sys/arch/arm/nvidia/files.tegra:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/files.tegra Sun Mar 29 10:41:59 2015
@@ -0,0 +1,64 @@
+# $NetBSD: files.tegra,v 1.1 2015/03/29 10:41:59 jmcneill Exp $
+#
+# Configuration info for NVIDIA Tegra ARM Peripherals
+#
+
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
+file arch/arm/arm32/arm32_boot.c
+file arch/arm/arm32/arm32_kvminit.c
+file arch/arm/arm32/arm32_reboot.c
+file arch/arm/arm32/irq_dispatch.S
+
+file arch/arm/nvidia/tegra_soc.c
+file arch/arm/nvidia/tegra_space.c
+file arch/arm/arm/bus_space_a4x.S
+file arch/arm/nvidia/soc_tegra124.c soc_tegra124
+
+# On-board I/O
+device tegraio { [port=-1] } : bus_space_generic
+attach tegraio at mainbus with tegra_io
+file arch/arm/nvidia/tegra_io.c tegra_io
+
+# Memory controller
+device tegramc
+attach tegramc at tegraio with tegra_mc
+file arch/arm/nvidia/tegra_mc.c tegra_mc
+
+# Power management controller
+device tegrapmc
+attach tegrapmc at tegraio with tegra_pmc
+file arch/arm/nvidia/tegra_pmc.c tegra_pmc
+
+# UART
+attach com at tegraio with tegra_com
+file arch/arm/nvidia/tegra_com.c tegra_com needs-flag
+
+# USB 2.0
+attach ehci at tegraio with tegra_ehci
+file arch/arm/nvidia/tegra_ehci.c tegra_ehci
+
+# SDMMC
+attach sdhc at tegraio with tegra_sdhc
+file arch/arm/nvidia/tegra_sdhc.c tegra_sdhc
+
+# SATA
+attach ahcisata at tegraio with tegra_ahcisata
+file arch/arm/nvidia/tegra_ahcisata.c tegra_ahcisata
+
+# HDA
+attach hdaudio at tegraio with tegra_hdaudio
+file arch/arm/nvidia/tegra_hdaudio.c tegra_hdaudio
+
+# Console parameters
+defparam opt_tegra.h CONADDR
+defparam opt_tegra.h CONSPEED
+defparam opt_tegra.h CONMODE
+
+# Memory parameters
+defparam opt_tegra.h MEMSIZE
+
+# SOC parameters
+defflag opt_tegra.h SOC_TEGRAK1
+defflag opt_tegra.h SOC_TEGRA124: SOC_TEGRAK1
Index: src/sys/arch/arm/nvidia/soc_tegra124.c
diff -u /dev/null src/sys/arch/arm/nvidia/soc_tegra124.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/soc_tegra124.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,57 @@
+/* $NetBSD: soc_tegra124.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_tegra.h"
+#include "opt_multiprocessor.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: soc_tegra124.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <arm/cpufunc.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_var.h>
+
+void
+tegra124_mpinit(void)
+{
+#if defined(MULTIPROCESSOR)
+ extern void cortex_mpstart(void);
+
+ arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
+
+ /* TODO */
+#endif
+}
Index: src/sys/arch/arm/nvidia/tegra_ahcisata.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_ahcisata.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_ahcisata.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,90 @@
+/* $NetBSD: tegra_ahcisata.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <dev/ata/atavar.h>
+#include <dev/ic/ahcisatavar.h>
+
+#include <arm/nvidia/tegra_var.h>
+
+static int tegra_ahcisata_match(device_t, cfdata_t, void *);
+static void tegra_ahcisata_attach(device_t, device_t, void *);
+
+struct tegra_ahcisata_softc {
+ struct ahci_softc sc;
+ void *sc_ih;
+};
+
+CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc),
+ tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL);
+
+static int
+tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+tegra_ahcisata_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_ahcisata_softc * const sc = device_private(self);
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+
+ sc->sc.sc_atac.atac_dev = self;
+ sc->sc.sc_dmat = tio->tio_dmat;
+ sc->sc.sc_ahcit = tio->tio_bst;
+ bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc.sc_ahcis);
+ sc->sc.sc_ahci_ports = 1;
+
+ aprint_naive("\n");
+ aprint_normal(": SATA\n");
+
+ sc->sc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
+ ahci_intr, &sc->sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt %d\n",
+ loc->loc_intr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
+
+ ahci_attach(&sc->sc);
+}
Index: src/sys/arch/arm/nvidia/tegra_apbreg.h
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_apbreg.h:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_apbreg.h Sun Mar 29 10:41:59 2015
@@ -0,0 +1,87 @@
+/* $NetBSD: tegra_apbreg.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_TEGRA_APBREG_H
+#define _ARM_TEGRA_APBREG_H
+
+#define APB_MISC_PP_CONFIG_CTL_0_REG 0x24
+#define APB_MISC_PP_PINMUX_GLOBAL_0_0_REG 0x40
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_REG 0xa8
+#define APB_MISC_SC1X_PADS_VIP_VCLKCTRL_0_REG 0x428
+#define APB_MISC_GP_HIDREV_0_REG 0x804
+#define APB_MISC_GP_MIPI_PAD_CTRL_0_REG 0x820
+#define APB_MISC_GP_AOCFG1PADCTRL_0_REG 0x868
+#define APB_MISC_GP_AOCFG2PADCTRL_0_REG 0x86c
+#define APB_MISC_GP_ATCFG1PADCTRL_0_REG 0x870
+#define APB_MISC_GP_ATCFG2PADCTRL_0_REG 0x874
+#define APB_MISC_GP_ATCFG3PADCTRL_0_REG 0x878
+#define APB_MISC_GP_ATCFG4PADCTRL_0_REG 0x87c
+#define APB_MISC_GP_ATCFG5PADCTRL_0_REG 0x880
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_REG 0x884
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_REG 0x888
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_REG 0x890
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_REG 0x894
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_REG 0x898
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_REG 0x89c
+#define APB_MISC_GP_DBGCFGPADCTRL_0_REG 0x8a0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_REG 0x8b0
+#define APB_MISC_GP_SPICFGPADCTRL_0_REG 0x8b4
+#define APB_MISC_GP_UAACFGPADCTRL_0_REG 0x8b8
+#define APB_MISC_GP_UABCFGPADCTRL_0_REG 0x8bc
+#define APB_MISC_GP_UART2CFGPADCTRL_0_REG 0x8c0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_REG 0x8c4
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_REG 0x8ec
+#define APB_MISC_GP_DDCCFGPADCTRL_0_REG 0x8fc
+#define APB_MISC_GP_GMCAFGPADCTRL_0_REG 0x900
+#define APB_MISC_GP_GMECFGPADCTRL_0_REG 0x910
+#define APB_MISC_GP_GMFCFGPADCTRL_0_REG 0x914
+#define APB_MISC_GP_GMGCFGPADCTRL_0_REG 0x918
+#define APB_MISC_GP_GMHCFGPADCTRL_0_REG 0x91c
+#define APB_MISC_GP_OWRCFGPADCTRL_0_REG 0x920
+#define APB_MISC_GP_UADCFGPADCTRL_0_REG 0x924
+#define APB_MISC_GP_GPVCFGPADCTRL_0_REG 0x928
+#define APB_MISC_GP_DEV3CFGPADCTRL_0_REG 0x92c
+#define APB_MISC_GP_CECCFGPADCTRL_0_REG 0x938
+#define APB_MISC_GP_ATCFG6PADCTRL_0_REG 0x994
+#define APB_MISC_GP_DAP5CFGPADCTRL_0_REG 0x998
+#define APB_MISC_GP_USB_VBUS_EN_CFGPADCTRL_0_REG 0x99c
+#define APB_MISC_GP_AOCFG3PADCTRL_0_REG 0x9a8
+#define APB_MISC_GP_AOCFG0PADCTRL_0_REG 0x9b0
+#define APB_MISC_GP_HVCFG0PADCTRL_0_REG 0x9b4
+#define APB_MISC_GP_SDIO4CFGPADCTRL_0_REG 0x9c4
+#define APB_MISC_GP_AOCFG4PADCTRL_0_REG 0x9c8
+#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0_REG 0xc00
+#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0_REG 0xc04
+#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0_REG 0xc08
+
+#define APB_MISC_GP_HIDREV_0_MINORREV __BITS(19,16)
+#define APB_MISC_GP_HIDREV_0_CHIPID __BITS(15,8)
+#define APB_MISC_GP_HIDREV_0_MAJORREV __BITS(7,4)
+#define APB_MISC_GP_HIDREV_0_HIDFAM __BITS(3,0)
+
+#endif /* _ARM_TEGRA_APBREG_H */
Index: src/sys/arch/arm/nvidia/tegra_com.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_com.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_com.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,109 @@
+/* $NetBSD: tegra_com.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: tegra_com.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/time.h>
+#include <sys/termios.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#include <dev/ic/comvar.h>
+
+static int tegra_com_match(device_t, cfdata_t, void *);
+static void tegra_com_attach(device_t, device_t, void *);
+
+struct tegra_com_softc {
+ struct com_softc tsc_sc;
+ void *tsc_ih;
+};
+
+CFATTACH_DECL_NEW(tegra_com, sizeof(struct tegra_com_softc),
+ tegra_com_match, tegra_com_attach, NULL, NULL);
+
+static int
+tegra_com_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+ bus_space_tag_t bst = tio->tio_a4x_bst;
+ bus_space_handle_t bsh;
+
+ if (com_is_console(bst, TEGRA_APB_BASE + loc->loc_offset, NULL))
+ return 1;
+
+ bus_space_subregion(bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &bsh);
+
+ return comprobe1(bst, bsh);
+}
+
+static void
+tegra_com_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_com_softc * const tsc = device_private(self);
+ struct com_softc * const sc = &tsc->tsc_sc;
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+ bus_space_tag_t bst = tio->tio_a4x_bst;
+ const bus_addr_t iobase = TEGRA_APB_BASE + loc->loc_offset;
+ bus_space_handle_t bsh;
+
+ sc->sc_dev = self;
+ sc->sc_frequency = TEGRA_UART_FREQ;
+ sc->sc_type = COM_TYPE_NORMAL;
+
+ if (com_is_console(bst, iobase, &bsh) == 0
+ && bus_space_subregion(bst, tio->tio_bsh,
+ loc->loc_offset / 4, loc->loc_size, &bsh)) {
+ panic(": can't map registers");
+ }
+ COM_INIT_REGS(sc->sc_regs, bst, bsh, iobase);
+
+ com_attach_subr(sc);
+ aprint_naive("\n");
+
+ tsc->tsc_ih = intr_establish(loc->loc_intr, IPL_SERIAL,
+ IST_LEVEL | IST_MPSAFE, comintr, sc);
+ if (tsc->tsc_ih == NULL)
+ panic("%s: failed to establish interrupt %d",
+ device_xname(self), loc->loc_intr);
+}
Index: src/sys/arch/arm/nvidia/tegra_ehci.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_ehci.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_ehci.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,109 @@
+/* $NetBSD: tegra_ehci.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_ehci.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+#include <dev/usb/ehcireg.h>
+#include <dev/usb/ehcivar.h>
+
+#include <arm/nvidia/tegra_var.h>
+
+static int tegra_ehci_match(device_t, cfdata_t, void *);
+static void tegra_ehci_attach(device_t, device_t, void *);
+
+struct tegra_ehci_softc {
+ struct ehci_softc sc;
+ void *sc_ih;
+};
+
+CFATTACH_DECL2_NEW(tegra_ehci, sizeof(struct tegra_ehci_softc),
+ tegra_ehci_match, tegra_ehci_attach, NULL,
+ ehci_activate, NULL, ehci_childdet);
+
+static int
+tegra_ehci_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+tegra_ehci_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_ehci_softc * const sc = device_private(self);
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+ int error;
+
+ sc->sc.sc_dev = self;
+ sc->sc.sc_bus.hci_private = &sc->sc;
+ sc->sc.sc_bus.dmatag = tio->tio_dmat;
+ sc->sc.sc_bus.usbrev = USBREV_2_0;
+ sc->sc.sc_flags = EHCIF_ETTF;
+ sc->sc.sc_id_vendor = 0x10de;
+ strlcpy(sc->sc.sc_vendor, "Tegra", sizeof(sc->sc.sc_vendor));
+ sc->sc.sc_size = loc->loc_size;
+ sc->sc.iot = tio->tio_bst;
+ bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc.ioh);
+
+ aprint_naive("\n");
+ aprint_normal(": USB%d\n", loc->loc_port + 1);
+
+ sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
+
+ sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
+ ehci_intr, &sc->sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt %d\n",
+ loc->loc_intr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
+
+ error = ehci_init(&sc->sc);
+ if (error != USBD_NORMAL_COMPLETION) {
+ aprint_error_dev(self, "init failed, error = %d\n", error);
+ return;
+ }
+
+ sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
+}
Index: src/sys/arch/arm/nvidia/tegra_hdaudio.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_hdaudio.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_hdaudio.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,136 @@
+/* $NetBSD: tegra_hdaudio.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_hdaudio.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <dev/hdaudio/hdaudioreg.h>
+#include <dev/hdaudio/hdaudiovar.h>
+
+#include <arm/nvidia/tegra_var.h>
+
+static int tegra_hdaudio_match(device_t, cfdata_t, void *);
+static void tegra_hdaudio_attach(device_t, device_t, void *);
+static int tegra_hdaudio_detach(device_t, int);
+static int tegra_hdaudio_rescan(device_t, const char *, const int *);
+static void tegra_hdaudio_childdet(device_t, device_t);
+
+static int tegra_hdaudio_intr(void *);
+
+struct tegra_hdaudio_softc {
+ struct hdaudio_softc sc;
+ void *sc_ih;
+};
+
+CFATTACH_DECL2_NEW(tegra_hdaudio, sizeof(struct tegra_hdaudio_softc),
+ tegra_hdaudio_match, tegra_hdaudio_attach, tegra_hdaudio_detach, NULL,
+ tegra_hdaudio_rescan, tegra_hdaudio_childdet);
+
+static int
+tegra_hdaudio_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+tegra_hdaudio_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_hdaudio_softc * const sc = device_private(self);
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+
+ sc->sc.sc_memt = tio->tio_bst;
+ bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc.sc_memh);
+ sc->sc.sc_memvalid = true;
+ sc->sc.sc_dmat = tio->tio_dmat;
+
+ aprint_naive("\n");
+ aprint_normal(": SATA\n");
+
+ sc->sc_ih = intr_establish(loc->loc_intr, IPL_AUDIO, IST_LEVEL,
+ tegra_hdaudio_intr, sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt %d\n",
+ loc->loc_intr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
+
+ hdaudio_attach(self, &sc->sc);
+}
+
+static int
+tegra_hdaudio_detach(device_t self, int flags)
+{
+ struct tegra_hdaudio_softc * const sc = device_private(self);
+
+ hdaudio_detach(&sc->sc, flags);
+
+ if (sc->sc_ih) {
+ intr_disestablish(sc->sc_ih);
+ sc->sc_ih = NULL;
+ }
+
+ sc->sc.sc_memvalid = false;
+
+ return 0;
+}
+
+static int
+tegra_hdaudio_rescan(device_t self, const char *ifattr, const int *locs)
+{
+ struct tegra_hdaudio_softc * const sc = device_private(self);
+
+ return hdaudio_rescan(&sc->sc, ifattr, locs);
+}
+
+static void
+tegra_hdaudio_childdet(device_t self, device_t child)
+{
+ struct tegra_hdaudio_softc * const sc = device_private(self);
+
+ hdaudio_childdet(&sc->sc, child);
+}
+
+static int
+tegra_hdaudio_intr(void *priv)
+{
+ struct tegra_hdaudio_softc * const sc = priv;
+
+ return hdaudio_intr(&sc->sc);
+}
Index: src/sys/arch/arm/nvidia/tegra_intr.h
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_intr.h:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_intr.h Sun Mar 29 10:41:59 2015
@@ -0,0 +1,54 @@
+/* $NetBSD: tegra_intr.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_TEGRA_INTR_H
+#define _ARM_TEGRA_INTR_H
+
+#define PIC_MAXSOURCES 192
+#define PIC_MAXMAXSOURCES (PIC_MAXSOURCES + 32)
+
+#include <arm/cortex/gic_intr.h>
+#include <arm/cortex/gtmr_intr.h>
+
+#define TEGRA_INTR(x) ((x) + 32)
+
+#define TEGRA_INTR_SDMMC1 TEGRA_INTR(14)
+#define TEGRA_INTR_SDMMC2 TEGRA_INTR(15)
+#define TEGRA_INTR_SDMMC3 TEGRA_INTR(19)
+#define TEGRA_INTR_USB1 TEGRA_INTR(20)
+#define TEGRA_INTR_USB2 TEGRA_INTR(21)
+#define TEGRA_INTR_SATA TEGRA_INTR(23)
+#define TEGRA_INTR_SDMMC4 TEGRA_INTR(31)
+#define TEGRA_INTR_UARTA TEGRA_INTR(36)
+#define TEGRA_INTR_UARTB TEGRA_INTR(37)
+#define TEGRA_INTR_UARTC TEGRA_INTR(46)
+#define TEGRA_INTR_HDA TEGRA_INTR(81)
+#define TEGRA_INTR_UARTD TEGRA_INTR(90)
+#define TEGRA_INTR_USB3 TEGRA_INTR(97)
+
+#endif /* _ARM_TEGRA_INTR_H */
Index: src/sys/arch/arm/nvidia/tegra_io.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_io.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_io.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,165 @@
+/* $NetBSD: tegra_io.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_tegra.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <machine/cpu.h>
+#include <sys/bus.h>
+
+#include <arm/mainbus/mainbus.h>
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#include "locators.h"
+
+static int tegraio_match(device_t, cfdata_t, void *);
+static void tegraio_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(tegra_io, 0,
+ tegraio_match, tegraio_attach, NULL, NULL);
+
+static int tegraio_print(void *, const char *);
+static int tegraio_find(device_t, cfdata_t, const int *, void *);
+
+static void tegraio_scan(device_t, bus_space_handle_t,
+ const struct tegra_locators *, u_int);
+
+static bool tegraio_found = false;
+
+#define NOPORT TEGRAIOCF_PORT_DEFAULT
+#define NOINTR TEGRAIO_INTR_DEFAULT
+
+static const struct tegra_locators tegra_apb_locators[] = {
+ { "tegramc",
+ TEGRA_MC_OFFSET, TEGRA_MC_SIZE, NOPORT, NOINTR },
+ { "tegrapmc",
+ TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, NOPORT, NOINTR },
+ { "com",
+ TEGRA_UARTA_OFFSET, TEGRA_UARTA_SIZE, 0, TEGRA_INTR_UARTA },
+ { "com",
+ TEGRA_UARTB_OFFSET, TEGRA_UARTB_SIZE, 1, TEGRA_INTR_UARTB },
+ { "com",
+ TEGRA_UARTC_OFFSET, TEGRA_UARTC_SIZE, 2, TEGRA_INTR_UARTC },
+ { "com",
+ TEGRA_UARTD_OFFSET, TEGRA_UARTD_SIZE, 3, TEGRA_INTR_UARTD },
+ { "sdhc",
+ TEGRA_SDMMC1_OFFSET, TEGRA_SDMMC1_SIZE, 0, TEGRA_INTR_SDMMC1 },
+ { "sdhc",
+ TEGRA_SDMMC2_OFFSET, TEGRA_SDMMC2_SIZE, 1, TEGRA_INTR_SDMMC2 },
+ { "sdhc",
+ TEGRA_SDMMC3_OFFSET, TEGRA_SDMMC3_SIZE, 2, TEGRA_INTR_SDMMC3 },
+ { "sdhc",
+ TEGRA_SDMMC4_OFFSET, TEGRA_SDMMC4_SIZE, 3, TEGRA_INTR_SDMMC4 },
+ { "ahcisata",
+ TEGRA_SATA_OFFSET, TEGRA_SATA_SIZE, NOPORT, TEGRA_INTR_SATA },
+ { "hdaudio",
+ TEGRA_HDA_OFFSET, TEGRA_HDA_SIZE, NOPORT, TEGRA_INTR_HDA },
+};
+
+static const struct tegra_locators tegra_ahb_a2_locators[] = {
+ { "ehci",
+ TEGRA_USB1_OFFSET, TEGRA_USB1_SIZE, 0, TEGRA_INTR_USB1 },
+ { "ehci",
+ TEGRA_USB2_OFFSET, TEGRA_USB2_SIZE, 1, TEGRA_INTR_USB2 },
+ { "ehci",
+ TEGRA_USB3_OFFSET, TEGRA_USB3_SIZE, 2, TEGRA_INTR_USB3 },
+};
+
+int
+tegraio_match(device_t parent, cfdata_t cf, void *aux)
+{
+ if (tegraio_found)
+ return 0;
+ return 1;
+}
+
+void
+tegraio_attach(device_t parent, device_t self, void *aux)
+{
+ tegraio_found = true;
+
+ aprint_naive("\n");
+ aprint_normal(": %s\n", tegra_chip_name());
+
+ tegraio_scan(self, tegra_apb_bsh,
+ tegra_apb_locators, __arraycount(tegra_apb_locators));
+ tegraio_scan(self, tegra_ahb_a2_bsh,
+ tegra_ahb_a2_locators, __arraycount(tegra_ahb_a2_locators));
+}
+
+static void
+tegraio_scan(device_t self, bus_space_handle_t bsh,
+ const struct tegra_locators *locators, u_int count)
+{
+ const struct tegra_locators * const eloc = locators + count;
+ for (const struct tegra_locators *loc = locators; loc < eloc; loc++) {
+ struct tegraio_attach_args tio = {
+ .tio_loc = *loc,
+ .tio_bst = &tegra_bs_tag,
+ .tio_a4x_bst = &tegra_a4x_bs_tag,
+ .tio_bsh = bsh,
+ .tio_dmat = &tegra_dma_tag,
+ };
+ cfdata_t cf = config_search_ia(tegraio_find, self,
+ "tegraio", &tio);
+ if (cf != NULL)
+ config_attach(self, cf, &tio, tegraio_print);
+ }
+}
+
+int
+tegraio_print(void *aux, const char *pnp)
+{
+ const struct tegraio_attach_args * const tio = aux;
+
+ if (tio->tio_loc.loc_port != TEGRAIOCF_PORT_DEFAULT)
+ aprint_normal(" port %d", tio->tio_loc.loc_port);
+
+ return UNCONF;
+}
+
+static int
+tegraio_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
+{
+ const struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+ const int port = cf->cf_loc[TEGRAIOCF_PORT];
+
+ if (strcmp(cf->cf_name, loc->loc_name)
+ || (port != TEGRAIOCF_PORT_DEFAULT && port != loc->loc_port))
+ return 0;
+
+ return config_match(parent, cf, aux);
+}
Index: src/sys/arch/arm/nvidia/tegra_mc.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_mc.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_mc.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,103 @@
+/* $NetBSD: tegra_mc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_mc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_mcreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+static int tegra_mc_match(device_t, cfdata_t, void *);
+static void tegra_mc_attach(device_t, device_t, void *);
+
+struct tegra_mc_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
+
+static struct tegra_mc_softc *mc_softc = NULL;
+
+CFATTACH_DECL_NEW(tegra_mc, sizeof(struct tegra_mc_softc),
+ tegra_mc_match, tegra_mc_attach, NULL, NULL);
+
+static int
+tegra_mc_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+tegra_mc_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_mc_softc * const sc = device_private(self);
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+
+ sc->sc_dev = self;
+ sc->sc_bst = tio->tio_bst;
+ bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
+ KASSERT(mc_softc == NULL);
+ mc_softc = sc;
+
+ aprint_naive("\n");
+ aprint_normal(": MC\n");
+}
+
+psize_t
+tegra_mc_memsize(void)
+{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+
+ if (mc_softc) {
+ bst = mc_softc->sc_bst;
+ bsh = mc_softc->sc_bsh;
+ } else {
+ bst = &tegra_bs_tag;
+ bus_space_subregion(bst, tegra_apb_bsh,
+ TEGRA_MC_OFFSET, TEGRA_MC_SIZE, &bsh);
+ }
+
+ const uint32_t emem_cfg = bus_space_read_4(bst, bsh, MC_EMEM_CFG_0_REG);
+ const psize_t nmb = __SHIFTOUT(emem_cfg, MC_EMEM_CFG_0_EMEM_SIZE_MB);
+
+ return nmb * 1024 * 1024;
+}
Index: src/sys/arch/arm/nvidia/tegra_mcreg.h
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_mcreg.h:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_mcreg.h Sun Mar 29 10:41:59 2015
@@ -0,0 +1,37 @@
+/* $NetBSD: tegra_mcreg.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_TEGRA_MCREG_H
+#define _ARM_TEGRA_MCREG_H
+
+#define MC_EMEM_CFG_0_REG 0x50
+
+#define MC_EMEM_CFG_0_EMEM_BOM __BIT(31)
+#define MC_EMEM_CFG_0_EMEM_SIZE_MB __BITS(13,0)
+
+#endif /* _ARM_TEGRA_MCREG_H */
Index: src/sys/arch/arm/nvidia/tegra_pmc.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_pmc.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_pmc.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,107 @@
+/* $NetBSD: tegra_pmc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_pmc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_pmcreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+static int tegra_pmc_match(device_t, cfdata_t, void *);
+static void tegra_pmc_attach(device_t, device_t, void *);
+
+struct tegra_pmc_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
+
+static struct tegra_pmc_softc *pmc_softc = NULL;
+
+CFATTACH_DECL_NEW(tegra_pmc, sizeof(struct tegra_pmc_softc),
+ tegra_pmc_match, tegra_pmc_attach, NULL, NULL);
+
+static int
+tegra_pmc_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+tegra_pmc_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_pmc_softc * const sc = device_private(self);
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+
+ sc->sc_dev = self;
+ sc->sc_bst = tio->tio_bst;
+ bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
+ KASSERT(pmc_softc == NULL);
+ pmc_softc = sc;
+
+ aprint_naive("\n");
+ aprint_normal(": PMC\n");
+}
+
+void
+tegra_pmc_reset(void)
+{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+ uint32_t cntrl;
+
+ if (pmc_softc) {
+ bst = pmc_softc->sc_bst;
+ bsh = pmc_softc->sc_bsh;
+ } else {
+ bst = &tegra_bs_tag;
+ bus_space_subregion(bst, tegra_apb_bsh,
+ TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, &bsh);
+ }
+
+ cntrl = bus_space_read_4(bst, bsh, PMC_CNTRL_0_REG);
+ cntrl |= PMC_CNTRL_0_MAIN_RST;
+ bus_space_write_4(bst, bsh, PMC_CNTRL_0_REG, cntrl);
+
+ for (;;) {
+ __asm("wfi");
+ }
+}
Index: src/sys/arch/arm/nvidia/tegra_pmcreg.h
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_pmcreg.h:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_pmcreg.h Sun Mar 29 10:41:59 2015
@@ -0,0 +1,56 @@
+/* $NetBSD: tegra_pmcreg.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_TEGRA_PMCREG_H
+#define _ARM_TEGRA_PMCREG_H
+
+#define PMC_CNTRL_0_REG 0x00
+
+#define PMC_CNTRL_0_CPUPWRGOOD_SEL __BITS(21,20)
+#define PMC_CNTRL_0_CPUPWRGOOD_EN __BIT(19)
+#define PMC_CNTRL_0_FUSE_OVERRIDE __BIT(18)
+#define PMC_CNTRL_0_INTR_POLARITY __BIT(17)
+#define PMC_CNTRL_0_CPUPWRREG_OE __BIT(16)
+#define PMC_CNTRL_0_CPUPWRREG_POLARITY __BIT(15)
+#define PMC_CNTRL_0_SIDE_EFFECT_LP0 __BIT(14)
+#define PMC_CNTRL_0_AOINIT __BIT(13)
+#define PMC_CNTRL_0_PWRGATE_DIS __BIT(12)
+#define PMC_CNTRL_0_SYSCLK_OE __BIT(11)
+#define PMC_CNTRL_0_SYSCLK_POLARITY __BIT(10)
+#define PMC_CNTRL_0_PWRREQ_OE __BIT(9)
+#define PMC_CNTRL_0_PWRREQ_POLARITY __BIT(8)
+#define PMC_CNTRL_0_BLINK_EN __BIT(7)
+#define PMC_CNTRL_0_GLITCHDET_DIS __BIT(6)
+#define PMC_CNTRL_0_LATCHWAKE_EN __BIT(5)
+#define PMC_CNTRL_0_MAIN_RST __BIT(4)
+#define PMC_CNTRL_0_KBC_RST __BIT(3)
+#define PMC_CNTRL_0_RTC_RST __BIT(2)
+#define PMC_CNTRL_0_RTC_CLK_DIS __BIT(1)
+#define PMC_CNTRL_0_KBC_CLK_DIS __BIT(0)
+
+#endif /* _ARM_TEGRA_PMCREG_H */
Index: src/sys/arch/arm/nvidia/tegra_reg.h
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_reg.h:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_reg.h Sun Mar 29 10:41:59 2015
@@ -0,0 +1,95 @@
+/* $NetBSD: tegra_reg.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_TEGRA_REG_H
+#define _ARM_TEGRA_REG_H
+
+#define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE)
+
+#define TEGRA_EXTMEM_BASE 0x80000000
+
+#define TEGRA_HOST1X_BASE 0x50000000
+#define TEGRA_HOST1X_SIZE 0x00100000
+#define TEGRA_PPSB_BASE 0x60000000
+#define TEGRA_PPSB_SIZE 0x01000000
+#define TEGRA_APB_BASE 0x70000000
+#define TEGRA_APB_SIZE 0x01000000
+#define TEGRA_AHB_A2_BASE 0x7c000000
+#define TEGRA_AHB_A2_SIZE 0x02000000
+
+#define TEGRA_HOST1X_VBASE 0xfd000000
+#define TEGRA_APB_VBASE 0xfe000000
+
+#define TEGRA_REF_FREQ 12000000
+#define TEGRA_UART_FREQ TEGRA_REF_FREQ
+
+/* APB */
+#define TEGRA_UARTA_OFFSET 0x00006000
+#define TEGRA_UARTA_SIZE 0x40
+#define TEGRA_UARTB_OFFSET 0x00006040
+#define TEGRA_UARTB_SIZE 0x40
+#define TEGRA_UARTC_OFFSET 0x00006200
+#define TEGRA_UARTC_SIZE 0x100
+#define TEGRA_UARTD_OFFSET 0x00006300
+#define TEGRA_UARTD_SIZE 0x100
+#define TEGRA_RTC_OFFSET 0x0000e000
+#define TEGRA_RTC_SIZE 0x100
+#define TEGRA_KBC_OFFSET 0x0000e200
+#define TEGRA_KBC_SIZE 0x100
+#define TEGRA_PMC_OFFSET 0x0000e400
+#define TEGRA_PMC_SIZE 0x800
+#define TEGRA_MC_OFFSET 0x00019000
+#define TEGRA_MC_SIZE 0x1000
+#define TEGRA_SATA_OFFSET 0x00020000
+#define TEGRA_SATA_SIZE 0x10000
+#define TEGRA_HDA_OFFSET 0x00030000
+#define TEGRA_HDA_SIZE 0x10000
+#define TEGRA_XUSB_PADCTL_OFFSET 0x0009f000
+#define TEGRA_XUSB_PADCTL_SIZE 0x1000
+#define TEGRA_XUSB_HOST_OFFSET 0x00090000
+#define TEGRA_XUSB_HOST_SIZE 0xa000
+#define TEGRA_SDMMC1_OFFSET 0x000b0000
+#define TEGRA_SDMMC1_SIZE 0x200
+#define TEGRA_SDMMC2_OFFSET 0x000b0200
+#define TEGRA_SDMMC2_SIZE 0x200
+#define TEGRA_SDMMC3_OFFSET 0x000b0400
+#define TEGRA_SDMMC3_SIZE 0x200
+#define TEGRA_SDMMC4_OFFSET 0x000b0600
+#define TEGRA_SDMMC4_SIZE 0x200
+#define TEGRA_XUSB_DEV_OFFSET 0x000d0000
+#define TEGRA_XUSB_DEV_SIZE 0xa000
+
+/* AHB_A2 */
+#define TEGRA_USB1_OFFSET 0x01000000
+#define TEGRA_USB1_SIZE 0x1800
+#define TEGRA_USB2_OFFSET 0x01004000
+#define TEGRA_USB2_SIZE 0x1800
+#define TEGRA_USB3_OFFSET 0x01008000
+#define TEGRA_USB3_SIZE 0x1800
+
+#endif /* _ARM_TEGRA_REG_H */
Index: src/sys/arch/arm/nvidia/tegra_sdhc.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_sdhc.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_sdhc.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,135 @@
+/* $NetBSD: tegra_sdhc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <dev/sdmmc/sdhcreg.h>
+#include <dev/sdmmc/sdhcvar.h>
+#include <dev/sdmmc/sdmmcvar.h>
+
+#include <arm/nvidia/tegra_var.h>
+
+/* 8-bit eMMC is supported on SDMMC2 and SDMMC4 */
+#define SDMMC_8BIT_P(port) ((port) == 1 || (port) == 3)
+
+static int tegra_sdhc_match(device_t, cfdata_t, void *);
+static void tegra_sdhc_attach(device_t, device_t, void *);
+
+static void tegra_sdhc_attach_i(device_t);
+
+struct tegra_sdhc_softc {
+ struct sdhc_softc sc;
+
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ bus_size_t sc_bsz;
+ struct sdhc_host *sc_host;
+ void *sc_ih;
+};
+
+CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc),
+ tegra_sdhc_match, tegra_sdhc_attach, NULL, NULL);
+
+static int
+tegra_sdhc_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+tegra_sdhc_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_sdhc_softc * const sc = device_private(self);
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+
+ sc->sc.sc_dev = self;
+ sc->sc.sc_dmat = tio->tio_dmat;
+ sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS |
+ SDHC_FLAG_USE_DMA;
+ if (SDMMC_8BIT_P(loc->loc_port)) {
+ sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
+ }
+ sc->sc.sc_host = &sc->sc_host;
+
+ sc->sc_bst = tio->tio_bst;
+ bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+ sc->sc_bsz = loc->loc_size;
+
+#if notyet
+ sc->sc.sc_clkbase = tegra_sdhc_get_freq(loc->loc_port) / 1000;
+#else
+ sc->sc.sc_clkbase = 0;
+#endif
+
+ aprint_naive("\n");
+ aprint_normal(": SDMMC%d\n", loc->loc_port + 1);
+
+ if (sc->sc.sc_clkbase == 0) {
+ aprint_error_dev(self, "couldn't determine frequency\n");
+ return;
+ }
+
+ sc->sc_ih = intr_establish(loc->loc_intr, IPL_SDMMC, IST_LEVEL,
+ sdhc_intr, &sc->sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt %d\n",
+ loc->loc_intr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
+
+ config_interrupts(self, tegra_sdhc_attach_i);
+}
+
+static void
+tegra_sdhc_attach_i(device_t self)
+{
+ struct tegra_sdhc_softc * const sc = device_private(self);
+ int error;
+
+ error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz);
+ if (error) {
+ aprint_error_dev(self, "couldn't initialize host, error = %d\n",
+ error);
+ intr_disestablish(sc->sc_ih);
+ sc->sc_ih = NULL;
+ return;
+ }
+}
Index: src/sys/arch/arm/nvidia/tegra_soc.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_soc.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_soc.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,122 @@
+/* $NetBSD: tegra_soc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_tegra.h"
+#include "opt_multiprocessor.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_soc.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <arm/bootconfig.h>
+#include <arm/cpufunc.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_apbreg.h>
+#include <arm/nvidia/tegra_mcreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+bus_space_handle_t tegra_host1x_bsh;
+bus_space_handle_t tegra_apb_bsh;
+bus_space_handle_t tegra_ahb_a2_bsh;
+
+struct arm32_bus_dma_tag tegra_dma_tag = {
+ _BUS_DMAMAP_FUNCS,
+ _BUS_DMAMEM_FUNCS,
+ _BUS_DMATAG_FUNCS,
+};
+
+#if defined(MULTIPROCESSOR)
+static void tegra_mpinit(void);
+#endif
+
+void
+tegra_bootstrap(void)
+{
+ bus_space_map(&tegra_bs_tag, TEGRA_HOST1X_BASE, TEGRA_HOST1X_SIZE, 0,
+ &tegra_host1x_bsh);
+ bus_space_map(&tegra_bs_tag, TEGRA_APB_BASE, TEGRA_APB_SIZE, 0,
+ &tegra_apb_bsh);
+ bus_space_map(&tegra_bs_tag, TEGRA_AHB_A2_BASE, TEGRA_AHB_A2_SIZE, 0,
+ &tegra_ahb_a2_bsh);
+
+ curcpu()->ci_data.cpu_cc_freq = 696000000; /* XXX */
+
+#if defined(MULTIPROCESSOR)
+ tegra_mpinit();
+#endif
+}
+
+#if defined(MULTIPROCESSOR)
+static void
+tegra_mpinit(void)
+{
+ switch (tegra_chip_id()) {
+#ifdef SOC_TEGRA124
+ case CHIP_ID_TEGRA124:
+ tegra124_mpinit();
+ break;
+#endif
+ default:
+ panic("Unsupported SOC ID %#x", tegra_chip_id());
+ }
+}
+#endif
+
+u_int
+tegra_chip_id(void)
+{
+ static u_int chip_id = 0;
+
+ if (!chip_id) {
+ const bus_space_tag_t bst = &tegra_bs_tag;
+ const bus_space_handle_t bsh = tegra_apb_bsh;
+ const uint32_t v = bus_space_read_4(bst, bsh,
+ APB_MISC_GP_HIDREV_0_REG);
+ chip_id = __SHIFTOUT(v, APB_MISC_GP_HIDREV_0_CHIPID);
+ }
+
+ return chip_id;
+}
+
+const char *
+tegra_chip_name(void)
+{
+ switch (tegra_chip_id()) {
+ case CHIP_ID_TEGRA124: return "Tegra K1 (T124)";
+ case CHIP_ID_TEGRA132: return "Tegra K1 (T132)";
+ default: return "Unknown Tegra SoC";
+ }
+}
Index: src/sys/arch/arm/nvidia/tegra_space.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_space.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_space.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,416 @@
+/* $NetBSD: tegra_space.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_space.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <sys/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(tegra);
+bs_protos(tegra_a4x);
+bs_protos(a4x);
+bs_protos(bs_notimpl);
+bs_protos(generic);
+bs_protos(generic_armv4);
+
+#if __ARMEB__
+#define NSWAP(n) n ## _swap
+#else
+#define NSWAP(n) n
+#endif
+
+struct bus_space tegra_bs_tag = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ tegra_bs_map,
+ tegra_bs_unmap,
+ tegra_bs_subregion,
+
+ /* allocation/deallocation */
+ tegra_bs_alloc, /* not implemented */
+ tegra_bs_free, /* not implemented */
+
+ /* get kernel virtual address */
+ tegra_bs_vaddr,
+
+ /* mmap */
+ tegra_bs_mmap,
+
+ /* barrier */
+ tegra_bs_barrier,
+
+ /* read (single) */
+ generic_bs_r_1,
+ NSWAP(generic_armv4_bs_r_2),
+ NSWAP(generic_bs_r_4),
+ bs_notimpl_bs_r_8,
+
+ /* read multiple */
+ generic_bs_rm_1,
+ NSWAP(generic_armv4_bs_rm_2),
+ NSWAP(generic_bs_rm_4),
+ bs_notimpl_bs_rm_8,
+
+ /* read region */
+ generic_bs_rr_1,
+ NSWAP(generic_armv4_bs_rr_2),
+ NSWAP(generic_bs_rr_4),
+ bs_notimpl_bs_rr_8,
+
+ /* write (single) */
+ generic_bs_w_1,
+ NSWAP(generic_armv4_bs_w_2),
+ NSWAP(generic_bs_w_4),
+ bs_notimpl_bs_w_8,
+
+ /* write multiple */
+ generic_bs_wm_1,
+ NSWAP(generic_armv4_bs_wm_2),
+ NSWAP(generic_bs_wm_4),
+ bs_notimpl_bs_wm_8,
+
+ /* write region */
+ generic_bs_wr_1,
+ NSWAP(generic_armv4_bs_wr_2),
+ NSWAP(generic_bs_wr_4),
+ bs_notimpl_bs_wr_8,
+
+ /* set multiple */
+ bs_notimpl_bs_sm_1,
+ bs_notimpl_bs_sm_2,
+ bs_notimpl_bs_sm_4,
+ bs_notimpl_bs_sm_8,
+
+ /* set region */
+ generic_bs_sr_1,
+ NSWAP(generic_armv4_bs_sr_2),
+ bs_notimpl_bs_sr_4,
+ bs_notimpl_bs_sr_8,
+
+ /* copy */
+ bs_notimpl_bs_c_1,
+ generic_armv4_bs_c_2,
+ bs_notimpl_bs_c_4,
+ bs_notimpl_bs_c_8,
+
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+ /* read (single) */
+ generic_bs_r_1,
+ NSWAP(generic_armv4_bs_r_2),
+ NSWAP(generic_bs_r_4),
+ bs_notimpl_bs_r_8,
+
+ /* read multiple */
+ generic_bs_rm_1,
+ NSWAP(generic_armv4_bs_rm_2),
+ NSWAP(generic_bs_rm_4),
+ bs_notimpl_bs_rm_8,
+
+ /* read region */
+ generic_bs_rr_1,
+ NSWAP(generic_armv4_bs_rr_2),
+ NSWAP(generic_bs_rr_4),
+ bs_notimpl_bs_rr_8,
+
+ /* write (single) */
+ generic_bs_w_1,
+ NSWAP(generic_armv4_bs_w_2),
+ NSWAP(generic_bs_w_4),
+ bs_notimpl_bs_w_8,
+
+ /* write multiple */
+ generic_bs_wm_1,
+ NSWAP(generic_armv4_bs_wm_2),
+ NSWAP(generic_bs_wm_4),
+ bs_notimpl_bs_wm_8,
+
+ /* write region */
+ generic_bs_wr_1,
+ NSWAP(generic_armv4_bs_wr_2),
+ NSWAP(generic_bs_wr_4),
+ bs_notimpl_bs_wr_8,
+#endif
+};
+
+struct bus_space tegra_a4x_bs_tag = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ tegra_bs_map,
+ tegra_bs_unmap,
+ tegra_a4x_bs_subregion,
+
+ /* allocation/deallocation */
+ tegra_bs_alloc, /* not implemented */
+ tegra_bs_free, /* not implemented */
+
+ /* get kernel virtual address */
+ tegra_bs_vaddr,
+
+ /* mmap */
+ tegra_a4x_bs_mmap,
+
+ /* barrier */
+ tegra_bs_barrier,
+
+ /* read (single) */
+ a4x_bs_r_1,
+ NSWAP(a4x_bs_r_2),
+ NSWAP(a4x_bs_r_4),
+ bs_notimpl_bs_r_8,
+
+ /* read multiple */
+ a4x_bs_rm_1,
+ NSWAP(a4x_bs_rm_2),
+ NSWAP(a4x_bs_rm_4),
+ bs_notimpl_bs_rm_8,
+
+ /* read region */
+ bs_notimpl_bs_rr_1,
+ bs_notimpl_bs_rr_2,
+ bs_notimpl_bs_rr_4,
+ bs_notimpl_bs_rr_8,
+
+ /* write (single) */
+ a4x_bs_w_1,
+ NSWAP(a4x_bs_w_2),
+ NSWAP(a4x_bs_w_4),
+ bs_notimpl_bs_w_8,
+
+ /* write multiple */
+ a4x_bs_wm_1,
+ NSWAP(a4x_bs_wm_2),
+ NSWAP(a4x_bs_wm_4),
+ bs_notimpl_bs_wm_8,
+
+ /* write region */
+ bs_notimpl_bs_wr_1,
+ bs_notimpl_bs_wr_2,
+ bs_notimpl_bs_wr_4,
+ bs_notimpl_bs_wr_8,
+
+ /* set multiple */
+ bs_notimpl_bs_sm_1,
+ bs_notimpl_bs_sm_2,
+ bs_notimpl_bs_sm_4,
+ bs_notimpl_bs_sm_8,
+
+ /* set region */
+ bs_notimpl_bs_sr_1,
+ bs_notimpl_bs_sr_2,
+ bs_notimpl_bs_sr_4,
+ bs_notimpl_bs_sr_8,
+
+ /* copy */
+ bs_notimpl_bs_c_1,
+ bs_notimpl_bs_c_2,
+ bs_notimpl_bs_c_4,
+ bs_notimpl_bs_c_8,
+
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+ /* read (single) */
+ a4x_bs_r_1,
+ NSWAP(a4x_bs_r_2),
+ NSWAP(a4x_bs_r_4),
+ bs_notimpl_bs_r_8,
+
+ /* read multiple */
+ a4x_bs_rm_1,
+ NSWAP(a4x_bs_rm_2),
+ NSWAP(a4x_bs_rm_4),
+ bs_notimpl_bs_rm_8,
+
+ /* read region */
+ a4x_bs_rr_1,
+ NSWAP(a4x_bs_rr_2),
+ NSWAP(a4x_bs_rr_4),
+ bs_notimpl_bs_rr_8,
+
+ /* write (single) */
+ a4x_bs_w_1,
+ NSWAP(a4x_bs_w_2),
+ NSWAP(a4x_bs_w_4),
+ bs_notimpl_bs_w_8,
+
+ /* write multiple */
+ a4x_bs_wm_1,
+ NSWAP(a4x_bs_wm_2),
+ NSWAP(a4x_bs_wm_4),
+ bs_notimpl_bs_wm_8,
+
+ /* write region */
+ a4x_bs_wr_1,
+ NSWAP(a4x_bs_wr_2),
+ NSWAP(a4x_bs_wr_4),
+ bs_notimpl_bs_wr_8,
+#endif
+};
+
+int
+tegra_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag,
+ bus_space_handle_t *bshp)
+{
+ u_long startpa, endpa, pa;
+ const struct pmap_devmap *pd;
+ vaddr_t va;
+
+ if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
+ /* Device was statically mapped. */
+ *bshp = pd->pd_va + (bpa - pd->pd_pa);
+ return 0;
+ }
+
+ startpa = trunc_page(bpa);
+ endpa = round_page(bpa + size);
+
+ /* XXX use extent manager to check duplicate mapping */
+
+ va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
+ UVM_KMF_VAONLY | UVM_KMF_NOWAIT | UVM_KMF_COLORMATCH);
+ if (!va)
+ return ENOMEM;
+
+ *bshp = (bus_space_handle_t)(va + (bpa - startpa));
+
+ const int pmapflags =
+ (flag & (BUS_SPACE_MAP_CACHEABLE|BUS_SPACE_MAP_PREFETCHABLE))
+ ? 0
+ : PMAP_NOCACHE;
+ for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
+ pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, pmapflags);
+ }
+ pmap_update(pmap_kernel());
+
+ return 0;
+}
+
+void
+tegra_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+ vaddr_t va;
+ vsize_t sz;
+
+ if (pmap_devmap_find_va(bsh, size) != NULL) {
+ /* Device was statically mapped; nothing to do. */
+ return;
+ }
+
+ va = trunc_page(bsh);
+ sz = round_page(bsh + size) - va;
+
+ pmap_kremove(va, sz);
+ pmap_update(pmap_kernel());
+ uvm_km_free(kernel_map, va, sz, UVM_KMF_VAONLY);
+}
+
+
+int
+tegra_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+ *nbshp = bsh + offset;
+ return (0);
+}
+
+int
+tegra_a4x_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+ *nbshp = bsh + 4 * offset;
+ return (0);
+}
+
+void
+tegra_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ bus_size_t len, int flags)
+{
+ flags &= BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE;
+
+ if (flags)
+ arm_dsb();
+}
+
+void *
+tegra_bs_vaddr(void *t, bus_space_handle_t bsh)
+{
+
+ return (void *)bsh;
+}
+
+paddr_t
+tegra_bs_mmap(void *t, bus_addr_t bpa, off_t offset, int prot, int flags)
+{
+ paddr_t bus_flags = 0;
+
+ if (flags & BUS_SPACE_MAP_PREFETCHABLE)
+ bus_flags |= ARM32_MMAP_WRITECOMBINE;
+
+ return (arm_btop(bpa + offset) | bus_flags);
+}
+
+paddr_t
+tegra_a4x_bs_mmap(void *t, bus_addr_t bpa, off_t offset, int prot, int flags)
+{
+ paddr_t bus_flags = 0;
+
+ if (flags & BUS_SPACE_MAP_PREFETCHABLE)
+ bus_flags |= ARM32_MMAP_WRITECOMBINE;
+
+ return (arm_btop(bpa + 4 * offset) | bus_flags);
+}
+
+int
+tegra_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
+ bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+ bus_addr_t *bpap, bus_space_handle_t *bshp)
+{
+
+ panic("%s(): not implemented\n", __func__);
+}
+
+void
+tegra_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+ panic("%s(): not implemented\n", __func__);
+}
Index: src/sys/arch/arm/nvidia/tegra_var.h
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_var.h:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_var.h Sun Mar 29 10:41:59 2015
@@ -0,0 +1,90 @@
+/* $NetBSD: tegra_var.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_TEGRA_VAR_H
+#define _ARM_TEGRA_VAR_H
+
+#include <sys/types.h>
+#include <sys/bus.h>
+
+#include "opt_tegra.h"
+
+struct tegra_locators {
+ const char *loc_name;
+ bus_addr_t loc_offset;
+ bus_size_t loc_size;
+ int loc_port;
+ int loc_intr;
+#define TEGRAIO_INTR_DEFAULT 0
+};
+
+struct tegraio_attach_args {
+ struct tegra_locators tio_loc;
+ bus_space_tag_t tio_bst;
+ bus_space_tag_t tio_a4x_bst;
+ bus_space_handle_t tio_bsh;
+ bus_dma_tag_t tio_dmat;
+};
+
+extern struct bus_space tegra_bs_tag;
+extern struct bus_space tegra_a4x_bs_tag;
+extern bus_space_handle_t tegra_host1x_bsh;
+extern bus_space_handle_t tegra_apb_bsh;
+extern bus_space_handle_t tegra_ahb_a2_bsh;
+extern struct arm32_bus_dma_tag tegra_dma_tag;
+
+#define CHIP_ID_TEGRA20 0x20
+#define CHIP_ID_TEGRA30 0x30
+#define CHIP_ID_TEGRA114 0x35
+#define CHIP_ID_TEGRA124 0x40
+#define CHIP_ID_TEGRA132 0x13
+
+u_int tegra_chip_id(void);
+const char *tegra_chip_name(void);
+void tegra_bootstrap(void);
+
+void tegra_pmc_reset(void);
+
+psize_t tegra_mc_memsize(void);
+
+#if defined(SOC_TEGRA124)
+void tegra124_mpinit(void);
+#endif
+
+static void inline
+tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
+ bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
+{
+ const uint32_t old = bus_space_read_4(bst, bsh, o);
+ const uint32_t new = set_mask | (old & ~clr_mask);
+ if (old != new) {
+ bus_space_write_4(bst, bsh, o, new);
+ }
+}
+
+#endif /* _ARM_TEGRA_VAR_H */
Index: src/sys/arch/evbarm/conf/JETSONTK1
diff -u /dev/null src/sys/arch/evbarm/conf/JETSONTK1:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/evbarm/conf/JETSONTK1 Sun Mar 29 10:41:59 2015
@@ -0,0 +1,237 @@
+#
+# $NetBSD: JETSONTK1,v 1.1 2015/03/29 10:41:59 jmcneill Exp $
+#
+# NVIDIA Jetson TK1 - Tegra K1 development kit
+# https://developer.nvidia.com/jetson-tk1
+#
+
+include "arch/evbarm/conf/std.tegra"
+
+# estimated number of users
+
+maxusers 32
+
+# Standard system options
+
+options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
+#options NTP # NTP phase/frequency locked loop
+
+# CPU options
+
+options CPU_CORTEXA15
+options SOC_TEGRA124
+options PMAPCOUNTERS
+
+# Architecture options
+
+# File systems
+
+file-system FFS # UFS
+#file-system LFS # log-structured file system
+file-system MFS # memory file system
+file-system NFS # Network file system
+#file-system ADOSFS # AmigaDOS-compatible file system
+#file-system EXT2FS # second extended file system (linux)
+#file-system CD9660 # ISO 9660 + Rock Ridge file system
+file-system MSDOSFS # MS-DOS file system
+#file-system FDESC # /dev/fd
+file-system KERNFS # /kern
+#file-system NULLFS # loopback file system
+file-system PROCFS # /proc
+#file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs)
+#file-system UMAPFS # NULLFS + uid and gid remapping
+#file-system UNION # union file system
+file-system TMPFS # memory file system
+file-system PTYFS # /dev/pts/N support
+
+# File system options
+#options QUOTA # legacy UFS quotas
+#options QUOTA2 # new, in-filesystem UFS quotas
+#options FFS_EI # FFS Endian Independant support
+#options NFSSERVER
+#options WAPBL # File system journaling support - Experimental
+#options FFS_NO_SNAPSHOT # No FFS snapshot support
+
+# Networking options
+
+#options GATEWAY # packet forwarding
+options INET # IP + ICMP + TCP + UDP
+options INET6 # IPV6
+#options IPSEC # IP security
+#options IPSEC_DEBUG # debug for IP security
+#options MROUTING # IP multicast routing
+#options PIM # Protocol Independent Multicast
+#options NETATALK # AppleTalk networking
+#options PPP_BSDCOMP # BSD-Compress compression support for PPP
+#options PPP_DEFLATE # Deflate compression support for PPP
+#options PPP_FILTER # Active filter support for PPP (requires bpf)
+#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
+
+options NFS_BOOT_BOOTP
+#options NFS_BOOT_DHCP
+#options NFS_BOOT_BOOTSTATIC
+#options NFS_BOOTSTATIC_MYIP="\"192.168.1.4\""
+#options NFS_BOOTSTATIC_GWIP="\"192.168.1.1\""
+#options NFS_BOOTSTATIC_MASK="\"255.255.255.0\""
+#options NFS_BOOTSTATIC_SERVADDR="\"192.168.1.1\""
+#options NFS_BOOTSTATIC_SERVER="\"192.168.1.1:/nfs/sdp2430\""
+
+options NFS_BOOT_RWSIZE=1024
+
+# Compatibility options
+
+#options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries
+#options COMPAT_43 # 4.3BSD compatibility.
+#options COMPAT_09 # NetBSD 0.9,
+#options COMPAT_10 # NetBSD 1.0,
+#options COMPAT_11 # NetBSD 1.1,
+#options COMPAT_12 # NetBSD 1.2,
+#options COMPAT_13 # NetBSD 1.3,
+#options COMPAT_14 # NetBSD 1.4,
+#options COMPAT_15 # NetBSD 1.5,
+#options COMPAT_16 # NetBSD 1.6,
+#options COMPAT_20 # NetBSD 2.0,
+#options COMPAT_30 # NetBSD 3.0,
+#options COMPAT_40 # NetBSD 4.0,
+#options COMPAT_50 # NetBSD 5.0,
+#options COMPAT_60 # NetBSD 6.0, and
+options COMPAT_70 # NetBSD 7.0 binary compatibility.
+#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
+#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
+
+# Shared memory options
+
+options SYSVMSG # System V-like message queues
+options SYSVSEM # System V-like semaphores
+#options SEMMNI=10 # number of semaphore identifiers
+#options SEMMNS=60 # number of semaphores in system
+#options SEMUME=10 # max number of undo entries per process
+#options SEMMNU=30 # number of undo structures in system
+options SYSVSHM # System V-like memory sharing
+
+# Device options
+
+#options MEMORY_DISK_HOOKS # boottime setup of ramdisk
+#options MEMORY_DISK_ROOT_SIZE=8192 # Size in blocks
+#options MEMORY_DISK_DYNAMIC
+#options MINIROOTSIZE=1000 # Size in blocks
+#options MEMORY_DISK_IS_ROOT # use memory disk as root
+#options MEMORY_DISK_FBFLAGS=RB_SINGLE
+
+# Miscellaneous kernel options
+options KTRACE # system call tracing, a la ktrace(1)
+#options KMEMSTATS # kernel memory statistics
+#options SCSIVERBOSE # Verbose SCSI errors
+#options MIIVERBOSE # Verbose MII autoconfuration messages
+#options DDB_KEYCODE=0x40
+#options USERCONF # userconf(4) support
+#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
+
+# Alternate buffer queue strategies for better responsiveness under high
+# disk I/O load.
+#options BUFQ_READPRIO
+options BUFQ_PRIOCSCAN
+
+# Development and Debugging options
+
+#options PERFCTRS # performance counters
+options DIAGNOSTIC # internal consistency checks
+options DEBUG
+options LOCKDEBUG
+#options PMAP_DEBUG # Enable pmap_debug_level code
+#options IPKDB # remote kernel debugging
+options VERBOSE_INIT_ARM # verbose bootstraping messages
+options DDB # in-kernel debugger
+options DDB_ONPANIC=1
+options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
+options DDB_COMMANDONENTER="bt"
+#options KGDB
+makeoptions DEBUG="-g" # compile full symbol table
+makeoptions COPY_SYMTAB=1
+
+options BOOT_ARGS="\"\""
+
+config netbsd root on ? type ?
+
+# The main bus device
+mainbus0 at root
+
+# The boot cpu
+cpu* at mainbus?
+options MULTIPROCESSOR
+
+# A5 core devices
+armperiph0 at mainbus?
+armgic0 at armperiph? # Interrupt Controller
+armgtmr0 at armperiph? # ARM Generic Timer
+
+# Specify the memory size in megabytes.
+#options MEMSIZE=2048
+
+# On-board I/O
+tegraio0 at mainbus?
+
+# Memory controller
+tegramc0 at tegraio? # MC
+
+# Power management controller
+tegrapmc0 at tegraio? # PMC
+
+# UART
+com3 at tegraio? port 3 # UART-D
+options CONSADDR=0x70006300, CONSPEED=115200
+
+# SDMMC
+sdhc2 at tegraio? port 2 # SDMMC3 (SD card)
+sdmmc2 at sdhc2
+sdhc3 at tegraio? port 3 # SDMMC4 (eMMC)
+sdmmc3 at sdhc3
+
+ld0 at sdmmc3 # eMMC
+ld1 at sdmmc2 # SD card
+
+# SATA
+ahcisata0 at tegraio? # SATA
+atabus* at ata?
+atapibus* at atapi?
+wd* at atabus? drive ?
+cd* at atapibus? drive ?
+
+# HDA
+hdaudio* at tegraio? # HDA
+hdafg* at hdaudiobus?
+audio* at audiobus?
+options HDAUDIO_ENABLE_HDMI
+options HDAUDIO_ENABLE_DISPLAYPORT
+
+# USB 2.0
+ehci0 at tegraio? port 0 # USB1
+ehci1 at tegraio? port 1 # USB2
+ehci2 at tegraio? port 2 # USB3
+usb* at ehci?
+
+include "dev/usb/usbdevices.config"
+midi* at midibus?
+
+# Pseudo-Devices
+
+# disk/mass storage pseudo-devices
+#pseudo-device md # memory disk device (ramdisk)
+pseudo-device vnd # disk-like interface to files
+#pseudo-device fss # file system snapshot device
+pseudo-device drvctl # driver control
+#pseudo-device putter # for puffs and pud
+
+# network pseudo-devices
+pseudo-device bpfilter # Berkeley packet filter
+pseudo-device loop # network loopback
+#pseudo-device kttcp # network loopback
+
+# miscellaneous pseudo-devices
+pseudo-device pty # pseudo-terminals
+#options RND_COM
+#pseudo-device clockctl # user control of clock subsystem
+pseudo-device ksyms # /dev/ksyms
+pseudo-device lockstat # lock profiling
+
+cinclude "arch/evbarm/conf/JETSONTK1.local"
Index: src/sys/arch/evbarm/conf/files.tegra
diff -u /dev/null src/sys/arch/evbarm/conf/files.tegra:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/evbarm/conf/files.tegra Sun Mar 29 10:41:59 2015
@@ -0,0 +1,10 @@
+# $NetBSD: files.tegra,v 1.1 2015/03/29 10:41:59 jmcneill Exp $
+#
+# NVIDIA Tegra configuration info
+#
+
+file arch/evbarm/tegra/tegra_machdep.c
+
+defparam opt_machdep.h BOOT_ARGS
+
+include "arch/arm/nvidia/files.tegra"
Index: src/sys/arch/evbarm/conf/mk.tegra
diff -u /dev/null src/sys/arch/evbarm/conf/mk.tegra:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/evbarm/conf/mk.tegra Sun Mar 29 10:41:59 2015
@@ -0,0 +1,33 @@
+# $NetBSD: mk.tegra,v 1.1 2015/03/29 10:41:59 jmcneill Exp $
+CPPFLAGS+= -mcpu=cortex-a15 -mfpu=neon
+
+SYSTEM_FIRST_OBJ= tegra_start.o
+SYSTEM_FIRST_SFILE= ${THISARM}/tegra/tegra_start.S
+
+GENASSYM_EXTRAS+= ${THISARM}/tegra/genassym.cf
+
+_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
+
+MKUBOOTIMAGEARGS= -A arm -T kernel
+MKUBOOTIMAGEARGS+= -a $(KERNEL_BASE_PHYS) -e $(KERNEL_BASE_PHYS)
+MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
+MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
+MKUBOOTIMAGEARGS_GZ= ${MKUBOOTIMAGEARGS} -C gz
+
+KERNEL_BASE_PHYS=0x81000000
+KERNEL_BASE_VIRT=0x81000000
+
+SYSTEM_LD_TAIL_EXTRA+=; \
+ echo ${OBJCOPY} -S -O binary $@ [email protected]; \
+ ${OBJCOPY} -S -O binary $@ [email protected]; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} [email protected] [email protected]; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} [email protected] [email protected]; \
+ echo ${TOOL_GZIP} -c [email protected] > [email protected]; \
+ ${TOOL_GZIP} -c [email protected] > [email protected]; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} [email protected] [email protected]; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} [email protected] [email protected]
+
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.ub@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin.gz@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.gz.ub@}
Index: src/sys/arch/evbarm/conf/std.tegra
diff -u /dev/null src/sys/arch/evbarm/conf/std.tegra:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/evbarm/conf/std.tegra Sun Mar 29 10:41:59 2015
@@ -0,0 +1,26 @@
+# $NetBSD: std.tegra,v 1.1 2015/03/29 10:41:59 jmcneill Exp $
+#
+
+machine evbarm arm
+include "arch/evbarm/conf/std.evbarm"
+
+include "arch/evbarm/conf/files.tegra"
+
+options MODULAR
+options MODULAR_DEFAULT_AUTOLOAD
+options __HAVE_CPU_COUNTER
+options CORTEX_PMC
+options __HAVE_FAST_SOFTINTS # should be in types.h
+options ARM_HAS_VBAR
+options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+options TPIDRPRW_IS_CURCPU
+options KERNEL_BASE_EXT=0x80000000
+options FPU_VFP
+
+makeoptions KERNEL_BASE_PHYS="0x81000000"
+makeoptions KERNEL_BASE_VIRT="0x81000000"
+makeoptions BOARDTYPE="tegra"
+makeoptions BOARDMKFRAG="${THISARM}/conf/mk.tegra"
+
+options ARM_INTR_IMPL="<arch/arm/nvidia/tegra_intr.h>"
+options ARM_GENERIC_TODR
Index: src/sys/arch/evbarm/tegra/genassym.cf
diff -u /dev/null src/sys/arch/evbarm/tegra/genassym.cf:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/evbarm/tegra/genassym.cf Sun Mar 29 10:41:59 2015
@@ -0,0 +1,38 @@
+# $NetBSD: genassym.cf,v 1.1 2015/03/29 10:41:59 jmcneill Exp $
+
+#-
+# Copyright (c) 2013 The NetBSD Foundation, Inc.
+# All rights reserved.
+#
+# This code is derived from software contributed to The NetBSD Foundation
+# by Matt Thomas of 3am Software Foundry.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include <dev/ic/ns16550reg.h>
+include <dev/ic/comreg.h>
+
+define LSR_TXRDY LSR_TXRDY
+define LSR_TSRE LSR_TSRE
+define COM_DATA com_data
+define COM_LSR com_lsr
Index: src/sys/arch/evbarm/tegra/platform.h
diff -u /dev/null src/sys/arch/evbarm/tegra/platform.h:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/evbarm/tegra/platform.h Sun Mar 29 10:41:59 2015
@@ -0,0 +1,39 @@
+/* $NetBSD: platform.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _EVBARM_TEGRA_PLATFORM_H
+#define _EVBARM_TEGRA_PLATFORM_H
+
+#include <arm/nvidia/tegra_reg.h>
+
+#define KERNEL_VM_BASE 0xc0000000
+#define KERNEL_VM_SIZE 0x20000000 /* 0x20000000 = 512MB */
+
+#define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE)
+
+#endif /* _EVBARM_TEGRA_PLATFORM_H */
Index: src/sys/arch/evbarm/tegra/tegra_machdep.c
diff -u /dev/null src/sys/arch/evbarm/tegra/tegra_machdep.c:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/evbarm/tegra/tegra_machdep.c Sun Mar 29 10:41:59 2015
@@ -0,0 +1,330 @@
+/* $NetBSD: tegra_machdep.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_machdep.c,v 1.1 2015/03/29 10:41:59 jmcneill Exp $");
+
+#include "opt_tegra.h"
+#include "opt_machdep.h"
+#include "opt_ddb.h"
+#include "opt_md.h"
+#include "opt_arm_debug.h"
+#include "opt_multiprocessor.h"
+
+#include "com.h"
+#include "ukbd.h"
+#include "genfb.h"
+#include "ether.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/atomic.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/exec.h>
+#include <sys/kernel.h>
+#include <sys/ksyms.h>
+#include <sys/msgbuf.h>
+#include <sys/proc.h>
+#include <sys/reboot.h>
+#include <sys/termios.h>
+#include <sys/gpio.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <sys/conf.h>
+#include <dev/cons.h>
+#include <dev/md.h>
+
+#include <machine/db_machdep.h>
+#include <ddb/db_sym.h>
+#include <ddb/db_extern.h>
+
+#include <machine/bootconfig.h>
+#include <arm/armreg.h>
+#include <arm/undefined.h>
+
+#include <arm/arm32/machdep.h>
+#include <arm/mainbus/mainbus.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#include <arm/cortex/gtmr_var.h>
+
+#include <evbarm/include/autoconf.h>
+#include <evbarm/tegra/platform.h>
+
+#include <dev/ic/ns16550reg.h>
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+#include <dev/usb/ukbdvar.h>
+#include <net/if_ether.h>
+
+#ifndef TEGRA_MAX_BOOT_STRING
+#define TEGRA_MAX_BOOT_STRING 1024
+#endif
+
+BootConfig bootconfig;
+static char bootargs[TEGRA_MAX_BOOT_STRING];
+char *boot_args = NULL;
+u_int uboot_args[4] = { 0 }; /* filled in by tegra_start.S (not in bss) */
+
+extern char KERNEL_BASE_phys[];
+#define KERNEL_BASE_PHYS ((paddr_t)KERNEL_BASE_phys)
+
+static void tegra_device_register(device_t, void *);
+
+bs_protos(bs_notimpl);
+
+#define _A(a) ((a) & ~L1_S_OFFSET)
+#define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1))
+
+static const struct pmap_devmap devmap[] = {
+ {
+ .pd_va = _A(TEGRA_HOST1X_VBASE),
+ .pd_pa = _A(TEGRA_HOST1X_BASE),
+ .pd_size = _S(TEGRA_HOST1X_SIZE),
+ .pd_prot = VM_PROT_READ|VM_PROT_WRITE,
+ .pd_cache = PTE_NOCACHE
+ },
+ {
+ .pd_va = _A(TEGRA_APB_VBASE),
+ .pd_pa = _A(TEGRA_APB_BASE),
+ .pd_size = _S(TEGRA_APB_SIZE),
+ .pd_prot = VM_PROT_READ|VM_PROT_WRITE,
+ .pd_cache = PTE_NOCACHE
+ },
+ {0}
+};
+
+#undef _A
+#undef _S
+
+#ifdef VERBOSE_INIT_ARM
+static void
+tegra_putchar(char c)
+{
+ volatile uint32_t *uartaddr = (volatile uint32_t *)CONSADDR_VA;
+ int timo = 150000;
+
+ while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) {
+ if (--timo == 0)
+ break;
+ }
+
+ uartaddr[com_data] = c;
+
+ while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) {
+ if (--timo == 0)
+ break;
+ }
+}
+static void
+tegra_putstr(const char *s)
+{
+ for (const char *p = s; *p; p++) {
+ tegra_putchar(*p);
+ }
+}
+#define DPRINTF(...) printf(__VA_ARGS__)
+#define DPRINT(x) tegra_putstr(x)
+#else
+#define DPRINTF(...)
+#define DPRINT(x)
+#endif
+
+/*
+ * u_int initarm(...)
+ *
+ * Initial entry point on startup. This gets called before main() is
+ * entered.
+ * It should be responsible for setting up everything that must be
+ * in place when main is called.
+ * This includes
+ * Taking a copy of the boot configuration structure.
+ * Initialising the physical console so characters can be printed.
+ * Setting up page tables for the kernel
+ * Relocating the kernel to the bottom of physical memory
+ */
+u_int
+initarm(void *arg)
+{
+ psize_t ram_size = 0;
+ DPRINT("initarm:");
+
+ DPRINT(" devmap");
+ pmap_devmap_register(devmap);
+
+ DPRINT(" bootstrap");
+ tegra_bootstrap();
+
+#ifdef MULTIPROCESSOR
+ DPRINT(" ncpu");
+ arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
+#endif
+
+ /* Heads up ... Setup the CPU / MMU / TLB functions. */
+ DPRINT(" cpufunc");
+ if (set_cpufuncs())
+ panic("cpu not recognized!");
+
+ DPRINT(" consinit");
+ consinit();
+
+ DPRINTF(" cbar=%#x", armreg_cbar_read());
+
+ DPRINTF(" ok\n");
+
+ DPRINTF("uboot: args %#x, %#x, %#x, %#x\n",
+ uboot_args[0], uboot_args[1], uboot_args[2], uboot_args[3]);
+
+ cpu_reset_address = tegra_pmc_reset;
+
+ /* Talk to the user */
+ DPRINTF("\nNetBSD/evbarm (tegra) booting ...\n");
+
+#ifdef BOOT_ARGS
+ char mi_bootargs[] = BOOT_ARGS;
+ parse_mi_bootargs(mi_bootargs);
+#endif
+
+ DPRINTF("KERNEL_BASE=0x%x, KERNEL_VM_BASE=0x%x, KERNEL_VM_BASE - KERNEL_BASE=0x%x, KERNEL_BASE_VOFFSET=0x%x\n",
+ KERNEL_BASE, KERNEL_VM_BASE, KERNEL_VM_BASE - KERNEL_BASE, KERNEL_BASE_VOFFSET);
+
+ ram_size = tegra_mc_memsize();
+
+#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+ if (ram_size > KERNEL_VM_BASE - KERNEL_BASE) {
+ printf("%s: dropping RAM size from %luMB to %uMB\n",
+ __func__, (unsigned long) (ram_size >> 20),
+ (KERNEL_VM_BASE - KERNEL_BASE) >> 20);
+ ram_size = KERNEL_VM_BASE - KERNEL_BASE;
+ }
+#endif
+
+ /*
+ * If MEMSIZE specified less than what we really have, limit ourselves
+ * to that.
+ */
+#ifdef MEMSIZE
+ if (ram_size == 0 || ram_size > (unsigned)MEMSIZE * 1024 * 1024)
+ ram_size = (unsigned)MEMSIZE * 1024 * 1024;
+ DPRINTF("ram_size = 0x%x\n", (int)ram_size);
+#else
+ KASSERTMSG(ram_size > 0, "RAM size unknown and MEMSIZE undefined");
+#endif
+
+ /* Fake bootconfig structure for the benefit of pmap.c. */
+ bootconfig.dramblocks = 1;
+ bootconfig.dram[0].address = TEGRA_EXTMEM_BASE; /* DDR PHY addr */
+ bootconfig.dram[0].pages = ram_size / PAGE_SIZE;
+
+#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+ const bool mapallmem_p = true;
+ KASSERT(ram_size <= KERNEL_VM_BASE - KERNEL_BASE);
+#else
+ const bool mapallmem_p = false;
+#endif
+ KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0);
+
+ arm32_bootmem_init(bootconfig.dram[0].address, ram_size,
+ KERNEL_BASE_PHYS);
+ arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap,
+ mapallmem_p);
+
+ if (mapallmem_p) {
+ if (uboot_args[3] < ram_size) {
+ const char * const args = (const char *)
+ (uboot_args[3] + KERNEL_BASE_VOFFSET);
+ strlcpy(bootargs, args, sizeof(bootargs));
+ }
+ }
+
+ DPRINTF("bootargs: %s\n", bootargs);
+
+ boot_args = bootargs;
+ parse_mi_bootargs(boot_args);
+
+ evbarm_device_register = tegra_device_register;
+
+ return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+
+}
+
+#if NCOM > 0
+#ifndef CONSADDR
+#error Specify the address of the console UART with the CONSADDR option.
+#endif
+#ifndef CONSPEED
+#define CONSPEED 115200
+#endif
+#ifndef CONMODE
+#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
+#endif
+#endif
+
+void
+consinit(void)
+{
+ static bool consinit_called = false;
+
+ if (consinit_called)
+ return;
+ consinit_called = true;
+
+#if NCOM > 0
+ const bus_space_tag_t bst = &tegra_a4x_bs_tag;
+ if (comcnattach(bst, CONSADDR, CONSPEED, TEGRA_UART_FREQ,
+ COM_TYPE_NORMAL, CONMODE)) {
+ panic("Serial console cannot be initialized.");
+ }
+#else
+#error only COM console is supported
+#endif
+}
+
+void
+tegra_device_register(device_t self, void *aux)
+{
+ prop_dictionary_t dict = device_properties(self);
+
+ if (device_is_a(self, "armperiph")
+ && device_is_a(device_parent(self), "mainbus")) {
+ struct mainbus_attach_args * const mb = aux;
+ mb->mb_iot = &tegra_bs_tag;
+ return;
+ }
+
+ if (device_is_a(self, "armgtmr")) {
+ prop_dictionary_set_uint32(dict, "frequency", TEGRA_REF_FREQ);
+ return;
+ }
+}
Index: src/sys/arch/evbarm/tegra/tegra_start.S
diff -u /dev/null src/sys/arch/evbarm/tegra/tegra_start.S:1.1
--- /dev/null Sun Mar 29 10:41:59 2015
+++ src/sys/arch/evbarm/tegra/tegra_start.S Sun Mar 29 10:41:59 2015
@@ -0,0 +1,181 @@
+/* $NetBSD: tegra_start.S,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014, 2015 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "opt_tegra.h"
+#include "opt_com.h"
+#include "opt_cpuoptions.h"
+#include "opt_cputypes.h"
+#include "opt_multiprocessor.h"
+#include "opt_arm_debug.h"
+
+#include <arm/asm.h>
+#include <arm/armreg.h>
+#include "assym.h"
+
+#include <arm/nvidia/tegra_reg.h>
+#include <evbarm/tegra/platform.h>
+
+RCSID("$NetBSD: tegra_start.S,v 1.1 2015/03/29 10:41:59 jmcneill Exp $")
+
+#if defined(VERBOSE_INIT_ARM)
+#define XPUTC(n) mov r0, n; bl xputc
+#if KERNEL_BASE_VOFFSET == 0
+#define XPUTC2(n) mov r0, n; bl xputc
+#else
+#define XPUTC2(n) mov r0, n; blx r11
+#endif
+#ifdef __ARMEB__
+#define COM_BSWAP
+#endif
+#define COM_MULT 4
+#define XPUTC_COM 1
+#else
+#define XPUTC(n)
+#define XPUTC2(n)
+#endif
+
+#define INIT_MEMSIZE 128
+#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
+
+#define MD_CPU_HATCH _C_LABEL(gtmr_init_cpu_clock)
+
+#if defined(SOC_TEGRA124)
+#define SOC_MPINIT _C_LABEL(tegra124_mpinit)
+#endif
+
+/*
+ * Kernel start routine for Tegra 124 SoC.
+ * At this point, this code has been loaded into SDRAM
+ * and the MMU maybe on or maybe off.
+ */
+#ifdef KERNEL_BASES_EQUAL
+ .text
+#else
+ .section .start,"ax",%progbits
+#endif
+
+ .global _C_LABEL(tegra_start)
+_C_LABEL(tegra_start):
+#ifdef __ARMEB__
+ setend be /* force big endian */
+#endif
+ mov r9, #0
+
+ /* Move into supervisor mode and disable IRQs/FIQs. */
+ cpsid if, #PSR_SVC32_MODE
+
+ /*
+ * Save any arguments passed to us.
+ */
+ movw r4, #:lower16:uboot_args
+ movt r4, #:upper16:uboot_args
+ sub r4, r4, #KERNEL_BASE_VOFFSET
+
+ stmia r4, {r0-r3} // Save the arguments
+
+ /*
+ * Turn on the SMP bit
+ */
+ bl cortex_init
+
+ /*
+ * Set up a preliminary mapping in the MMU to allow us to run
+ * at KERNEL_BASE with caches on.
+ */
+ movw r0, #:lower16:TEMP_L1_TABLE
+ movt r0, #:upper16:TEMP_L1_TABLE
+ movw r1, #:lower16:mmu_init_table
+ movt r1, #:upper16:mmu_init_table
+ bl arm_boot_l1pt_init
+ XPUTC(#68)
+
+ /*
+ * Turn on the MMU, Caches, etc. Return to new enabled address space.
+ */
+ movw r0, #:lower16:TEMP_L1_TABLE
+ movt r0, #:upper16:TEMP_L1_TABLE
+#if KERNEL_BASE_VOFFSET == 0
+ bl arm_cpuinit
+#else
+ /*
+ * After the MMU is on, we can execute in the normal .text segment
+ * so setup the lr to be in .text. Cache the address for xputc
+ * before we go.
+ */
+#if defined(VERBOSE_INIT_ARM)
+ adr r11, xputc @ for XPUTC2
+#endif
+ movw lr, #:lower16:1f
+ movt lr, #:upper16:1f
+ b arm_cpuinit
+ .pushsection .text,"ax",%progbits
+1:
+#endif
+ XPUTC2(#90)
+
+ /*
+ * Jump to start in locore.S, which in turn will call initarm and main.
+ */
+ b start
+
+ /* NOTREACHED */
+
+#ifndef KERNEL_BASES_EQUAL
+ .popsection
+#endif
+
+#include <arm/cortex/a9_mpsubr.S>
+
+mmu_init_table:
+ MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
+
+#if KERNEL_BASE_VOFFSET != 0
+ /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
+ MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
+ KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
+#endif
+
+ /* Map APB */
+ MMU_INIT(TEGRA_APB_VBASE, TEGRA_APB_BASE,
+ (TEGRA_APB_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+
+ /* Map APB */
+ MMU_INIT(TEGRA_APB_BASE, TEGRA_APB_BASE,
+ (TEGRA_APB_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+
+ /* end of table */
+ MMU_INIT(0, 0, 0, 0)
+
+END(_C_LABEL(tegra_start))
