Module Name: src
Committed By: jmcneill
Date: Fri May 15 11:49:11 UTC 2015
Modified Files:
src/sys/arch/arm/nvidia: files.tegra tegra_io.c
Added Files:
src/sys/arch/arm/nvidia: tegra_xusbpad.c tegra_xusbpadreg.h
Log Message:
Tegra XUSB PADCTL driver
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/nvidia/files.tegra
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/nvidia/tegra_io.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/nvidia/tegra_xusbpad.c \
src/sys/arch/arm/nvidia/tegra_xusbpadreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/files.tegra
diff -u src/sys/arch/arm/nvidia/files.tegra:1.10 src/sys/arch/arm/nvidia/files.tegra:1.11
--- src/sys/arch/arm/nvidia/files.tegra:1.10 Wed May 13 11:06:13 2015
+++ src/sys/arch/arm/nvidia/files.tegra Fri May 15 11:49:10 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.10 2015/05/13 11:06:13 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.11 2015/05/15 11:49:10 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -47,6 +47,11 @@ device tegrampio
attach tegrampio at tegraio with tegra_mpio
file arch/arm/nvidia/tegra_mpio.c tegra_mpio
+# XUSB PADCTL
+device tegraxusbpad
+attach tegraxusbpad at tegraio with tegra_xusbpad
+file arch/arm/nvidia/tegra_xusbpad.c tegra_xusbpad
+
# UART
attach com at tegraio with tegra_com
file arch/arm/nvidia/tegra_com.c tegra_com needs-flag
Index: src/sys/arch/arm/nvidia/tegra_io.c
diff -u src/sys/arch/arm/nvidia/tegra_io.c:1.8 src/sys/arch/arm/nvidia/tegra_io.c:1.9
--- src/sys/arch/arm/nvidia/tegra_io.c:1.8 Sun May 10 23:50:21 2015
+++ src/sys/arch/arm/nvidia/tegra_io.c Fri May 15 11:49:10 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_io.c,v 1.8 2015/05/10 23:50:21 jmcneill Exp $ */
+/* $NetBSD: tegra_io.c,v 1.9 2015/05/15 11:49:10 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.8 2015/05/10 23:50:21 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.9 2015/05/15 11:49:10 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -73,6 +73,8 @@ static const struct tegra_locators tegra
TEGRA_MC_OFFSET, TEGRA_MC_SIZE, NOPORT, NOINTR },
{ "tegrapmc",
TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, NOPORT, NOINTR },
+ { "tegraxusbpad",
+ TEGRA_XUSB_PADCTL_OFFSET, TEGRA_XUSB_PADCTL_SIZE, NOPORT, NOINTR },
{ "tegrampio",
TEGRA_MPIO_OFFSET, TEGRA_MPIO_SIZE, NOPORT, NOINTR },
{ "tegrai2c",
Added files:
Index: src/sys/arch/arm/nvidia/tegra_xusbpad.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_xusbpad.c:1.1
--- /dev/null Fri May 15 11:49:11 2015
+++ src/sys/arch/arm/nvidia/tegra_xusbpad.c Fri May 15 11:49:10 2015
@@ -0,0 +1,136 @@
+/* $NetBSD: tegra_xusbpad.c,v 1.1 2015/05/15 11:49:10 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_xusbpad.c,v 1.1 2015/05/15 11:49:10 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_xusbpadreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+static int tegra_xusbpad_match(device_t, cfdata_t, void *);
+static void tegra_xusbpad_attach(device_t, device_t, void *);
+
+struct tegra_xusbpad_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
+
+static struct tegra_xusbpad_softc *xusbpad_softc = NULL;
+
+CFATTACH_DECL_NEW(tegra_xusbpad, sizeof(struct tegra_xusbpad_softc),
+ tegra_xusbpad_match, tegra_xusbpad_attach, NULL, NULL);
+
+static int
+tegra_xusbpad_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+tegra_xusbpad_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_xusbpad_softc * const sc = device_private(self);
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+
+ sc->sc_dev = self;
+ sc->sc_bst = tio->tio_bst;
+ bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
+ KASSERT(xusbpad_softc == NULL);
+ xusbpad_softc = sc;
+
+ aprint_naive("\n");
+ aprint_normal(": XUSB PADCTL\n");
+
+}
+
+static void
+tegra_xusbpad_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
+{
+ if (xusbpad_softc) {
+ *pbst = xusbpad_softc->sc_bst;
+ *pbsh = xusbpad_softc->sc_bsh;
+ } else {
+ *pbst = &armv7_generic_bs_tag;
+ bus_space_subregion(*pbst, tegra_apb_bsh,
+ TEGRA_XUSB_PADCTL_OFFSET, TEGRA_XUSB_PADCTL_SIZE, pbsh);
+ }
+}
+
+void
+tegra_xusbpad_sata_enable(void)
+{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+ int retry;
+
+ tegra_xusbpad_get_bs(&bst, &bsh);
+
+ tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_USB3_PAD_MUX_REG,
+ __SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA,
+ XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0) |
+ XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0,
+ XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0);
+
+ tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG,
+ 0,
+ XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ |
+ XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD);
+ tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
+ 0,
+ XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ |
+ XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD);
+ tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
+ XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE, 0);
+ tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
+ XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST, 0);
+
+ for (retry = 1000; retry > 0; retry--) {
+ const uint32_t v = bus_space_read_4(bst, bsh,
+ XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG);
+ if (v & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)
+ break;
+ delay(100);
+ }
+ if (retry == 0) {
+ printf("WARNING: SATA PHY power-on failed\n");
+ }
+}
Index: src/sys/arch/arm/nvidia/tegra_xusbpadreg.h
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_xusbpadreg.h:1.1
--- /dev/null Fri May 15 11:49:11 2015
+++ src/sys/arch/arm/nvidia/tegra_xusbpadreg.h Fri May 15 11:49:10 2015
@@ -0,0 +1,136 @@
+/* $NetBSD: tegra_xusbpadreg.h,v 1.1 2015/05/15 11:49:10 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_TEGRA_XUSBPADCTLREG_H
+#define _ARM_TEGRA_XUSBPADCTLREG_H
+
+#define XUSB_PADCTL_BOOT_MEDIA_REG 0x000
+#define XUSB_PADCTL_USB2_PAD_MUX_REG 0x004
+#define XUSB_PADCTL_USB2_PORT_CAP_REG 0x008
+#define XUSB_PADCTL_SNPS_OC_MAP_REG 0x00c
+#define XUSB_PADCTL_USB2_OC_MAP_REG 0x010
+#define XUSB_PADCTL_SS_PORT_MAP_REG 0x014
+#define XUSB_PADCTL_OC_DET_REG 0x018
+#define XUSB_PADCTL_ELPG_PROGRAM_REG 0x01c
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_REG 0x020
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_REG 0x024
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_REG 0x028
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_REG 0x02c
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_REG 0x030
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_REG 0x034
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_REG 0x038
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_REG 0x03c
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REG 0x040
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REG 0x044
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL3_REG 0x048
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL4_REG 0x04c
+#define XUSB_PADCTL_IOPHY_USB3_PAD0_CTL1_REG 0x050
+#define XUSB_PADCTL_IOPHY_USB3_PAD1_CTL1_REG 0x054
+#define XUSB_PADCTL_IOPHY_USB3_PAD0_CTL2_REG 0x058
+#define XUSB_PADCTL_IOPHY_USB3_PAD1_CTL2_REG 0x05c
+#define XUSB_PADCTL_IOPHY_USB3_PAD0_CTL3_REG 0x060
+#define XUSB_PADCTL_IOPHY_USB3_PAD1_CTL3_REG 0x064
+#define XUSB_PADCTL_IOPHY_USB3_PAD0_CTL4_REG 0x068
+#define XUSB_PADCTL_IOPHY_USB3_PAD1_CTL4_REG 0x06c
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL1_REG 0x070
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL1_REG 0x074
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL2_REG 0x078
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL2_REG 0x07c
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL3_REG 0x080
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL3_REG 0x084
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL4_REG 0x088
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL4_REG 0x08c
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL5_REG 0x090
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL5_REG 0x094
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL6_REG 0x098
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL6_REG 0x09c
+#define XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG 0x0a0
+#define XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG 0x0a4
+#define XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG 0x0a8
+#define XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG 0x0ac
+#define XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG 0x0b0
+#define XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG 0x0b4
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG 0x0b8
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_REG 0x0bc
+#define XUSB_PADCTL_HSIC_PAD0_CTL0_REG 0x0c0
+#define XUSB_PADCTL_HSIC_PAD1_CTL0_REG 0x0c4
+#define XUSB_PADCTL_HSIC_PAD0_CTL1_REG 0x0c8
+#define XUSB_PADCTL_HSIC_PAD1_CTL1_REG 0x0cc
+#define XUSB_PADCTL_HSIC_PAD0_CTL2_REG 0x0d0
+#define XUSB_PADCTL_HSIC_PAD1_CTL2_REG 0x0d4
+#define XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_REG 0x0d8
+#define XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_REG 0x0dc
+#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_REG 0x0e0
+#define XUSB_PADCTL_WAKE_CTRL_REG 0x0e4
+#define XUSB_PADCTL_PM_SPARE_REG 0x0e8
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL1_REG 0x0ec
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL1_REG 0x0f0
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL1_REG 0x0f4
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL2_REG 0x0f8
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL2_REG 0x0fc
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL2_REG 0x100
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL3_REG 0x104
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL3_REG 0x108
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL3_REG 0x10c
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL4_REG 0x110
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL4_REG 0x114
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL4_REG 0x118
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL5_REG 0x11c
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL5_REG 0x120
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL5_REG 0x124
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P2_CTL6_REG 0x128
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL6_REG 0x12c
+#define XUSB_PADCTL_IOPHY_MISC_PAD_P4_CTL6_REG 0x130
+#define XUSB_PADCTL_USB3_PAD_MUX_REG 0x134
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG 0x138
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_REG 0x13c
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL3_REG 0x140
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL4_REG 0x144
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG 0x148
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2_REG 0x14c
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3_REG 0x150
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4_REG 0x154
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5_REG 0x158
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6_REG 0x15c
+
+#define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0 __BITS(27,26)
+#define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_PCIE 0
+#define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_USB3_SS 1
+#define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA 2
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 __BIT(6)
+
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET __BIT(27)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE __BIT(24)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD __BIT(3)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST __BIT(1)
+#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ __BIT(0)
+
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD __BIT(1)
+#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ __BIT(0)
+
+#endif /* _ARM_TEGRA_XUSBPADCTLREG_H */
